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Tue, 10 Mar 2026 02:49:52 -0700 (PDT) From: Colin Huang Date: Tue, 10 Mar 2026 17:49:36 +0800 Subject: [PATCH v3 2/3] ARM: dts: aspeed: anacapa: update SGPIO mappings for DFT integration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260310-anacapa-dts-sgpio-v3-2-12d9b7f1202e@gmail.com> References: <20260310-anacapa-dts-sgpio-v3-0-12d9b7f1202e@gmail.com> In-Reply-To: <20260310-anacapa-dts-sgpio-v3-0-12d9b7f1202e@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, Colin.Huang2@amd.com, Carl.Lee@amd.com, Peter.Shen@amd.com, Colin Huang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773136185; l=6745; i=u8813345@gmail.com; s=20260202; h=from:subject:message-id; bh=v/LRXhLIF0yd7V29cZg5G1XTEDL1TBrOYIcbE+/BVbc=; b=Hq0F8fihREKMsfW+ctFW+xs2hNYwsN7OOcZmVaIlEsBoYlO5juDIcQwMZ/v9oJIGcRZhngGVW pqliDEpcGmzAD40ZtczhMDbQLrQZbn9jlk8s0Xn5HTG69FTbLwU9vJR X-Developer-Key: i=u8813345@gmail.com; a=ed25519; pk=Zlg0WqpCw4qbswOqamTBTXIchwR/3SnYZpy7rjaGMdQ= Update SGPIOM0 GPIO line names and signal mappings to align with the latest DFT (Design For Tooling) integration requirements. This change reworks SGPIO input/output assignments, replaces legacy or reserved placeholders, and updates signal naming to match the definitions provided by the CPLD on 2026-03-03. The update improves signal clarity and correctness across leakage detection, presence, fault, power-good, and debug-related GPIOs. Signed-off-by: Colin Huang --- .../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 143 ++++++++++++-----= ---- 1 file changed, 83 insertions(+), 60 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arc= h/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts index 3e297abc5ba4..85b7e027daef 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -862,89 +862,106 @@ &sgpiom0 { ngpios =3D <128>; bus-frequency =3D <2000000>; gpio-line-names =3D - /*in - out - in - out */ + /*in - out */ /* A0-A7 line 0-15 */ - "", "FM_CPU0_SYS_RESET_N", "", "CPU0_KBRST_N", - "", "FM_CPU0_PROCHOT_trigger_N", "", "FM_CLR_CMOS_R_P0", - "", "Force_I3C_SEL", "", "SYSTEM_Force_Run_AC_Cycle", - "", "", "", "", + "L_FNIC_FLT", "FM_CPU0_SYS_RESET_N", + "L_BNIC0_FLT", "CPU0_KBRST_N", + "L_BNIC1_FLT", "FM_CPU0_PROCHOT_trigger_N", + "L_BNIC2_FLT", "FM_CLR_CMOS_R_P0", + "L_BNIC3_FLT", "Force_I3C_SEL", + "L_RTM_SW_FLT", "SYSTEM_Force_Run_AC_Cycle", + "", "", + "", "", =20 /* B0-B7 line 16-31 */ "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", "Channel3_leakage", "FM_CPU0_NMI_SYNC_FLOOD_N", - "Channel4_leakage_Manifold2", "", - "Channel5_leakage_EAM1", "", - "Channel6_leakage_CPU_DIMM", "", - "Channel7_leakage_EAM2", "", + "Channel4_leakage_Manifold2", "BMC_AINIC0_WP_R2_L", + "Channel5_leakage_EAM1", "BMC_AINIC1_WP_R2_L", + "Channel6_leakage_CPU_DIMM", "CPLD_BUF_R_AGPIO330", + "Channel7_leakage_EAM2", "CPLD_BUF_R_AGPIO331", =20 /* C0-C7 line 32-47 */ - "RSVD_RMC_GPIO3", "", "LEAK_DETECT_RMC_N", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", + "RSVD_RMC_GPIO3", "RTM_MUX_L", + "LEAK_DETECT_RMC_N", "RTM_MUX_R", + "HDR_P0_NMI_BTN_BUF_R_N", "FPGA_JTAG_SCM_DBREQ_N", + "No_Leak_Sensor_flag", "whdt_sel", + "", "", + "", "", + "", "", + "", "", =20 /* D0-D7 line 48-63 */ - "PWRGD_PDB_EAMHSC0_CPLD_PG_R", "", - "PWRGD_PDB_EAMHSC1_CPLD_PG_R", "", - "PWRGD_PDB_EAMHSC2_CPLD_PG_R", "", - "PWRGD_PDB_EAMHSC3_CPLD_PG_R", "", - "AMC_BRD_PRSNT_CPLD_L", "", "", "", - "", "", "", "", + "PWRGD_CHAD_CPU0_FPGA", "", + "PWRGD_CHEH_CPU0_FPGA", "", + "PWRGD_CHIL_CPU0_FPGA", "", + "PWRGD_CHMP_CPU0_FPGA", "", + "AMC_BRD_PRSNT_CPLD_L", "", + "", "", + "", "", + "", "", =20 /* E0-E7 line 64-79 */ - "AMC_PDB_EAMHSC0_CPLD_EN_R", "", - "AMC_PDB_EAMHSC1_CPLD_EN_R", "", - "AMC_PDB_EAMHSC2_CPLD_EN_R", "", - "AMC_PDB_EAMHSC3_CPLD_EN_R", "", - "", "", "", "", - "", "", "", "", + "L_PRSNT_B_FENIC_R2_N", "", + "L_PRSNT_B_BENIC0_R2_N", "", + "L_PRSNT_B_BENIC1_R2_N", "", + "L_PRSNT_B_BENIC2_R2_N", "", + "L_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", =20 /* F0-F7 line 80-95 */ - "PWRGD_PVDDCR_CPU1_P0", "SGPIO_READY", - "PWRGD_PVDDCR_CPU0_P0", "", - "", "", "", "", - "", "", "", "", + "R_PRSNT_B_FENIC_R2_N", "SGPIO_READY", + "R_PRSNT_B_BENIC0_R2_N", "", + "R_PRSNT_B_BENIC1_R2_N", "", + "R_PRSNT_B_BENIC2_R2_N", "", + "R_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", =20 /* G0-G7 line 96-111 */ - "PWRGD_PVDDCR_SOC_P0", "", - "PWRGD_PVDDIO_P0", "", - "PWRGD_PVDDIO_MEM_S3_P0", "", - "PWRGD_CHMP_CPU0_FPGA", "", - "PWRGD_CHIL_CPU0_FPGA", "", - "PWRGD_CHEH_CPU0_FPGA", "", - "PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD", + "L_PRSNT_EDSFF2_N", "", + "L_PRSNT_EDSFF3_N", "", + "R_PRSNT_EDSFF2_N", "", + "R_PRSNT_EDSFF3_N", "", + "", "", + "", "", "", "", + "PRSNT_NFC_BOARD_R", "", =20 /* H0-H7 line 112-127 */ - "PWRGD_P3V3", "", - "P12V_DDR_IP_PWRGD_R", "", - "P12V_DDR_AH_PWRGD_R", "", - "PWRGD_P12V_VRM1_CPLD_PG_R", "", - "PWRGD_P12V_VRM0_CPLD_PG_R", "", - "PWRGD_PDB_HSC4_CPLD_PG_R", "", - "PWRGD_PVDD18_S5_P0_PG", "", - "PWRGD_PVDD33_S5_P0_PG", "", + "R_FNIC_FLT", "", + "R_BNIC0_FLT", "", + "R_BNIC1_FLT", "", + "R_BNIC2_FLT", "", + "R_BNIC3_FLT", "", + "R_RTM_SW_FLT", "", + "", "", + "", "", =20 /* I0-I7 line 128-143 */ "EAM0_BRD_PRSNT_R_L", "", "EAM1_BRD_PRSNT_R_L", "", "EAM2_BRD_PRSNT_R_L", "", "EAM3_BRD_PRSNT_R_L", "", - "EAM0_CPU_MOD_PWR_GD_R", "", - "EAM1_CPU_MOD_PWR_GD_R", "", - "EAM2_CPU_MOD_PWR_GD_R", "", - "EAM3_CPU_MOD_PWR_GD_R", "", + "FM_TPM_PRSNT_R_N", "", + "PDB_PRSNT_R_N", "", + "PRSNT_EDSFF0_N", "", + "PRSNT_CPU0_N", "", =20 /* J0-J7 line 144-159 */ - "PRSNT_L_BIRDGE_R", "", - "PRSNT_R_BIRDGE_R", "", + "PRSNT_L_BRIDGE_R", "", + "PRSNT_R_BRIDGE_R", "", "BRIDGE_L_MAIN_PG_R", "", "BRIDGE_R_MAIN_PG_R", "", "BRIDGE_L_STBY_PG_R", "", "BRIDGE_R_STBY_PG_R", "", - "", "", "", "", + "IRQ_NFC_BOARD_R", "", + "RSMRST_N", "", =20 /* K0-K7 line 160-175 */ "ADC_I2C_ALERT_N", "", @@ -957,10 +974,14 @@ &sgpiom0 { "PDB_ALERT_R_N", "", =20 /* L0-L7 line 176-191 */ - "CPU0_SP7R1", "", "CPU0_SP7R2", "", - "CPU0_SP7R3", "", "CPU0_SP7R4", "", - "CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "", - "CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "", + "CPU0_SP7R1", "", + "CPU0_SP7R2", "", + "CPU0_SP7R3", "", + "CPU0_SP7R4", "", + "CPU0_CORETYPE0", "", + "CPU0_CORETYPE1", "", + "CPU0_CORETYPE2", "", + "FM_BIOS_POST_CMPLT_R_N", "", =20 /* M0-M7 line 192-207 */ "EAM0_SMERR_CPLD_R_L", "", @@ -978,17 +999,19 @@ &sgpiom0 { "AMC_STBY_PGOOD_R", "", "CPU_AMC_SLP_S5_R_L", "", "AMC_CPU_EAMPG_R", "", - "", "", "", "", + "DIMM_PMIC_PG_TIMEOUT", "", + "EAM_MOD_PWR_GD_TIMEOUT", "", + "CPLD_AMC_STBY_PWR_EN", "", =20 /* O0-O7 line 224-239 */ "HPM_PWR_FAIL", "Port80_b0", "FM_DIMM_IP_FAIL", "Port80_b1", "FM_DIMM_AH_FAIL", "Port80_b2", "HPM_AMC_THERMTRIP_R_L", "Port80_b3", - "FM_CPU0_THERMTRIP_N", "Port80_b4", + "cpu_thermtrip_detect", "Port80_b4", "PVDDCR_SOC_P0_OCP_L", "Port80_b5", "CPLD_SGPIO_RDY", "Port80_b6", - "", "Port80_b7", + "FM_MAIN_PWREN_RMC_EN_ISO", "Port80_b7", =20 /* P0-P7 line 240-255 */ "CPU0_SLP_S5_N_R", "NFC_VEN", @@ -997,8 +1020,8 @@ &sgpiom0 { "PWRGD_RMC", "", "FM_RST_CPU0_RESET_N", "", "FM_PWRGD_CPU0_PWROK", "", - "wS5_PWR_Ready", "", - "wS0_ON_N", "PWRGD_P1V0_AUX"; + "AMC_FAIL", "", + "wS0_ON_N", ""; status =3D "okay"; }; =20 --=20 2.34.1