From nobody Thu Apr 9 05:48:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E8B52E1747; Tue, 10 Mar 2026 14:32:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773153149; cv=none; b=uxFgPi9QNHDXvPuHvCNgKrEhSt9kDN71mOXTfmSbL0niLml9p69byGqLIX6UOsNxZDrDreATHRdSGwxB4L43i+36JMIrNxkyso3rtW9gyZzw4VaHhJKus6hi0d5gyP90dnrjb46ZhHBL0szyMvKlwEZYhvYTJKXEUbQLqnpqyrk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773153149; c=relaxed/simple; bh=GI5A6sIDTkRHuW8a/SgtskqxywWH7KKoxYkTh0qrVok=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=U+7QhdDCKJ1jh/MgtBTgmTgUHqwWyCFU/OsK9K+MsZUCuIBVNjA1MaiKLPM/ebDFLulrZaan6CnKwv3gcrEcn5VjPlXAYo787z4nJMxRZZAj2V5zqaCcsnmlEt3UEhSOdEa/EupGOEfl9qGCyFDxRl2b9XYphFmztH+7xsHqFuU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nrD4brEu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nrD4brEu" Received: by smtp.kernel.org (Postfix) with ESMTPS id 061DAC2BC86; Tue, 10 Mar 2026 14:32:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773153149; bh=GI5A6sIDTkRHuW8a/SgtskqxywWH7KKoxYkTh0qrVok=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=nrD4brEuF29d2wupLzr69zWPKb5HLsyEOPDdGRCbTmcHTzT3N/2PhaKdf0VBKJXpn p9zdLYdCpvBPjMgdEXMb7h+ewXNN/7165voqn+/a701gUPVBLeTPW4r91cae3GcZ8D FQkV566wccNpQJ43eA6VJBEuC7pjwxQJ9OoVfM8xp8mKcseD2kXrGc/HcU5f04tenD s9Vm6ytmjrOHgBML/lAv76T7S9q1l48+zIRPKreClxnbJsDLsYtoO6IGb+GhYC4mt1 Upha/P9+ufeuurALK32lXq56fsOLpJ1WpvvhEodbwSyxCMHEXskTyzZeK3smff3klg Cxw07GeGtnncw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4FB6EB105D; Tue, 10 Mar 2026 14:32:28 +0000 (UTC) From: Radu Sabau via B4 Relay Date: Tue, 10 Mar 2026 16:32:22 +0200 Subject: [PATCH v2 1/4] dt-bindings: iio: adc: add bindings for AD4691 family Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260310-ad4692-multichannel-sar-adc-driver-v2-1-d9bb8aeb5e17@analog.com> References: <20260310-ad4692-multichannel-sar-adc-driver-v2-0-d9bb8aeb5e17@analog.com> In-Reply-To: <20260310-ad4692-multichannel-sar-adc-driver-v2-0-d9bb8aeb5e17@analog.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Liam Girdwood , Mark Brown , Linus Walleij , Bartosz Golaszewski Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org, Radu Sabau X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773153147; l=7296; i=radu.sabau@analog.com; s=20260220; h=from:subject:message-id; bh=oJ+skzTO+ldVyCAp6LzsSaIW3BVvqyXV5zmKWF0Z/GQ=; b=D8lAzbPQKVzrDR2n/+ls243qCuQhUt/LfQ0SrmxeYVQ3wsxaJfNeVr8qu5QRnyCs3MZll1CZw nWDbc+FTB5FCnV0m9bitXLZzuKE/Zf9cy8Mfb+oDZsJzkH8Gzg7EEk2 X-Developer-Key: i=radu.sabau@analog.com; a=ed25519; pk=lDPQHgn9jTdt0vo58Na9lLxLaE2mb330if71Cn+EvFU= X-Endpoint-Received: by B4 Relay for radu.sabau@analog.com/20260220 with auth_id=642 X-Original-From: Radu Sabau Reply-To: radu.sabau@analog.com From: Radu Sabau Add DT bindings for the Analog Devices AD4691 family of multichannel SAR ADCs (AD4691, AD4692, AD4693, AD4694). The binding describes the hardware connections: an optional PWM on the CNV pin selects CNV Clock Mode; when absent, Manual Mode is used with CNV tied to SPI CS. GPIO pins, voltage supplies, and the trigger-source interface for SPI Engine offload operation are also described. Signed-off-by: Radu Sabau --- .../devicetree/bindings/iio/adc/adi,ad4691.yaml | 180 +++++++++++++++++= ++++ MAINTAINERS | 8 + include/dt-bindings/iio/adc/adi,ad4691.h | 13 ++ 3 files changed, 201 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4691.yaml new file mode 100644 index 000000000000..a9301e0ca851 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml @@ -0,0 +1,180 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad4691.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD4691 Family Multichannel SAR ADCs + +maintainers: + - Radu Sabau + +description: | + The AD4691 family are high-speed, low-power, multichannel successive + approximation register (SAR) analog-to-digital converters (ADCs) with + an SPI-compatible serial interface. The ADC supports CNV Clock Mode, + where an external PWM drives the CNV pin, and Manual Mode, where CNV + is directly tied to the SPI chip-select. + + Datasheets: + * https://www.analog.com/en/products/ad4692.html + * https://www.analog.com/en/products/ad4691.html + * https://www.analog.com/en/products/ad4694.html + * https://www.analog.com/en/products/ad4693.html + +$ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - adi,ad4691 + - adi,ad4692 + - adi,ad4693 + - adi,ad4694 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 40000000 + + spi-cpol: true + spi-cpha: true + + vio-supply: + description: I/O voltage supply (1.71V to 1.89V or VDD). + + vref-supply: + description: External reference voltage supply (2.4V to 5.25V). + + vrefin-supply: + description: Internal reference buffer input supply. + + reset-gpios: + description: GPIO connected to the RESET pin (active high). + maxItems: 1 + + clocks: + description: Reference clock for PWM timing in CNV Clock Mode. + maxItems: 1 + + pwms: + description: + PWM connected to the CNV pin. When present, selects CNV Clock Mode w= here + the PWM drives the conversion rate. When absent, Manual Mode is used + (CNV tied to SPI CS). + maxItems: 1 + + pwm-names: + items: + - const: cnv + + interrupts: + description: + Interrupt line connected to the ADC GP0 pin. GP0 must be physically + wired to an interrupt-capable input on the SoC. The ADC asserts GP0 = as + DATA_READY at end of conversion, used both for non-offload CNV Clock= Mode + operation and for SPI Engine offload triggering via '#trigger-source= -cells'. + Not used in Manual Mode, where CNV is tied to SPI CS and no DATA_REA= DY + signal is generated. + maxItems: 1 + + '#trigger-source-cells': + description: | + For SPI Engine offload operation, this node acts as a trigger source. + Two cells are required: + - First cell: Trigger event type (0 =3D BUSY, 1 =3D DATA_READY) + - Second cell: GPIO pin number (only 0 =3D GP0 is supported) + + Macros are available in dt-bindings/iio/adc/adi,ad4691.h: + AD4691_TRIGGER_EVENT_BUSY, AD4691_TRIGGER_EVENT_DATA_READY + AD4691_TRIGGER_PIN_GP0 + const: 2 + +required: + - compatible + - reg + - vio-supply + - reset-gpios + +allOf: + # vref-supply and vrefin-supply are mutually exclusive, one is required + - oneOf: + - required: + - vref-supply + - required: + - vrefin-supply + + # CNV Clock Mode requires a reference clock. + - if: + required: + - pwms + then: + required: + - clocks + + # CNV Clock Mode (pwms present) without SPI offload requires a DRDY inte= rrupt. + # Offload configurations expose '#trigger-source-cells' instead. + - if: + required: + - pwms + not: + required: + - '#trigger-source-cells' + then: + required: + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + + /* Example: AD4692 in CNV Clock Mode (pwms present) with standard SPI = */ + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad4692"; + reg =3D <0>; + spi-cpol; + spi-cpha; + spi-max-frequency =3D <40000000>; + + vio-supply =3D <&vio_supply>; + vref-supply =3D <&vref_5v>; + + reset-gpios =3D <&gpio 10 GPIO_ACTIVE_HIGH>; + + clocks =3D <&ref_clk>; + + pwms =3D <&pwm_gen 0 0>; + pwm-names =3D "cnv"; + + interrupts =3D <12 4>; + }; + }; + + - | + #include + + /* Example: AD4692 in Manual Mode (no pwms) with SPI Engine offload */ + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + + adc@0 { + compatible =3D "adi,ad4692"; + reg =3D <0>; + spi-cpol; + spi-cpha; + spi-max-frequency =3D <31250000>; + + vio-supply =3D <&vio_supply>; + vrefin-supply =3D <&vrefin_supply>; + + reset-gpios =3D <&gpio 10 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 61bf550fd37c..9994d107d88d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1484,6 +1484,14 @@ W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad4170-4.yaml F: drivers/iio/adc/ad4170-4.c =20 +ANALOG DEVICES INC AD4691 DRIVER +M: Radu Sabau +L: linux-iio@vger.kernel.org +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml +F: include/dt-bindings/iio/adc/adi,ad4691.h + ANALOG DEVICES INC AD4695 DRIVER M: Michael Hennerich M: Nuno S=C3=A1 diff --git a/include/dt-bindings/iio/adc/adi,ad4691.h b/include/dt-bindings= /iio/adc/adi,ad4691.h new file mode 100644 index 000000000000..294b03974f48 --- /dev/null +++ b/include/dt-bindings/iio/adc/adi,ad4691.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_ADI_AD4691_H +#define _DT_BINDINGS_ADI_AD4691_H + +/* Trigger event types */ +#define AD4691_TRIGGER_EVENT_BUSY 0 +#define AD4691_TRIGGER_EVENT_DATA_READY 1 + +/* Trigger GPIO pin selection */ +#define AD4691_TRIGGER_PIN_GP0 0 + +#endif /* _DT_BINDINGS_ADI_AD4691_H */ --=20 2.43.0 From nobody Thu Apr 9 05:48:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E7ED2E11B0; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260310-ad4692-multichannel-sar-adc-driver-v2-2-d9bb8aeb5e17@analog.com> References: <20260310-ad4692-multichannel-sar-adc-driver-v2-0-d9bb8aeb5e17@analog.com> In-Reply-To: <20260310-ad4692-multichannel-sar-adc-driver-v2-0-d9bb8aeb5e17@analog.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Liam Girdwood , Mark Brown , Linus Walleij , Bartosz Golaszewski Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org, Radu Sabau X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773153147; l=26093; i=radu.sabau@analog.com; s=20260220; h=from:subject:message-id; bh=o2i3m/FjhlfwGifaLu6UELKv2Jz+QZeDnd0g+7KBxr8=; b=DkjLKew1BXueW+r1Y4gF3XRgZ1tBm4iCOkFETSrMBNuA4RTNoKKFakAzZw7CQw7PBaQlvbw3c 9PEUD/EoCNACl7T3GsWjeX52IBppRnTZCmPuxU7+FOT3/h924OPHj5K X-Developer-Key: i=radu.sabau@analog.com; a=ed25519; pk=lDPQHgn9jTdt0vo58Na9lLxLaE2mb330if71Cn+EvFU= X-Endpoint-Received: by B4 Relay for radu.sabau@analog.com/20260220 with auth_id=642 X-Original-From: Radu Sabau Reply-To: radu.sabau@analog.com From: Radu Sabau Add support for the Analog Devices AD4691 family of high-speed, low-power multichannel SAR ADCs: AD4691 (16-ch, 500 kSPS), AD4692 (16-ch, 1 MSPS), AD4693 (8-ch, 500 kSPS) and AD4694 (8-ch, 1 MSPS). The driver implements a custom regmap layer over raw SPI to handle the device's mixed 1/2/3/4-byte register widths and uses the standard IIO read_raw/write_raw interface for single-channel reads. Two buffered operating modes are supported, auto-detected from the device tree: - CNV Clock Mode: an external PWM drives the CNV pin; the sampling rate is controlled via the PWM period. Requires a reference clock and a DATA_READY interrupt. - Manual Mode: CNV is tied to SPI CS; each SPI transfer triggers a conversion and returns the previous result (pipelined). No external clock or interrupt needed. In both modes the chip idles in Autonomous Mode so that single-shot read_raw can use the internal oscillator without disturbing the hardware configuration. Signed-off-by: Radu Sabau --- MAINTAINERS | 1 + drivers/iio/adc/Kconfig | 11 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ad4691.c | 773 +++++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 786 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 9994d107d88d..5325f7d3b7f4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1490,6 +1490,7 @@ L: linux-iio@vger.kernel.org S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml +F: drivers/iio/adc/ad4691.c F: include/dt-bindings/iio/adc/adi,ad4691.h =20 ANALOG DEVICES INC AD4695 DRIVER diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 60038ae8dfc4..3685a03aa8dc 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -139,6 +139,17 @@ config AD4170_4 To compile this driver as a module, choose M here: the module will be called ad4170-4. =20 +config AD4691 + tristate "Analog Devices AD4691 Family ADC Driver" + depends on SPI + select REGMAP + help + Say yes here to build support for Analog Devices AD4691 Family MuxSAR + SPI analog to digital converters (ADC). + + To compile this driver as a module, choose M here: the module will be + called ad4691. + config AD4695 tristate "Analog Device AD4695 ADC Driver" depends on SPI diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index c76550415ff1..4ac1ea09d773 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_AD4080) +=3D ad4080.o obj-$(CONFIG_AD4130) +=3D ad4130.o obj-$(CONFIG_AD4134) +=3D ad4134.o obj-$(CONFIG_AD4170_4) +=3D ad4170-4.o +obj-$(CONFIG_AD4691) +=3D ad4691.o obj-$(CONFIG_AD4695) +=3D ad4695.o obj-$(CONFIG_AD4851) +=3D ad4851.o obj-$(CONFIG_AD7091R) +=3D ad7091r-base.o diff --git a/drivers/iio/adc/ad4691.c b/drivers/iio/adc/ad4691.c new file mode 100644 index 000000000000..528c37a9a383 --- /dev/null +++ b/drivers/iio/adc/ad4691.c @@ -0,0 +1,773 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2024-2026 Analog Devices, Inc. + * Author: Radu Sabau + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#define AD4691_VREF_MIN 2400000 +#define AD4691_VREF_MAX 5250000 + +/* + * Default sampling frequency for MANUAL_MODE. + * Each sample needs (num_channels + 1) SPI transfers of 24 bits. + * The factor 36 =3D 24 * 3/2 folds in a 50% scheduling margin: + * freq =3D spi_hz / (24 * 3/2 * (num_channels + 1)) + * =3D spi_hz / (36 * (num_channels + 1)) + */ +#define AD4691_MANUAL_MODE_STD_FREQ(x, y) ((y) / (36 * ((x) + 1))) +#define AD4691_BITS_PER_XFER 24 +#define AD4691_CNV_DUTY_CYCLE_NS 380 +#define AD4691_MAX_CONV_PERIOD_US 800 + +#define AD4691_SEQ_ALL_CHANNELS_OFF 0x00 +#define AD4691_STATE_RESET_ALL 0x01 + +#define AD4691_REF_CTRL_MASK GENMASK(4, 2) + +#define AD4691_DEVICE_MANUAL 0x14 +#define AD4691_DEVICE_REGISTER 0x10 +#define AD4691_AUTONOMOUS_MODE_VAL 0x02 + +#define AD4691_NOOP 0x00 +#define AD4691_ADC_CHAN(ch) ((0x10 + (ch)) << 3) + +#define AD4691_STATUS_REG 0x14 +#define AD4691_CLAMP_STATUS1_REG 0x1A +#define AD4691_CLAMP_STATUS2_REG 0x1B +#define AD4691_DEVICE_SETUP 0x20 +#define AD4691_REF_CTRL 0x21 +#define AD4691_OSC_FREQ_REG 0x23 +#define AD4691_STD_SEQ_CONFIG 0x25 +#define AD4691_SPARE_CONTROL 0x2A + +#define AD4691_OSC_EN_REG 0x180 +#define AD4691_STATE_RESET_REG 0x181 +#define AD4691_ADC_SETUP 0x182 +#define AD4691_ACC_MASK1_REG 0x184 +#define AD4691_ACC_MASK2_REG 0x185 +#define AD4691_ACC_COUNT_LIMIT(n) (0x186 + (n)) +#define AD4691_ACC_COUNT_VAL 0x3F +#define AD4691_GPIO_MODE1_REG 0x196 +#define AD4691_GPIO_MODE2_REG 0x197 +#define AD4691_GPIO_READ 0x1A0 +#define AD4691_ACC_STATUS_FULL1_REG 0x1B0 +#define AD4691_ACC_STATUS_FULL2_REG 0x1B1 +#define AD4691_ACC_STATUS_OVERRUN1_REG 0x1B2 +#define AD4691_ACC_STATUS_OVERRUN2_REG 0x1B3 +#define AD4691_ACC_STATUS_SAT1_REG 0x1B4 +#define AD4691_ACC_STATUS_SAT2_REG 0x1BE +#define AD4691_ACC_SAT_OVR_REG(n) (0x1C0 + (n)) +#define AD4691_AVG_IN(n) (0x201 + (2 * (n))) +#define AD4691_AVG_STS_IN(n) (0x222 + (3 * (n))) +#define AD4691_ACC_IN(n) (0x252 + (3 * (n))) +#define AD4691_ACC_STS_DATA(n) (0x283 + (4 * (n))) + +enum ad4691_adc_mode { + AD4691_CNV_CLOCK_MODE, + AD4691_MANUAL_MODE, +}; + +enum ad4691_gpio_mode { + AD4691_ADC_BUSY =3D 4, + AD4691_DATA_READY =3D 6, +}; + +enum ad4691_ref_ctrl { + AD4691_VREF_2P5 =3D 0, + AD4691_VREF_3P0, + AD4691_VREF_3P3, + AD4691_VREF_4P096, + AD4691_VREF_5P0, +}; + +struct ad4691_chip_info { + const struct iio_chan_spec *channels; + const struct iio_chan_spec *manual_channels; + const char *name; + int num_channels; + int max_rate; +}; + +#define AD4691_CHANNEL(chan, index, real_bits, storage_bits, _shift) \ + { \ + .type =3D IIO_VOLTAGE, \ + .indexed =3D 1, \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ) \ + | BIT(IIO_CHAN_INFO_SCALE), \ + .channel =3D chan, \ + .scan_index =3D index, \ + .scan_type =3D { \ + .sign =3D 'u', \ + .realbits =3D real_bits, \ + .storagebits =3D storage_bits, \ + .shift =3D _shift, \ + }, \ + } + +static const struct iio_chan_spec ad4691_channels[] =3D { + AD4691_CHANNEL(0, 0, 16, 32, 0), + AD4691_CHANNEL(1, 1, 16, 32, 0), + AD4691_CHANNEL(2, 2, 16, 32, 0), + AD4691_CHANNEL(3, 3, 16, 32, 0), + AD4691_CHANNEL(4, 4, 16, 32, 0), + AD4691_CHANNEL(5, 5, 16, 32, 0), + AD4691_CHANNEL(6, 6, 16, 32, 0), + AD4691_CHANNEL(7, 7, 16, 32, 0), + AD4691_CHANNEL(8, 8, 16, 32, 0), + AD4691_CHANNEL(9, 9, 16, 32, 0), + AD4691_CHANNEL(10, 10, 16, 32, 0), + AD4691_CHANNEL(11, 11, 16, 32, 0), + AD4691_CHANNEL(12, 12, 16, 32, 0), + AD4691_CHANNEL(13, 13, 16, 32, 0), + AD4691_CHANNEL(14, 14, 16, 32, 0), + AD4691_CHANNEL(15, 15, 16, 32, 0) +}; + +static const struct iio_chan_spec ad4693_channels[] =3D { + AD4691_CHANNEL(0, 0, 16, 32, 0), + AD4691_CHANNEL(1, 1, 16, 32, 0), + AD4691_CHANNEL(2, 2, 16, 32, 0), + AD4691_CHANNEL(3, 3, 16, 32, 0), + AD4691_CHANNEL(4, 4, 16, 32, 0), + AD4691_CHANNEL(5, 5, 16, 32, 0), + AD4691_CHANNEL(6, 6, 16, 32, 0), + AD4691_CHANNEL(7, 7, 16, 32, 0) +}; + +static const struct iio_chan_spec ad4691_manual_channels[] =3D { + AD4691_CHANNEL(0, 0, 16, 24, 8), + AD4691_CHANNEL(1, 1, 16, 24, 8), + AD4691_CHANNEL(2, 2, 16, 24, 8), + AD4691_CHANNEL(3, 3, 16, 24, 8), + AD4691_CHANNEL(4, 4, 16, 24, 8), + AD4691_CHANNEL(5, 5, 16, 24, 8), + AD4691_CHANNEL(6, 6, 16, 24, 8), + AD4691_CHANNEL(7, 7, 16, 24, 8), + AD4691_CHANNEL(8, 8, 16, 24, 8), + AD4691_CHANNEL(9, 9, 16, 24, 8), + AD4691_CHANNEL(10, 10, 16, 24, 8), + AD4691_CHANNEL(11, 11, 16, 24, 8), + AD4691_CHANNEL(12, 12, 16, 24, 8), + AD4691_CHANNEL(13, 13, 16, 24, 8), + AD4691_CHANNEL(14, 14, 16, 24, 8), + AD4691_CHANNEL(15, 15, 16, 24, 8) +}; + +static const struct iio_chan_spec ad4693_manual_channels[] =3D { + AD4691_CHANNEL(0, 0, 16, 24, 8), + AD4691_CHANNEL(1, 1, 16, 24, 8), + AD4691_CHANNEL(2, 2, 16, 24, 8), + AD4691_CHANNEL(3, 3, 16, 24, 8), + AD4691_CHANNEL(4, 4, 16, 24, 8), + AD4691_CHANNEL(5, 5, 16, 24, 8), + AD4691_CHANNEL(6, 6, 16, 24, 8), + AD4691_CHANNEL(7, 7, 16, 24, 8) +}; + +static const struct ad4691_chip_info ad4691_ad4691 =3D { + .channels =3D ad4691_channels, + .manual_channels =3D ad4691_manual_channels, + .name =3D "ad4691", + .num_channels =3D ARRAY_SIZE(ad4691_channels), + .max_rate =3D 500000, +}; + +static const struct ad4691_chip_info ad4691_ad4692 =3D { + .channels =3D ad4691_channels, + .manual_channels =3D ad4691_manual_channels, + .name =3D "ad4692", + .num_channels =3D ARRAY_SIZE(ad4691_channels), + .max_rate =3D 1000000, +}; + +static const struct ad4691_chip_info ad4691_ad4693 =3D { + .channels =3D ad4693_channels, + .manual_channels =3D ad4693_manual_channels, + .name =3D "ad4693", + .num_channels =3D ARRAY_SIZE(ad4693_channels), + .max_rate =3D 500000, +}; + +static const struct ad4691_chip_info ad4691_ad4694 =3D { + .channels =3D ad4693_channels, + .manual_channels =3D ad4693_manual_channels, + .name =3D "ad4694", + .num_channels =3D ARRAY_SIZE(ad4693_channels), + .max_rate =3D 1000000, +}; + +struct ad4691_state { + const struct ad4691_chip_info *chip; + struct spi_device *spi; + struct regmap *regmap; + + unsigned long ref_clk_rate; + struct pwm_device *conv_trigger; + + enum ad4691_adc_mode adc_mode; + + int vref; + u64 cnv_period; + /* + * Synchronize access to members of the driver state, and ensure + * atomicity of consecutive SPI operations. + */ + struct mutex lock; +}; + +static void ad4691_disable_pwm(void *data) +{ + struct pwm_device *pwm =3D data; + struct pwm_state state; + + pwm_get_state(pwm, &state); + state.enabled =3D false; + pwm_apply_might_sleep(pwm, &state); +} + +static int ad4691_regulator_get(struct ad4691_state *st) +{ + struct device *dev =3D &st->spi->dev; + int ret; + + ret =3D devm_regulator_get_enable(dev, "vio"); + if (ret) + return dev_err_probe(dev, ret, "Failed to get and enable VIO\n"); + + st->vref =3D devm_regulator_get_enable_read_voltage(dev, "vref"); + if (st->vref =3D=3D -ENODEV) + st->vref =3D devm_regulator_get_enable_read_voltage(dev, "vrefin"); + if (st->vref < 0) + return dev_err_probe(dev, st->vref, + "Failed to get reference supply\n"); + + if (st->vref < AD4691_VREF_MIN || st->vref > AD4691_VREF_MAX) + return dev_err_probe(dev, -EINVAL, "vref(%d) must be under [%u %u]\n", + st->vref, AD4691_VREF_MIN, AD4691_VREF_MAX); + + return 0; +} + +static int ad4691_reg_read(void *context, unsigned int reg, unsigned int *= val) +{ + struct ad4691_state *st =3D context; + u8 tx[2], rx[4]; + int ret; + + put_unaligned_be16(0x8000 | reg, tx); + + switch (reg) { + case 0 ... AD4691_OSC_FREQ_REG: + case AD4691_SPARE_CONTROL ... AD4691_ACC_SAT_OVR_REG(15): + ret =3D spi_write_then_read(st->spi, tx, 2, rx, 1); + if (!ret) + *val =3D rx[0]; + return ret; + case AD4691_STD_SEQ_CONFIG: + case AD4691_AVG_IN(0) ... AD4691_AVG_IN(15): + ret =3D spi_write_then_read(st->spi, tx, 2, rx, 2); + if (!ret) + *val =3D get_unaligned_be16(rx); + return ret; + case AD4691_AVG_STS_IN(0) ... AD4691_AVG_STS_IN(15): + case AD4691_ACC_IN(0) ... AD4691_ACC_IN(15): + ret =3D spi_write_then_read(st->spi, tx, 2, rx, 3); + if (!ret) + *val =3D get_unaligned_be24(rx); + return ret; + case AD4691_ACC_STS_DATA(0) ... AD4691_ACC_STS_DATA(15): + ret =3D spi_write_then_read(st->spi, tx, 2, rx, 4); + if (!ret) + *val =3D get_unaligned_be32(rx); + return ret; + default: + return -EINVAL; + } +} + +static int ad4691_reg_write(void *context, unsigned int reg, unsigned int = val) +{ + struct ad4691_state *st =3D context; + u8 tx[4]; + + put_unaligned_be16(reg, tx); + + switch (reg) { + case 0 ... AD4691_OSC_FREQ_REG: + case AD4691_SPARE_CONTROL ... AD4691_GPIO_MODE2_REG: + if (val > 0xFF) + return -EINVAL; + tx[2] =3D val; + return spi_write_then_read(st->spi, tx, 3, NULL, 0); + case AD4691_STD_SEQ_CONFIG: + if (val > 0xFFFF) + return -EINVAL; + put_unaligned_be16(val, &tx[2]); + return spi_write_then_read(st->spi, tx, 4, NULL, 0); + default: + return -EINVAL; + } +} + +static bool ad4691_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case AD4691_STATUS_REG: + case AD4691_CLAMP_STATUS1_REG: + case AD4691_CLAMP_STATUS2_REG: + case AD4691_GPIO_READ: + case AD4691_ACC_STATUS_FULL1_REG ... AD4691_ACC_STATUS_SAT2_REG: + case AD4691_ACC_SAT_OVR_REG(0) ... AD4691_ACC_SAT_OVR_REG(15): + case AD4691_AVG_IN(0) ... AD4691_AVG_IN(15): + case AD4691_AVG_STS_IN(0) ... AD4691_AVG_STS_IN(15): + case AD4691_ACC_IN(0) ... AD4691_ACC_IN(15): + case AD4691_ACC_STS_DATA(0) ... AD4691_ACC_STS_DATA(15): + return true; + default: + return false; + } +} + +static bool ad4691_readable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case 0 ... AD4691_OSC_FREQ_REG: + case AD4691_SPARE_CONTROL ... AD4691_ACC_SAT_OVR_REG(15): + case AD4691_STD_SEQ_CONFIG: + case AD4691_AVG_IN(0) ... AD4691_AVG_IN(15): + case AD4691_AVG_STS_IN(0) ... AD4691_AVG_STS_IN(15): + case AD4691_ACC_IN(0) ... AD4691_ACC_IN(15): + case AD4691_ACC_STS_DATA(0) ... AD4691_ACC_STS_DATA(15): + return true; + default: + return false; + } +} + +static bool ad4691_writeable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case 0 ... AD4691_OSC_FREQ_REG: + case AD4691_STD_SEQ_CONFIG: + case AD4691_SPARE_CONTROL ... AD4691_GPIO_MODE2_REG: + return true; + default: + return false; + } +} + +static const struct regmap_config ad4691_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 32, + .reg_read =3D ad4691_reg_read, + .reg_write =3D ad4691_reg_write, + .volatile_reg =3D ad4691_volatile_reg, + .readable_reg =3D ad4691_readable_reg, + .writeable_reg =3D ad4691_writeable_reg, + .max_register =3D AD4691_ACC_STS_DATA(15), + .cache_type =3D REGCACHE_RBTREE, +}; + +static int ad4691_get_sampling_freq(struct ad4691_state *st) +{ + if (st->adc_mode =3D=3D AD4691_MANUAL_MODE) { + return DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, + ktime_to_ns(st->sampling_period)); + } + + return DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, + pwm_get_period(st->conv_trigger)); +} + +static int __ad4691_set_sampling_freq(struct ad4691_state *st, int freq) +{ + unsigned long long target, ref_clk_period_ns; + struct pwm_state cnv_state; + + pwm_init_state(st->conv_trigger, &cnv_state); + + freq =3D clamp(freq, 1, st->chip->max_rate); + target =3D DIV_ROUND_CLOSEST_ULL(st->ref_clk_rate, freq); + ref_clk_period_ns =3D DIV_ROUND_CLOSEST_ULL(NANO, st->ref_clk_rate); + st->cnv_period =3D ref_clk_period_ns * target; + cnv_state.period =3D ref_clk_period_ns * target; + cnv_state.duty_cycle =3D AD4691_CNV_DUTY_CYCLE_NS; + cnv_state.enabled =3D false; + + return pwm_apply_might_sleep(st->conv_trigger, &cnv_state); +} + +static int ad4691_pwm_get(struct spi_device *spi, struct ad4691_state *st) +{ + struct clk *ref_clk; + int ret; + + ref_clk =3D devm_clk_get_enabled(&spi->dev, NULL); + if (IS_ERR(ref_clk)) + return dev_err_probe(&spi->dev, PTR_ERR(ref_clk), + "Failed to get ref clock\n"); + + st->ref_clk_rate =3D clk_get_rate(ref_clk); + + st->conv_trigger =3D devm_pwm_get(&spi->dev, "cnv"); + if (IS_ERR(st->conv_trigger)) + return dev_err_probe(&spi->dev, PTR_ERR(st->conv_trigger), + "Failed to get cnv pwm\n"); + + ret =3D devm_add_action_or_reset(&spi->dev, ad4691_disable_pwm, + st->conv_trigger); + if (ret) + return dev_err_probe(&spi->dev, ret, + "Failed to register PWM disable action\n"); + + return __ad4691_set_sampling_freq(st, st->chip->max_rate); +} + +static int ad4691_set_sampling_freq(struct iio_dev *indio_dev, unsigned in= t freq) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); + + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + + guard(mutex)(&st->lock); + + if (st->adc_mode =3D=3D AD4691_MANUAL_MODE) { + if (!freq || freq > st->chip->max_rate) + return -EINVAL; + + st->sampling_period =3D ns_to_ktime(DIV_ROUND_CLOSEST_ULL + (NSEC_PER_SEC, freq)); + return 0; + } + + if (!st->conv_trigger) + return -ENODEV; + + if (!freq || freq > st->chip->max_rate) + return -EINVAL; + + return __ad4691_set_sampling_freq(st, freq); +} + +static int ad4691_single_shot_read(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + unsigned long conv_us =3D DIV_ROUND_UP(2UL * USEC_PER_SEC, + st->chip->max_rate); + u16 mask =3D ~BIT(chan->channel); + unsigned int reg_val; + int ret; + + /* + * Always use AUTONOMOUS mode for single-shot reads, regardless + * of the buffer mode (CNV_CLOCK or MANUAL). The chip is kept + * in AUTONOMOUS mode during idle; enter_conversion_mode() and + * exit_conversion_mode() handle the switch for buffer operation. + */ + ret =3D regmap_write(st->regmap, AD4691_STATE_RESET_REG, + AD4691_STATE_RESET_ALL); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4691_STD_SEQ_CONFIG, + BIT(chan->channel)); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4691_ACC_MASK1_REG, mask & 0xFF); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4691_ACC_MASK2_REG, (mask >> 8) & 0xFF= ); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4691_OSC_EN_REG, 1); + if (ret) + return ret; + + /* + * Wait for conversion to complete using a timed delay. + * A single read needs 2 internal oscillator periods. + * OSC_FREQ_REG is never modified by the driver, so the + * oscillator runs at reset-default speed. Use chip->max_rate + * as a conservative proxy: it is always <=3D the OSC frequency, + * so the computed delay is >=3D the actual conversion time. + */ + fsleep(conv_us); + + ret =3D regmap_write(st->regmap, AD4691_OSC_EN_REG, 0); + if (ret) + return ret; + + ret =3D regmap_read(st->regmap, AD4691_AVG_IN(chan->channel), ®_val); + if (ret) + return ret; + + *val =3D reg_val; + regmap_write(st->regmap, AD4691_STATE_RESET_REG, AD4691_STATE_RESET_ALL); + + return IIO_VAL_INT; +} + +static int ad4691_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long info) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + + switch (info) { + case IIO_CHAN_INFO_RAW: { + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); + + if (IIO_DEV_ACQUIRE_FAILED(claim)) + return -EBUSY; + + return ad4691_single_shot_read(indio_dev, chan, val); + } + case IIO_CHAN_INFO_SAMP_FREQ: + *val =3D ad4691_get_sampling_freq(st); + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + *val =3D st->vref / 1000; + *val2 =3D chan->scan_type.realbits; + return IIO_VAL_FRACTIONAL_LOG2; + default: + return -EINVAL; + } +} + +static int ad4691_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_SAMP_FREQ: + return ad4691_set_sampling_freq(indio_dev, val); + default: + return -EINVAL; + } +} + +static int ad4691_reg_access(struct iio_dev *indio_dev, unsigned int reg, + unsigned int writeval, unsigned int *readval) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + + guard(mutex)(&st->lock); + + if (readval) + return regmap_read(st->regmap, reg, readval); + + return regmap_write(st->regmap, reg, writeval); +} + +static const struct iio_info ad4691_info =3D { + .read_raw =3D &ad4691_read_raw, + .write_raw =3D &ad4691_write_raw, + .debugfs_reg_access =3D &ad4691_reg_access, +}; + +static int ad4691_gpio_setup(struct ad4691_state *st) +{ + struct device *dev =3D &st->spi->dev; + struct gpio_desc *reset; + + reset =3D devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(reset)) + return dev_err_probe(dev, PTR_ERR(reset), + "Failed to get reset GPIO\n"); + + /* Reset delay required. See datasheet Table 5. */ + fsleep(300); + gpiod_set_value(reset, 0); + + return 0; +} + +static int ad4691_config(struct ad4691_state *st) +{ + struct device *dev =3D &st->spi->dev; + unsigned int reg_val; + int ret; + + /* + * Determine buffer conversion mode from DT: if a PWM is provided it + * drives the CNV pin (CNV_CLOCK_MODE); otherwise CNV is tied to CS + * and each SPI transfer triggers a conversion (MANUAL_MODE). + * Both modes idle in AUTONOMOUS mode so that read_raw can use the + * internal oscillator without disturbing the hardware configuration. + */ + if (device_property_present(dev, "pwms")) { + st->adc_mode =3D AD4691_CNV_CLOCK_MODE; + ret =3D ad4691_pwm_get(st->spi, st); + if (ret) + return ret; + } else { + st->adc_mode =3D AD4691_MANUAL_MODE; + } + + /* Perform a state reset on the channels at start-up. */ + ret =3D regmap_write(st->regmap, AD4691_STATE_RESET_REG, + AD4691_STATE_RESET_ALL); + if (ret) + return dev_err_probe(dev, ret, "Failed to write state reset\n"); + + /* Clear STATUS register by reading from the STATUS register. */ + ret =3D regmap_read(st->regmap, AD4691_STATUS_REG, ®_val); + if (ret) + return dev_err_probe(dev, ret, "Failed to read status register\n"); + + switch (st->vref) { + case AD4691_VREF_MIN ... 2750000: + ret =3D regmap_write(st->regmap, AD4691_REF_CTRL, + FIELD_PREP(AD4691_REF_CTRL_MASK, + AD4691_VREF_2P5)); + break; + case 2750001 ... 3250000: + ret =3D regmap_write(st->regmap, AD4691_REF_CTRL, + FIELD_PREP(AD4691_REF_CTRL_MASK, + AD4691_VREF_3P0)); + break; + case 3250001 ... 3750000: + ret =3D regmap_write(st->regmap, AD4691_REF_CTRL, + FIELD_PREP(AD4691_REF_CTRL_MASK, + AD4691_VREF_3P3)); + break; + case 3750001 ... 4500000: + ret =3D regmap_write(st->regmap, AD4691_REF_CTRL, + FIELD_PREP(AD4691_REF_CTRL_MASK, + AD4691_VREF_4P096)); + break; + case 4500001 ... AD4691_VREF_MAX: + ret =3D regmap_write(st->regmap, AD4691_REF_CTRL, + FIELD_PREP(AD4691_REF_CTRL_MASK, + AD4691_VREF_5P0)); + break; + default: + return dev_err_probe(dev, -EINVAL, + "Unsupported vref voltage: %d uV\n", + st->vref); + } + if (ret) + return dev_err_probe(dev, ret, "Failed to write REF_CTRL\n"); + + /* Both CNV_CLOCK and MANUAL devices start in AUTONOMOUS mode. */ + ret =3D regmap_write(st->regmap, AD4691_ADC_SETUP, AD4691_AUTONOMOUS_MODE= _VAL); + if (ret) + return dev_err_probe(dev, ret, "Failed to write ADC_SETUP\n"); + + return regmap_write(st->regmap, AD4691_GPIO_MODE1_REG, AD4691_ADC_BUSY); +} + +static int ad4691_probe(struct spi_device *spi) +{ + struct device *dev =3D &spi->dev; + struct iio_dev *indio_dev; + struct ad4691_state *st; + int ret; + + indio_dev =3D devm_iio_device_alloc(&spi->dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st =3D iio_priv(indio_dev); + ret =3D devm_mutex_init(dev, &st->lock); + if (ret) + return ret; + + st->spi =3D spi; + + st->regmap =3D devm_regmap_init(dev, NULL, st, &ad4691_regmap_config); + if (IS_ERR(st->regmap)) + return dev_err_probe(dev, PTR_ERR(st->regmap), + "Failed to initialize regmap\n"); + + st->chip =3D spi_get_device_match_data(spi); + if (!st->chip) + return dev_err_probe(dev, -ENODEV, "Could not find chip info\n"); + + ret =3D ad4691_regulator_get(st); + if (ret) + return ret; + + ret =3D ad4691_gpio_setup(st); + if (ret) + return ret; + + ret =3D ad4691_config(st); + if (ret) + return ret; + + indio_dev->name =3D st->chip->name; + indio_dev->info =3D &ad4691_info; + indio_dev->modes =3D INDIO_DIRECT_MODE; + + indio_dev->channels =3D (st->adc_mode =3D=3D AD4691_MANUAL_MODE) + ? st->chip->manual_channels : st->chip->channels; + indio_dev->num_channels =3D st->chip->num_channels; + + return devm_iio_device_register(dev, indio_dev); +} + +static const struct of_device_id ad4691_of_match[] =3D { + { .compatible =3D "adi,ad4691", .data =3D &ad4691_ad4691 }, + { .compatible =3D "adi,ad4692", .data =3D &ad4691_ad4692 }, + { .compatible =3D "adi,ad4693", .data =3D &ad4691_ad4693 }, + { .compatible =3D "adi,ad4694", .data =3D &ad4691_ad4694 }, + { } +}; +MODULE_DEVICE_TABLE(of, ad4691_of_match); + +static const struct spi_device_id ad4691_id[] =3D { + { "ad4691", (kernel_ulong_t)&ad4691_ad4691 }, + { "ad4692", (kernel_ulong_t)&ad4691_ad4692 }, + { "ad4693", (kernel_ulong_t)&ad4691_ad4693 }, + { "ad4694", (kernel_ulong_t)&ad4691_ad4694 }, + { } +}; +MODULE_DEVICE_TABLE(spi, ad4691_id); + +static struct spi_driver ad4691_driver =3D { + .driver =3D { + .name =3D "ad4691", + .of_match_table =3D ad4691_of_match, + }, + .probe =3D ad4691_probe, + .id_table =3D ad4691_id, +}; +module_spi_driver(ad4691_driver); + +MODULE_AUTHOR("Radu Sabau "); +MODULE_DESCRIPTION("Analog Devices AD4691 Family ADC Driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Thu Apr 9 05:48:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E2822E5B09; Tue, 10 Mar 2026 14:32:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260310-ad4692-multichannel-sar-adc-driver-v2-3-d9bb8aeb5e17@analog.com> References: <20260310-ad4692-multichannel-sar-adc-driver-v2-0-d9bb8aeb5e17@analog.com> In-Reply-To: <20260310-ad4692-multichannel-sar-adc-driver-v2-0-d9bb8aeb5e17@analog.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Liam Girdwood , Mark Brown , Linus Walleij , Bartosz Golaszewski Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org, Radu Sabau X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773153147; l=17111; i=radu.sabau@analog.com; s=20260220; h=from:subject:message-id; bh=8O0mQbD6rNXGpXxojq9wOKjwgwNr9Jd2ObpkjUzk0Ks=; b=8rQf21NJGtDw/WIw/edZpx7wwFdV43cHP5MMm1JrP7PINXCKdYnubWP1s1B5AaB/hqw+VnhiF bOGLtDtcxjKAA2u2EuWnkAhiwkK9Cman1zdwYh30jTowcl6TGq/h1bW X-Developer-Key: i=radu.sabau@analog.com; a=ed25519; pk=lDPQHgn9jTdt0vo58Na9lLxLaE2mb330if71Cn+EvFU= X-Endpoint-Received: by B4 Relay for radu.sabau@analog.com/20260220 with auth_id=642 X-Original-From: Radu Sabau Reply-To: radu.sabau@analog.com From: Radu Sabau Add buffered capture support using the IIO triggered buffer framework. Both operating modes share a single IIO trigger and trigger handler. The handler builds a complete scan =E2=80=94 one u32 slot per channel at its scan_index position, followed by a timestamp =E2=80=94 and pushes it to the IIO buffer in a single iio_push_to_buffers_with_ts() call. For CNV Clock Mode the GP0 pin is configured as DATA_READY output. The IRQ handler stops conversions and fires the IIO trigger; the trigger handler reads accumulated results from the AVG_IN registers via regmap and restarts conversions for the next cycle. For Manual Mode there is no DATA_READY signal; CNV is tied to SPI CS so conversions are triggered by CS assertion rather than by a dedicated pin. The standard iio-trig-hrtimer module is not used because the timer period must be derived from the SPI clock rate and the number of active channels: the pipelined protocol requires N+1 SPI transfers per scan (the first result is garbage and is discarded), so the minimum period depends on both the SPI speed and the live channel count at buffer enable time. A driver-private hrtimer whose period is recomputed by buffer_postenable is simpler and avoids requiring the user to configure an external trigger with the correct hardware-derived period. Manual mode channels use storagebits=3D32 (shift=3D8, realbits=3D16) so all channel slots in the scan buffer are uniformly sized regardless of the SPI wire format (24-bit transfer, 16-bit ADC data in bits[23:8]). Signed-off-by: Radu Sabau --- drivers/iio/adc/Kconfig | 2 + drivers/iio/adc/ad4691.c | 405 +++++++++++++++++++++++++++++++++++++++++++= +--- 2 files changed, 382 insertions(+), 25 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 3685a03aa8dc..d498f16c0816 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -142,6 +142,8 @@ config AD4170_4 config AD4691 tristate "Analog Devices AD4691 Family ADC Driver" depends on SPI + select IIO_BUFFER + select IIO_TRIGGERED_BUFFER select REGMAP help Say yes here to build support for Analog Devices AD4691 Family MuxSAR diff --git a/drivers/iio/adc/ad4691.c b/drivers/iio/adc/ad4691.c index 528c37a9a383..8b3caf0334ba 100644 --- a/drivers/iio/adc/ad4691.c +++ b/drivers/iio/adc/ad4691.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -25,8 +26,13 @@ #include #include =20 +#include #include =20 +#include +#include +#include + #include =20 #define AD4691_VREF_MIN 2400000 @@ -71,7 +77,7 @@ #define AD4691_ACC_MASK1_REG 0x184 #define AD4691_ACC_MASK2_REG 0x185 #define AD4691_ACC_COUNT_LIMIT(n) (0x186 + (n)) -#define AD4691_ACC_COUNT_VAL 0x3F +#define AD4691_ACC_COUNT_VAL 0x01 #define AD4691_GPIO_MODE1_REG 0x196 #define AD4691_GPIO_MODE2_REG 0x197 #define AD4691_GPIO_READ 0x1A0 @@ -161,33 +167,33 @@ static const struct iio_chan_spec ad4693_channels[] = =3D { }; =20 static const struct iio_chan_spec ad4691_manual_channels[] =3D { - AD4691_CHANNEL(0, 0, 16, 24, 8), - AD4691_CHANNEL(1, 1, 16, 24, 8), - AD4691_CHANNEL(2, 2, 16, 24, 8), - AD4691_CHANNEL(3, 3, 16, 24, 8), - AD4691_CHANNEL(4, 4, 16, 24, 8), - AD4691_CHANNEL(5, 5, 16, 24, 8), - AD4691_CHANNEL(6, 6, 16, 24, 8), - AD4691_CHANNEL(7, 7, 16, 24, 8), - AD4691_CHANNEL(8, 8, 16, 24, 8), - AD4691_CHANNEL(9, 9, 16, 24, 8), - AD4691_CHANNEL(10, 10, 16, 24, 8), - AD4691_CHANNEL(11, 11, 16, 24, 8), - AD4691_CHANNEL(12, 12, 16, 24, 8), - AD4691_CHANNEL(13, 13, 16, 24, 8), - AD4691_CHANNEL(14, 14, 16, 24, 8), - AD4691_CHANNEL(15, 15, 16, 24, 8) + AD4691_CHANNEL(0, 0, 16, 32, 8), + AD4691_CHANNEL(1, 1, 16, 32, 8), + AD4691_CHANNEL(2, 2, 16, 32, 8), + AD4691_CHANNEL(3, 3, 16, 32, 8), + AD4691_CHANNEL(4, 4, 16, 32, 8), + AD4691_CHANNEL(5, 5, 16, 32, 8), + AD4691_CHANNEL(6, 6, 16, 32, 8), + AD4691_CHANNEL(7, 7, 16, 32, 8), + AD4691_CHANNEL(8, 8, 16, 32, 8), + AD4691_CHANNEL(9, 9, 16, 32, 8), + AD4691_CHANNEL(10, 10, 16, 32, 8), + AD4691_CHANNEL(11, 11, 16, 32, 8), + AD4691_CHANNEL(12, 12, 16, 32, 8), + AD4691_CHANNEL(13, 13, 16, 32, 8), + AD4691_CHANNEL(14, 14, 16, 32, 8), + AD4691_CHANNEL(15, 15, 16, 32, 8) }; =20 static const struct iio_chan_spec ad4693_manual_channels[] =3D { - AD4691_CHANNEL(0, 0, 16, 24, 8), - AD4691_CHANNEL(1, 1, 16, 24, 8), - AD4691_CHANNEL(2, 2, 16, 24, 8), - AD4691_CHANNEL(3, 3, 16, 24, 8), - AD4691_CHANNEL(4, 4, 16, 24, 8), - AD4691_CHANNEL(5, 5, 16, 24, 8), - AD4691_CHANNEL(6, 6, 16, 24, 8), - AD4691_CHANNEL(7, 7, 16, 24, 8) + AD4691_CHANNEL(0, 0, 16, 32, 8), + AD4691_CHANNEL(1, 1, 16, 32, 8), + AD4691_CHANNEL(2, 2, 16, 32, 8), + AD4691_CHANNEL(3, 3, 16, 32, 8), + AD4691_CHANNEL(4, 4, 16, 32, 8), + AD4691_CHANNEL(5, 5, 16, 32, 8), + AD4691_CHANNEL(6, 6, 16, 32, 8), + AD4691_CHANNEL(7, 7, 16, 32, 8) }; =20 static const struct ad4691_chip_info ad4691_ad4691 =3D { @@ -230,6 +236,8 @@ struct ad4691_state { unsigned long ref_clk_rate; struct pwm_device *conv_trigger; =20 + struct iio_trigger *trig; + enum ad4691_adc_mode adc_mode; =20 int vref; @@ -239,6 +247,22 @@ struct ad4691_state { * atomicity of consecutive SPI operations. */ struct mutex lock; + + /* hrtimer for MANUAL_MODE triggered buffer (non-offload) */ + struct hrtimer sampling_timer; + ktime_t sampling_period; + + /* + * DMA (thus cache coherency maintenance) may require the + * transfer buffers to live in their own cache lines. + */ + unsigned char rx_data[ALIGN(3, sizeof(s64)) + sizeof(s64)] __aligned(IIO_= DMA_MINALIGN); + unsigned char tx_data[ALIGN(3, sizeof(s64)) + sizeof(s64)]; + /* Scan buffer: one slot per channel (u32) plus timestamp */ + struct { + u32 vals[16]; + s64 ts __aligned(8); + } scan __aligned(IIO_DMA_MINALIGN); }; =20 static void ad4691_disable_pwm(void *data) @@ -394,6 +418,27 @@ static const struct regmap_config ad4691_regmap_config= =3D { .cache_type =3D REGCACHE_RBTREE, }; =20 +static int ad4691_transfer(struct ad4691_state *st, int command, + unsigned int *val) +{ + struct spi_transfer xfer =3D { + .tx_buf =3D st->tx_data, + .rx_buf =3D st->rx_data, + .len =3D 3, + }; + int ret; + + memcpy(st->tx_data, &command, 3); + + ret =3D spi_sync_transfer(st->spi, &xfer, 1); + if (ret) + return ret; + + *val =3D get_unaligned_be24(st->rx_data); + + return 0; +} + static int ad4691_get_sampling_freq(struct ad4691_state *st) { if (st->adc_mode =3D=3D AD4691_MANUAL_MODE) { @@ -478,6 +523,18 @@ static int ad4691_set_sampling_freq(struct iio_dev *in= dio_dev, unsigned int freq return __ad4691_set_sampling_freq(st, freq); } =20 +static int ad4691_sampling_enable(struct ad4691_state *st, bool enable) +{ + struct pwm_state conv_state =3D { }; + + conv_state.period =3D st->cnv_period; + conv_state.duty_cycle =3D AD4691_CNV_DUTY_CYCLE_NS; + conv_state.polarity =3D PWM_POLARITY_NORMAL; + conv_state.enabled =3D enable; + + return pwm_apply_might_sleep(st->conv_trigger, &conv_state); +} + static int ad4691_single_shot_read(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val) { @@ -592,6 +649,240 @@ static int ad4691_reg_access(struct iio_dev *indio_de= v, unsigned int reg, return regmap_write(st->regmap, reg, writeval); } =20 +/* + * ad4691_enter_conversion_mode - Switch the chip to its buffer conversion= mode. + * + * Configures the ADC hardware registers for the mode selected at probe + * (CNV_CLOCK or MANUAL). Called from buffer postenable before starting + * sampling. The chip is in AUTONOMOUS mode during idle (for read_raw). + */ +static int ad4691_enter_conversion_mode(struct ad4691_state *st) +{ + int ret; + + if (st->adc_mode =3D=3D AD4691_MANUAL_MODE) + return regmap_write(st->regmap, AD4691_DEVICE_SETUP, + AD4691_DEVICE_MANUAL); + + ret =3D regmap_write(st->regmap, AD4691_ADC_SETUP, AD4691_CNV_CLOCK_MODE); + if (ret) + return ret; + + return regmap_write(st->regmap, AD4691_GPIO_MODE1_REG, + AD4691_DATA_READY); +} + +/* + * ad4691_exit_conversion_mode - Return the chip to AUTONOMOUS mode. + * + * Called from buffer postdisable/predisable to restore the chip to the + * idle state used by read_raw. Clears the sequencer and resets state. + */ +static int ad4691_exit_conversion_mode(struct ad4691_state *st) +{ + int ret; + + if (st->adc_mode =3D=3D AD4691_MANUAL_MODE) { + ret =3D regmap_write(st->regmap, AD4691_DEVICE_SETUP, + AD4691_DEVICE_REGISTER); + if (ret) + return ret; + } + + ret =3D regmap_write(st->regmap, AD4691_ADC_SETUP, AD4691_AUTONOMOUS_MODE= _VAL); + if (ret) + return ret; + + /* Restore GP0 to ADC_BUSY for AUTONOMOUS idle (enter set it to DATA_READ= Y) */ + ret =3D regmap_write(st->regmap, AD4691_GPIO_MODE1_REG, AD4691_ADC_BUSY); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4691_STD_SEQ_CONFIG, + AD4691_SEQ_ALL_CHANNELS_OFF); + if (ret) + return ret; + + return regmap_write(st->regmap, AD4691_STATE_RESET_REG, + AD4691_STATE_RESET_ALL); +} + +static int ad4691_buffer_postenable(struct iio_dev *indio_dev) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + int n_active =3D hweight_long(*indio_dev->active_scan_mask); + unsigned int bit; + int ret; + + ret =3D ad4691_enter_conversion_mode(st); + if (ret) + return ret; + + if (st->adc_mode =3D=3D AD4691_MANUAL_MODE) { + u64 min_period_ns; + + /* N+1 transfers needed for N channels, with 50% overhead */ + min_period_ns =3D div64_u64((u64)(n_active + 1) * AD4691_BITS_PER_XFER * + NSEC_PER_SEC * 3, + st->spi->max_speed_hz * 2); + + if (ktime_to_ns(st->sampling_period) < min_period_ns) { + dev_err(&st->spi->dev, + "Sampling period %lld ns too short for %d channels. Min: %llu ns\n", + ktime_to_ns(st->sampling_period), n_active, + min_period_ns); + return -EINVAL; + } + + hrtimer_start(&st->sampling_timer, st->sampling_period, + HRTIMER_MODE_REL); + return 0; + } + + /* CNV_CLOCK_MODE: configure sequencer and start PWM */ + ret =3D regmap_write(st->regmap, AD4691_STATE_RESET_REG, + AD4691_STATE_RESET_ALL); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4691_ACC_MASK1_REG, + ~(*indio_dev->active_scan_mask) & 0xFF); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4691_ACC_MASK2_REG, + ~(*indio_dev->active_scan_mask >> 8) & 0xFF); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4691_STD_SEQ_CONFIG, + *indio_dev->active_scan_mask); + if (ret) + return ret; + + iio_for_each_active_channel(indio_dev, bit) { + ret =3D regmap_write(st->regmap, AD4691_ACC_COUNT_LIMIT(bit), + AD4691_ACC_COUNT_VAL); + if (ret) + return ret; + } + + return ad4691_sampling_enable(st, true); +} + +static int ad4691_buffer_postdisable(struct iio_dev *indio_dev) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + + if (st->adc_mode =3D=3D AD4691_MANUAL_MODE) + hrtimer_cancel_wait_running(&st->sampling_timer); + else + ad4691_sampling_enable(st, false); + + return ad4691_exit_conversion_mode(st); +} + +static const struct iio_buffer_setup_ops ad4691_buffer_setup_ops =3D { + .postenable =3D &ad4691_buffer_postenable, + .postdisable =3D &ad4691_buffer_postdisable, +}; + +static irqreturn_t ad4691_irq(int irq, void *private) +{ + struct iio_dev *indio_dev =3D private; + struct ad4691_state *st =3D iio_priv(indio_dev); + + /* + * DATA_READY has asserted: stop conversions before reading so the + * accumulator does not continue sampling while the trigger handler + * processes the data. Then fire the IIO trigger to push the sample + * to the buffer. + */ + ad4691_sampling_enable(st, false); + iio_trigger_poll(st->trig); + + return IRQ_HANDLED; +} + +static enum hrtimer_restart ad4691_sampling_timer_handler(struct hrtimer *= timer) +{ + struct ad4691_state *st =3D container_of(timer, struct ad4691_state, + sampling_timer); + + iio_trigger_poll(st->trig); + hrtimer_forward_now(timer, st->sampling_period); + + return HRTIMER_RESTART; +} + +static const struct iio_trigger_ops ad4691_trigger_ops =3D { + .validate_device =3D iio_trigger_validate_own_device, +}; + +static irqreturn_t ad4691_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf =3D p; + struct iio_dev *indio_dev =3D pf->indio_dev; + struct ad4691_state *st =3D iio_priv(indio_dev); + unsigned int val; + int ret, i; + + mutex_lock(&st->lock); + + if (st->adc_mode =3D=3D AD4691_MANUAL_MODE) { + unsigned int prev_val; + int prev_chan =3D -1; + + /* + * MANUAL_MODE with CNV tied to CS: each transfer triggers a + * conversion AND returns the previous conversion's result. + * First transfer returns garbage, so we do N+1 transfers for + * N channels. Collect all results into scan.vals[], then push + * the complete scan once. + */ + iio_for_each_active_channel(indio_dev, i) { + ret =3D ad4691_transfer(st, AD4691_ADC_CHAN(i), &val); + if (ret) + goto done; + + if (prev_chan >=3D 0) + st->scan.vals[prev_chan] =3D prev_val; + prev_val =3D val; + prev_chan =3D i; + } + + /* Final NOOP transfer to retrieve last channel's result */ + ret =3D ad4691_transfer(st, AD4691_NOOP, &val); + if (ret) + goto done; + + st->scan.vals[prev_chan] =3D val; + } else { + for (i =3D 0; i < st->chip->num_channels; i++) { + if (BIT(i) & *indio_dev->active_scan_mask) { + ret =3D regmap_read(st->regmap, AD4691_AVG_IN(i), &val); + if (ret) + goto done; + + st->scan.vals[i] =3D val; + } + } + + regmap_write(st->regmap, AD4691_STATE_RESET_REG, AD4691_STATE_RESET_ALL); + + /* Restart conversions for the next trigger cycle. */ + ad4691_sampling_enable(st, true); + } + + iio_push_to_buffers_with_ts(indio_dev, &st->scan, sizeof(st->scan), + pf->timestamp); + +done: + iio_trigger_notify_done(indio_dev->trig); + mutex_unlock(&st->lock); + return IRQ_HANDLED; +} + static const struct iio_info ad4691_info =3D { .read_raw =3D &ad4691_read_raw, .write_raw =3D &ad4691_write_raw, @@ -690,6 +981,66 @@ static int ad4691_config(struct ad4691_state *st) return regmap_write(st->regmap, AD4691_GPIO_MODE1_REG, AD4691_ADC_BUSY); } =20 +static int ad4691_setup_triggered_buffer(struct iio_dev *indio_dev, + struct ad4691_state *st) +{ + struct device *dev =3D &st->spi->dev; + int irq, ret; + + st->trig =3D devm_iio_trigger_alloc(dev, "%s-dev%d", + indio_dev->name, + iio_device_id(indio_dev)); + if (!st->trig) + return dev_err_probe(dev, -ENOMEM, + "Failed to allocate IIO trigger\n"); + + st->trig->ops =3D &ad4691_trigger_ops; + iio_trigger_set_drvdata(st->trig, st); + + ret =3D devm_iio_trigger_register(dev, st->trig); + if (ret) + return dev_err_probe(dev, ret, "IIO trigger register failed\n"); + + indio_dev->trig =3D iio_trigger_get(st->trig); + + if (st->adc_mode =3D=3D AD4691_MANUAL_MODE) { + /* + * No DATA_READY signal in MANUAL_MODE; CNV is tied to CS so + * conversions start with each SPI transfer. Use an hrtimer to + * schedule periodic reads. + */ + hrtimer_setup(&st->sampling_timer, ad4691_sampling_timer_handler, + CLOCK_MONOTONIC, HRTIMER_MODE_REL); + st->sampling_period =3D ns_to_ktime(DIV_ROUND_CLOSEST_ULL( + NSEC_PER_SEC, + AD4691_MANUAL_MODE_STD_FREQ(st->chip->num_channels, + st->spi->max_speed_hz))); + } else { + /* + * DATA_READY asserts at end-of-conversion. The IRQ handler + * stops conversions and fires the IIO trigger so the trigger + * handler can read and push the sample to the buffer. + */ + irq =3D fwnode_irq_get(dev_fwnode(dev), 0); + if (irq <=3D 0) + return dev_err_probe(dev, irq ? irq : -ENOENT, + "failed to get DATA_READY interrupt\n"); + + ret =3D devm_request_threaded_irq(dev, irq, NULL, + &ad4691_irq, + IRQF_ONESHOT, + indio_dev->name, indio_dev); + if (ret) + return dev_err_probe(dev, ret, + "request irq %d failed\n", irq); + } + + return devm_iio_triggered_buffer_setup(dev, indio_dev, + &iio_pollfunc_store_time, + &ad4691_trigger_handler, + &ad4691_buffer_setup_ops); +} + static int ad4691_probe(struct spi_device *spi) { struct device *dev =3D &spi->dev; @@ -737,6 +1088,10 @@ static int ad4691_probe(struct spi_device *spi) ? st->chip->manual_channels : st->chip->channels; indio_dev->num_channels =3D st->chip->num_channels; =20 + ret =3D ad4691_setup_triggered_buffer(indio_dev, st); + if (ret) + return ret; + return devm_iio_device_register(dev, indio_dev); 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Tue, 10 Mar 2026 14:32:29 +0000 (UTC) From: Radu Sabau via B4 Relay Date: Tue, 10 Mar 2026 16:32:25 +0200 Subject: [PATCH v2 4/4] iio: adc: ad4691: add SPI offload support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260310-ad4692-multichannel-sar-adc-driver-v2-4-d9bb8aeb5e17@analog.com> References: <20260310-ad4692-multichannel-sar-adc-driver-v2-0-d9bb8aeb5e17@analog.com> In-Reply-To: <20260310-ad4692-multichannel-sar-adc-driver-v2-0-d9bb8aeb5e17@analog.com> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Liam Girdwood , Mark Brown , Linus Walleij , Bartosz Golaszewski Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org, Radu Sabau X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773153147; l=18450; i=radu.sabau@analog.com; s=20260220; h=from:subject:message-id; bh=BHgIa8pe6A8XMJvEo+AxZy5Cw3LLOU1NleJ4RT2NNoA=; b=Q/yPNk0DAT4z68vxkEwQKoqZtxKG/l6e454OJkJ78fAiEt5plSzXcuxnJxD2/GMlX8fxEZnVt BZuhR63eSzOAlIYW6gr6/F7JOjeSl94/KqIscOPilyGe1cRNpNTmIcC X-Developer-Key: i=radu.sabau@analog.com; a=ed25519; pk=lDPQHgn9jTdt0vo58Na9lLxLaE2mb330if71Cn+EvFU= X-Endpoint-Received: by B4 Relay for radu.sabau@analog.com/20260220 with auth_id=642 X-Original-From: Radu Sabau Reply-To: radu.sabau@analog.com From: Radu Sabau Add SPI offload support to enable DMA-based, CPU-independent data acquisition using the SPI Engine offload framework. When an SPI offload is available (devm_spi_offload_get() succeeds), the driver registers a DMA engine IIO buffer and uses dedicated buffer setup operations. If no offload is available the existing software triggered buffer path is used unchanged. Both CNV Clock Mode and Manual Mode support offload, but use different trigger mechanisms: CNV Clock Mode: the SPI Engine is triggered by the ADC's DATA_READY signal on GP0. For this mode the driver acts as both an SPI offload consumer (DMA RX stream, message optimization) and a trigger source provider: it registers the GP0/DATA_READY output via devm_spi_offload_trigger_register() so the offload framework can match the '#trigger-source-cells' phandle from the device tree and automatically fire the SPI Engine DMA transfer at end-of-conversion. The pre-built SPI message reads all active channels from the AVG_IN accumulator registers (2-byte address + 2-byte data per channel, one 4-byte transfer each) followed by a state reset word to re-arm the accumulator for the next cycle. Manual Mode: the SPI Engine is triggered by a periodic trigger at the configured sampling frequency. The pre-built SPI message uses the pipelined CNV-on-CS protocol: N+1 4-byte transfers are issued for N active channels (the first result is discarded as garbage from the pipeline flush) and the remaining N results are captured by DMA. All offload transfers use 32-bit frames (bits_per_word=3D32, len=3D4) for DMA word alignment. In Manual Mode the 4-byte DMA word layout is [dummy(8), data_hi(8), data_lo(8), extra(8)]; the channel scan type storagebits=3D32, shift=3D8, realbits=3D16 correctly extracts the 16-bit ADC result from the middle two bytes. Kconfig gains a dependency on IIO_BUFFER_DMAENGINE. Signed-off-by: Radu Sabau --- drivers/iio/adc/Kconfig | 1 + drivers/iio/adc/ad4691.c | 398 +++++++++++++++++++++++++++++++++++++++++++= ++-- 2 files changed, 389 insertions(+), 10 deletions(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index d498f16c0816..93f090e9a562 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -144,6 +144,7 @@ config AD4691 depends on SPI select IIO_BUFFER select IIO_TRIGGERED_BUFFER + select IIO_BUFFER_DMAENGINE select REGMAP help Say yes here to build support for Analog Devices AD4691 Family MuxSAR diff --git a/drivers/iio/adc/ad4691.c b/drivers/iio/adc/ad4691.c index 8b3caf0334ba..2ed384cfc1b9 100644 --- a/drivers/iio/adc/ad4691.c +++ b/drivers/iio/adc/ad4691.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -22,11 +23,15 @@ #include #include #include +#include +#include #include #include #include =20 #include +#include +#include #include =20 #include @@ -47,6 +52,7 @@ */ #define AD4691_MANUAL_MODE_STD_FREQ(x, y) ((y) / (36 * ((x) + 1))) #define AD4691_BITS_PER_XFER 24 +#define AD4691_OFFLOAD_BITS_PER_WORD 32 #define AD4691_CNV_DUTY_CYCLE_NS 380 #define AD4691_MAX_CONV_PERIOD_US 800 =20 @@ -252,6 +258,16 @@ struct ad4691_state { struct hrtimer sampling_timer; ktime_t sampling_period; =20 + struct spi_offload *offload; + struct spi_offload_trigger *offload_trigger; + struct spi_offload_trigger *offload_trigger_periodic; + u64 offload_trigger_hz; + struct spi_message offload_msg; + /* Max 16 channel transfers + 1 state reset or NOOP */ + struct spi_transfer offload_xfer[17]; + /* TX commands for manual and accumulator modes */ + u32 offload_tx_cmd[17]; + u32 offload_tx_reset; /* * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. @@ -265,6 +281,65 @@ struct ad4691_state { } scan __aligned(IIO_DMA_MINALIGN); }; =20 +static const struct spi_offload_config ad4691_offload_config =3D { + .capability_flags =3D SPI_OFFLOAD_CAP_TRIGGER | + SPI_OFFLOAD_CAP_RX_STREAM_DMA, +}; + +static bool ad4691_offload_trigger_match(struct spi_offload_trigger *trigg= er, + enum spi_offload_trigger_type type, + u64 *args, u32 nargs) +{ + if (type !=3D SPI_OFFLOAD_TRIGGER_DATA_READY) + return false; + + /* + * Requires 2 args: + * args[0] is the trigger event (BUSY or DATA_READY). + * args[1] is the GPIO pin number (only GP0 supported). + */ + if (nargs !=3D 2) + return false; + + if (args[0] !=3D AD4691_TRIGGER_EVENT_BUSY && + args[0] !=3D AD4691_TRIGGER_EVENT_DATA_READY) + return false; + + if (args[1] !=3D AD4691_TRIGGER_PIN_GP0) + return false; + + return true; +} + +static int ad4691_offload_trigger_request(struct spi_offload_trigger *trig= ger, + enum spi_offload_trigger_type type, + u64 *args, u32 nargs) +{ + /* + * GP0 is configured as DATA_READY or BUSY in ad4691_config() + * based on the ADC mode. No additional configuration needed here. + */ + if (nargs !=3D 2) + return -EINVAL; + + return 0; +} + +static int ad4691_offload_trigger_validate(struct spi_offload_trigger *tri= gger, + struct spi_offload_trigger_config *config) +{ + if (config->type !=3D SPI_OFFLOAD_TRIGGER_DATA_READY) + return -EINVAL; + + return 0; +} + +static const struct spi_offload_trigger_ops ad4691_offload_trigger_ops =3D= { + .match =3D ad4691_offload_trigger_match, + .request =3D ad4691_offload_trigger_request, + .validate =3D ad4691_offload_trigger_validate, +}; + static void ad4691_disable_pwm(void *data) { struct pwm_device *pwm =3D data; @@ -442,6 +517,9 @@ static int ad4691_transfer(struct ad4691_state *st, int= command, static int ad4691_get_sampling_freq(struct ad4691_state *st) { if (st->adc_mode =3D=3D AD4691_MANUAL_MODE) { + /* Offload uses periodic trigger, non-offload uses hrtimer */ + if (st->offload) + return st->offload_trigger_hz; return DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, ktime_to_ns(st->sampling_period)); } @@ -497,6 +575,7 @@ static int ad4691_pwm_get(struct spi_device *spi, struc= t ad4691_state *st) static int ad4691_set_sampling_freq(struct iio_dev *indio_dev, unsigned in= t freq) { struct ad4691_state *st =3D iio_priv(indio_dev); + int ret; =20 IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); =20 @@ -506,12 +585,31 @@ static int ad4691_set_sampling_freq(struct iio_dev *i= ndio_dev, unsigned int freq guard(mutex)(&st->lock); =20 if (st->adc_mode =3D=3D AD4691_MANUAL_MODE) { - if (!freq || freq > st->chip->max_rate) - return -EINVAL; - - st->sampling_period =3D ns_to_ktime(DIV_ROUND_CLOSEST_ULL - (NSEC_PER_SEC, freq)); - return 0; + /* For offload mode, validate and store frequency for periodic trigger */ + if (st->offload) { + struct spi_offload_trigger_config config =3D { + .type =3D SPI_OFFLOAD_TRIGGER_PERIODIC, + .periodic =3D { + .frequency_hz =3D freq, + }, + }; + + ret =3D spi_offload_trigger_validate(st->offload_trigger_periodic, + &config); + if (ret) + return ret; + + st->offload_trigger_hz =3D config.periodic.frequency_hz; + return 0; + } else { + /* Non-offload: update hrtimer sampling period */ + if (!freq || freq > st->chip->max_rate) + return -EINVAL; + + st->sampling_period =3D ns_to_ktime(DIV_ROUND_CLOSEST_ULL + (NSEC_PER_SEC, freq)); + return 0; + } } =20 if (!st->conv_trigger) @@ -787,6 +885,224 @@ static const struct iio_buffer_setup_ops ad4691_buffe= r_setup_ops =3D { .postdisable =3D &ad4691_buffer_postdisable, }; =20 +static int ad4691_offload_buffer_postenable(struct iio_dev *indio_dev) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + struct spi_offload_trigger_config config =3D { }; + struct spi_offload_trigger *trigger; + struct spi_transfer *xfer =3D st->offload_xfer; + int ret, num_xfers =3D 0; + int active_chans[16]; + unsigned int bit; + int n_active =3D 0; + int i; + + memset(xfer, 0, sizeof(st->offload_xfer)); + + /* Collect active channels in scan order */ + iio_for_each_active_channel(indio_dev, bit) + active_chans[n_active++] =3D bit; + + ret =3D ad4691_enter_conversion_mode(st); + if (ret) + return ret; + + /* + * MANUAL_MODE uses a periodic (PWM) trigger and reads directly from + * the ADC. CNV_CLOCK_MODE uses the DATA_READY trigger and reads from + * accumulators. + */ + if (st->adc_mode =3D=3D AD4691_MANUAL_MODE) { + config.type =3D SPI_OFFLOAD_TRIGGER_PERIODIC; + config.periodic.frequency_hz =3D st->offload_trigger_hz; + trigger =3D st->offload_trigger_periodic; + if (!trigger) + return -EINVAL; + } else { + ret =3D regmap_write(st->regmap, AD4691_STATE_RESET_REG, + AD4691_STATE_RESET_ALL); + if (ret) + return ret; + + /* Configure accumulator masks - 0 =3D enabled, 1 =3D masked */ + ret =3D regmap_write(st->regmap, AD4691_ACC_MASK1_REG, + ~(*indio_dev->active_scan_mask) & 0xFF); + if (ret) + return ret; + + ret =3D regmap_write(st->regmap, AD4691_ACC_MASK2_REG, + ~(*indio_dev->active_scan_mask >> 8) & 0xFF); + if (ret) + return ret; + + /* Configure sequencer with active channels */ + ret =3D regmap_write(st->regmap, AD4691_STD_SEQ_CONFIG, + *indio_dev->active_scan_mask); + if (ret) + return ret; + + iio_for_each_active_channel(indio_dev, bit) { + ret =3D regmap_write(st->regmap, AD4691_ACC_COUNT_LIMIT(bit), + AD4691_ACC_COUNT_VAL); + if (ret) + return ret; + } + + config.type =3D SPI_OFFLOAD_TRIGGER_DATA_READY; + trigger =3D st->offload_trigger; + } + + if (st->adc_mode =3D=3D AD4691_MANUAL_MODE) { + /* + * Manual mode with CNV tied to CS: Each CS toggle triggers a + * conversion AND reads the previous conversion result (pipeline). + */ + for (i =3D 0; i < n_active; i++) { + st->offload_tx_cmd[num_xfers] =3D AD4691_ADC_CHAN(active_chans[i]) << 2= 4; + xfer[num_xfers].tx_buf =3D &st->offload_tx_cmd[num_xfers]; + xfer[num_xfers].len =3D 4; + xfer[num_xfers].bits_per_word =3D 32; + xfer[num_xfers].speed_hz =3D st->spi->max_speed_hz; + xfer[num_xfers].cs_change =3D 1; + xfer[num_xfers].cs_change_delay.value =3D 1000; + xfer[num_xfers].cs_change_delay.unit =3D SPI_DELAY_UNIT_NSECS; + /* First transfer RX is garbage - don't capture it */ + if (num_xfers) + xfer[num_xfers].offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; + num_xfers++; + } + + /* Final NOOP to flush pipeline and get last channel's data */ + st->offload_tx_cmd[num_xfers] =3D AD4691_NOOP << 24; + xfer[num_xfers].tx_buf =3D &st->offload_tx_cmd[num_xfers]; + xfer[num_xfers].len =3D 4; + xfer[num_xfers].bits_per_word =3D 32; + xfer[num_xfers].speed_hz =3D st->spi->max_speed_hz; + xfer[num_xfers].cs_change =3D 0; + xfer[num_xfers].offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; + num_xfers++; + } else { + /* + * CNV_CLOCK_MODE: single transfer per channel (2-byte cmd + + * 2-byte data =3D 4 bytes, one 32-bit SPI Engine DMA word). + * AVG_IN registers are used; RX layout: [cmd_hi, cmd_lo, d_hi, d_lo] + */ + for (i =3D 0; i < n_active; i++) { + unsigned int reg; + int ch =3D active_chans[i]; + + reg =3D AD4691_AVG_IN(ch); + st->offload_tx_cmd[ch] =3D + ((reg >> 8) | 0x80) << 24 | + (reg & 0xFF) << 16; + xfer[num_xfers].tx_buf =3D &st->offload_tx_cmd[ch]; + xfer[num_xfers].len =3D 4; + xfer[num_xfers].bits_per_word =3D 32; + xfer[num_xfers].speed_hz =3D st->spi->max_speed_hz; + xfer[num_xfers].offload_flags =3D SPI_OFFLOAD_XFER_RX_STREAM; + xfer[num_xfers].cs_change =3D 1; + num_xfers++; + } + + /* + * State reset: clear accumulator so DATA_READY can fire again. + * With bits_per_word=3D32, SPI engine transmits MSB first. + */ + st->offload_tx_reset =3D ((AD4691_STATE_RESET_REG >> 8) << 24) | + ((AD4691_STATE_RESET_REG & 0xFF) << 16) | + (0x01 << 8); + + xfer[num_xfers].tx_buf =3D &st->offload_tx_reset; + xfer[num_xfers].len =3D 4; + xfer[num_xfers].bits_per_word =3D 32; + xfer[num_xfers].speed_hz =3D st->spi->max_speed_hz; + xfer[num_xfers].cs_change =3D 0; + num_xfers++; + } + + if (num_xfers =3D=3D 0) + return -EINVAL; + + /* + * For MANUAL_MODE, validate that the trigger frequency is low enough + * for all SPI transfers to complete. Each transfer is 32 bits. + * Add 50% margin for CS setup/hold and other overhead. + */ + if (st->adc_mode =3D=3D AD4691_MANUAL_MODE) { + u64 min_period_ns; + u64 trigger_period_ns; + + /* Time for all transfers in nanoseconds, with 50% overhead margin */ + min_period_ns =3D div64_u64((u64)num_xfers * AD4691_OFFLOAD_BITS_PER_WOR= D * + NSEC_PER_SEC * 3, + st->spi->max_speed_hz * 2); + + trigger_period_ns =3D div64_u64(NSEC_PER_SEC, st->offload_trigger_hz); + + if (trigger_period_ns < min_period_ns) + return -EINVAL; + } + + spi_message_init_with_transfers(&st->offload_msg, xfer, num_xfers); + st->offload_msg.offload =3D st->offload; + + ret =3D spi_optimize_message(st->spi, &st->offload_msg); + if (ret) + return ret; + + /* + * For CNV_CLOCK_MODE, start conversions before enabling the trigger. + * If the trigger is enabled first, the SPI engine blocks waiting for + * DATA_READY, and any subsequent SPI write times out. + * + * MANUAL_MODE: CNV is tied to CS; conversion starts with each transfer. + */ + if (st->adc_mode =3D=3D AD4691_CNV_CLOCK_MODE) { + ret =3D ad4691_sampling_enable(st, true); + if (ret) + goto err_unoptimize_message; + } + + ret =3D spi_offload_trigger_enable(st->offload, trigger, &config); + if (ret) + goto err_sampling_disable; + + return 0; + +err_sampling_disable: + if (st->adc_mode =3D=3D AD4691_CNV_CLOCK_MODE) + ad4691_sampling_enable(st, false); +err_unoptimize_message: + spi_unoptimize_message(&st->offload_msg); + return ret; +} + +static int ad4691_offload_buffer_predisable(struct iio_dev *indio_dev) +{ + struct ad4691_state *st =3D iio_priv(indio_dev); + struct spi_offload_trigger *trigger; + int ret; + + trigger =3D (st->adc_mode =3D=3D AD4691_MANUAL_MODE) ? + st->offload_trigger_periodic : st->offload_trigger; + + spi_offload_trigger_disable(st->offload, trigger); + spi_unoptimize_message(&st->offload_msg); + + if (st->adc_mode =3D=3D AD4691_CNV_CLOCK_MODE) { + ret =3D ad4691_sampling_enable(st, false); + if (ret) + return ret; + } + + return ad4691_exit_conversion_mode(st); +} + +static const struct iio_buffer_setup_ops ad4691_offload_buffer_setup_ops = =3D { + .postenable =3D &ad4691_offload_buffer_postenable, + .predisable =3D &ad4691_offload_buffer_predisable, +}; + static irqreturn_t ad4691_irq(int irq, void *private) { struct iio_dev *indio_dev =3D private; @@ -981,6 +1297,54 @@ static int ad4691_config(struct ad4691_state *st) return regmap_write(st->regmap, AD4691_GPIO_MODE1_REG, AD4691_ADC_BUSY); } =20 +static int ad4691_setup_offload(struct iio_dev *indio_dev, + struct ad4691_state *st) +{ + struct device *dev =3D &st->spi->dev; + struct dma_chan *rx_dma; + int ret; + + if (st->adc_mode =3D=3D AD4691_MANUAL_MODE) { + st->offload_trigger_periodic =3D devm_spi_offload_trigger_get(dev, + st->offload, SPI_OFFLOAD_TRIGGER_PERIODIC); + if (IS_ERR(st->offload_trigger_periodic)) + return dev_err_probe(dev, + PTR_ERR(st->offload_trigger_periodic), + "failed to get periodic offload trigger\n"); + + st->offload_trigger_hz =3D AD4691_MANUAL_MODE_STD_FREQ(st->chip->num_cha= nnels, + st->spi->max_speed_hz); + } else { + struct spi_offload_trigger_info trigger_info =3D { + .fwnode =3D dev_fwnode(dev), + .ops =3D &ad4691_offload_trigger_ops, + .priv =3D st, + }; + + ret =3D devm_spi_offload_trigger_register(dev, &trigger_info); + if (ret) + return dev_err_probe(dev, ret, + "failed to register offload trigger\n"); + + st->offload_trigger =3D devm_spi_offload_trigger_get(dev, + st->offload, SPI_OFFLOAD_TRIGGER_DATA_READY); + if (IS_ERR(st->offload_trigger)) + return dev_err_probe(dev, PTR_ERR(st->offload_trigger), + "failed to get offload trigger\n"); + } + + rx_dma =3D devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload); + if (IS_ERR(rx_dma)) + return dev_err_probe(dev, PTR_ERR(rx_dma), + "failed to get offload RX DMA\n"); + + indio_dev->modes =3D INDIO_DIRECT_MODE | INDIO_BUFFER_HARDWARE; + indio_dev->setup_ops =3D &ad4691_offload_buffer_setup_ops; + + return devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, + rx_dma, IIO_BUFFER_DIRECTION_IN); +} + static int ad4691_setup_triggered_buffer(struct iio_dev *indio_dev, struct ad4691_state *st) { @@ -1064,6 +1428,14 @@ static int ad4691_probe(struct spi_device *spi) return dev_err_probe(dev, PTR_ERR(st->regmap), "Failed to initialize regmap\n"); =20 + st->offload =3D devm_spi_offload_get(dev, spi, &ad4691_offload_config); + if (IS_ERR(st->offload)) { + if (PTR_ERR(st->offload) !=3D -ENODEV) + return dev_err_probe(dev, PTR_ERR(st->offload), + "failed to get SPI offload\n"); + st->offload =3D NULL; + } + st->chip =3D spi_get_device_match_data(spi); if (!st->chip) return dev_err_probe(dev, -ENODEV, "Could not find chip info\n"); @@ -1088,10 +1460,15 @@ static int ad4691_probe(struct spi_device *spi) ? st->chip->manual_channels : st->chip->channels; indio_dev->num_channels =3D st->chip->num_channels; =20 - ret =3D ad4691_setup_triggered_buffer(indio_dev, st); - if (ret) - return ret; - + if (st->offload) { + ret =3D ad4691_setup_offload(indio_dev, st); + if (ret) + return ret; + } else { + ret =3D ad4691_setup_triggered_buffer(indio_dev, st); + if (ret) + return ret; + } return devm_iio_device_register(dev, indio_dev); } =20 @@ -1126,3 +1503,4 @@ module_spi_driver(ad4691_driver); MODULE_AUTHOR("Radu Sabau "); MODULE_DESCRIPTION("Analog Devices AD4691 Family ADC Driver"); MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_DMA_BUFFER"); --=20 2.43.0