From nobody Sat Apr 11 12:32:03 2026 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A635528E0F; Tue, 10 Mar 2026 08:43:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.12 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773132192; cv=pass; b=p0H4jo/ovBC4ZToWTsCs2W8k68zrUhLu93KDJBiL4FYdRk6hiBsGvY4aAWifPZWS0YESTWLEz9sL57iz0yWL6uD/LCYSlZ7LvPQ3F4aXZr3TL0lVrHD1oN3o2/E07WdtqPI6uFBgmxjWCRGLBXqtF8QhV6zErFVMzxfDPh2tiEE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773132192; c=relaxed/simple; bh=bDQQ07+q0sfEpEYyV7E3EisRqqof5mVY8dCFZ9d5GKQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=N1sFjAABJOVuC67kh+wyL3ewc6sC4DntSp7F+n2SZDEjC5FSv1L/ERcoLK6DjAzJvWRlQRZCJxERSriEtdBkvHSPyfkfTKqb7QjpCMihtD5bc6WwqW7xO8XuwR9eXY5lun/0XXJ2Vq/h7K5i9enHAbrcYNa2JQKutvMV1LqHAOQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=R4XJ0GXV; arc=pass smtp.client-ip=136.143.188.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="R4XJ0GXV" ARC-Seal: i=1; a=rsa-sha256; t=1773132164; cv=none; d=zohomail.com; s=zohoarc; b=TZ89Wujx/8cbriyvofgVtVPHxVa1l5aXJKROPQwK6dmkmSCKnTNwXfLCX/ZqqqjbVw+b33kr7tlFbtFlKddylm5pxQiPAgxOVjnTDh6s1YTdOcix3+i1krANTOUkHCYw9O1JDBpTe/P6okJxScA1qkAJ9ye98N0Y6+qgZ8YPZbU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1773132164; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=4/4oeENi+CU2cFcvvT4vEgwhnzZSRJGTSJJWjkZW1uc=; b=gaRL2za9DrZT1xVeL5rGMVkWcnokHkXBLiuyQp9LI/VZW0FN/y1OFPTKcqgg9QC+EL9dAY9O0JM2dU2AdM2pd7BltL2BeG1RcC5Jf0nOAPtbiAyE8btzUc+BF/yDyRVHWcQ900WJEAXK4ooASW5JE3OosxSQcqGRTyCztnLYmPk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1773132164; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=4/4oeENi+CU2cFcvvT4vEgwhnzZSRJGTSJJWjkZW1uc=; b=R4XJ0GXVNQ1PhjGCfYb6lpKvXHqlZ84VLfSPwt3SpoJBC6bdVTHAp/mau+VQ9Dw0 P0wv1tjipjyHT8hcnvz1kkjWc0lM6JIQb8fUJlxUXKx4cwjNvwRvu4QJIyQfdRdBLbU 08MANv5Jd98gajcrbmZTYGOktxaOf5saLQ1pXuCg= Received: by mx.zohomail.com with SMTPS id 1773132161806156.35921249456987; Tue, 10 Mar 2026 01:42:41 -0700 (PDT) From: Junhui Liu Date: Tue, 10 Mar 2026 16:33:59 +0800 Subject: [PATCH RFC 6/8] clk: sunxi-ng: a733: Add mod clocks support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260310-a733-clk-v1-6-36b4e9b24457@pigmoral.tech> References: <20260310-a733-clk-v1-0-36b4e9b24457@pigmoral.tech> In-Reply-To: <20260310-a733-clk-v1-0-36b4e9b24457@pigmoral.tech> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773132092; l=38950; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=bDQQ07+q0sfEpEYyV7E3EisRqqof5mVY8dCFZ9d5GKQ=; b=t6cWjtq9MoHNfDfq+a8cf5hZYY12xWvcbS/w2ut1tOgvx+8CMulUGx8fAEKW+JaMiqSUoYNyQ podOeU+SWN9D3/PZ9bU8ft69fT9iZGo4QAzej3TtGwa+JGnnJK5thn3 X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External Add the module clocks found in the Allwinner A733 SoC, including video, storage, interfaces and others. While most of these clocks are similar to those in the A523 SoC, this implementation accounts for changes in register offsets and introduces support for new modules. Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 1108 ++++++++++++++++++++++++++++= ++++ 1 file changed, 1108 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c b/drivers/clk/sunxi-ng/= ccu-sun60i-a733.c index 68457813dbbb..36b44568a56f 100644 --- a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c @@ -19,8 +19,10 @@ #include "ccu_common.h" =20 #include "ccu_div.h" +#include "ccu_gate.h" #include "ccu_mp.h" #include "ccu_mult.h" +#include "ccu_mux.h" #include "ccu_nkmp.h" #include "ccu_nm.h" =20 @@ -75,6 +77,9 @@ static const struct clk_hw *pll_ref_hws[] =3D { * - sys-24M serves as reference clock for downstream functional modules */ static CLK_FIXED_FACTOR_HWS(sys_24M_clk, "sys-24M", pll_ref_hws, 1, 1, 0); +static const struct clk_hw *sys_24M_hws[] =3D { + &sys_24M_clk.hw +}; =20 #define SUN60I_A733_PLL_DDR_REG 0x020 static struct ccu_nkmp pll_ddr_clk =3D { @@ -133,10 +138,16 @@ static CLK_FIXED_FACTOR_HWS(pll_periph0_400M_clk, "pl= l-periph0-400M", pll_periph0_2x_hws, 3, 1, 0); static CLK_FIXED_FACTOR_HWS(pll_periph0_300M_clk, "pll-periph0-300M", pll_periph0_2x_hws, 4, 1, 0); +static const struct clk_hw *pll_periph0_300M_hws[] =3D { + &pll_periph0_300M_clk.hw +}; static CLK_FIXED_FACTOR_HWS(pll_periph0_200M_clk, "pll-periph0-200M", pll_periph0_2x_hws, 6, 1, 0); static CLK_FIXED_FACTOR_HWS(pll_periph0_150M_clk, "pll-periph0-150M", pll_periph0_2x_hws, 8, 1, 0); +static const struct clk_hw *pll_periph0_150M_hws[] =3D { + &pll_periph0_150M_clk.hw +}; static CLK_FIXED_FACTOR_HWS(pll_periph0_160M_clk, "pll-periph0-160M", pll_periph0_480M_hws, 3, 1, 0); =20 @@ -483,6 +494,915 @@ static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(mbus_clk,= "mbus", mbus_parents, 0x58 CLK_IS_CRITICAL, CCU_FEATURE_UPDATE_BIT); =20 +/************************************************************************** + * mod clocks * + *************************************************************************= */ + +static const struct clk_parent_data timer_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .fw_name =3D "iosc" }, + { .fw_name =3D "losc" }, + { .hw =3D &pll_periph0_200M_clk.hw }, + { .fw_name =3D "hosc" }, +}; +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer0_clk, "timer0", timer_parents= , 0x800, + 0, 0, /* no M */ + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer1_clk, "timer1", timer_parents= , 0x804, + 0, 0, /* no M */ + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer2_clk, "timer2", timer_parents= , 0x808, + 0, 0, /* no M */ + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer3_clk, "timer3", timer_parents= , 0x80c, + 0, 0, /* no M */ + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer4_clk, "timer4", timer_parents= , 0x810, + 0, 0, /* no M */ + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer5_clk, "timer5", timer_parents= , 0x814, + 0, 0, /* no M */ + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer6_clk, "timer6", timer_parents= , 0x818, + 0, 0, /* no M */ + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer7_clk, "timer7", timer_parents= , 0x81c, + 0, 0, /* no M */ + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer8_clk, "timer8", timer_parents= , 0x820, + 0, 0, /* no M */ + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer9_clk, "timer9", timer_parents= , 0x824, + 0, 0, /* no M */ + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data avs_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .fw_name =3D "hosc" }, +}; +static SUNXI_CCU_MUX_DATA_WITH_GATE(avs_clk, "avs-clk", avs_parents, 0x880, + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *de_parents[] =3D { + &pll_de_3x_clk.common.hw, + &pll_de_4x_clk.common.hw, + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, + &pll_periph0_300M_clk.hw, + &pll_video0_4x_clk.common.hw, + &pll_video2_4x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(de_clk, "de", de_parents, 0xa00, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *di_parents[] =3D { + &pll_periph0_600M_clk.hw, + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, + &pll_video0_4x_clk.common.hw, + &pll_video2_4x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(di_clk, "di", di_parents, 0xa20, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *g2d_parents[] =3D { + &pll_periph0_400M_clk.hw, + &pll_periph0_300M_clk.hw, + &pll_video0_4x_clk.common.hw, + &pll_video1_4x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(g2d_clk, "g2d", g2d_parents, 0xa40, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *eink_parents[] =3D { + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(eink_clk, "eink", eink_parents, 0xa60, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *eink_panel_parents[] =3D { + &pll_video0_4x_clk.common.hw, + &pll_video0_3x_clk.common.hw, + &pll_video1_4x_clk.common.hw, + &pll_video1_3x_clk.common.hw, + &pll_periph0_300M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(eink_panel_clk, "eink-panel", eink_pan= el_parents, 0xa64, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *ve_enc_parents[] =3D { + &pll_ve0_clk.common.hw, + &pll_ve1_clk.common.hw, + &pll_periph0_800M_clk.common.hw, + &pll_periph0_600M_clk.hw, + &pll_periph0_480M_clk.common.hw, + &pll_de_3x_clk.common.hw, + &pll_npu_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_enc_clk, "ve-enc", ve_enc_parents, = 0xa80, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *ve_dec_parents[] =3D { + &pll_ve1_clk.common.hw, + &pll_ve0_clk.common.hw, + &pll_periph0_800M_clk.common.hw, + &pll_periph0_600M_clk.hw, + &pll_periph0_480M_clk.common.hw, + &pll_de_3x_clk.common.hw, + &pll_npu_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_dec_clk, "ve-dec", ve_dec_parents, = 0xa88, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *ce_parents[] =3D { + &sys_24M_clk.hw, + &pll_periph0_400M_clk.hw, + &pll_periph0_600M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0xac0, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *npu_parents[] =3D { + &pll_npu_clk.common.hw, + &pll_periph0_800M_clk.common.hw, + &pll_periph0_600M_clk.hw, + &pll_periph0_480M_clk.common.hw, + &pll_ve0_clk.common.hw, + &pll_ve1_clk.common.hw, + &pll_de_3x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(npu_clk, "npu", npu_parents, 0xb00, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +/* + * GPU_CLK =3D ClockSource * ((16 - M) / 16) + * Here we use a div_table to select M values that result in integer divis= ors. + */ +static struct clk_div_table gpu_div_table[] =3D { + { .val =3D 0, .div =3D 1 }, + { .val =3D 8, .div =3D 2 }, + { .val =3D 12, .div =3D 4 }, + { .val =3D 14, .div =3D 8 }, + { .val =3D 15, .div =3D 16 }, + { /* sentinel */ }, +}; +static const struct clk_parent_data gpu_parents[] =3D { + { .hw =3D &pll_gpu_clk.common.hw, }, + { .hw =3D &pll_periph0_800M_clk.common.hw, }, + { .hw =3D &pll_periph0_600M_clk.hw, }, + { .hw =3D &pll_periph0_400M_clk.hw, }, + { .hw =3D &pll_periph0_300M_clk.hw, }, + { .hw =3D &pll_periph0_200M_clk.hw, }, +}; +static struct ccu_div gpu_clk =3D { + .enable =3D BIT(31), + .div =3D _SUNXI_CCU_DIV_TABLE(0, 4, gpu_div_table), + .mux =3D _SUNXI_CCU_MUX(24, 3), + .common =3D { + .reg =3D 0xb20, + .features =3D CCU_FEATURE_UPDATE_BIT, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("gpu", gpu_parents, + &ccu_div_ops, 0), + } +}; + +static const struct clk_parent_data dram_parents[] =3D { + { .hw =3D &pll_ddr_clk.common.hw, }, + { .hw =3D &pll_periph0_800M_clk.common.hw, }, + { .hw =3D &pll_periph0_600M_clk.hw, }, + { .hw =3D &pll_de_clk.common.hw, }, + { .hw =3D &pll_npu_clk.common.hw, }, +}; +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(dram_clk, "dram", dram_parents= , 0xc00, + 0, 4, /* M */ + 0, 0, /* no P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_IS_CRITICAL, + CCU_FEATURE_UPDATE_BIT); + +static const struct clk_parent_data nand_mmc_parents[] =3D { + { .hw =3D &sys_24M_clk.hw, }, + { .hw =3D &pll_periph0_400M_clk.hw, }, + { .hw =3D &pll_periph0_300M_clk.hw, }, + { .hw =3D &pll_periph1_400M_clk.hw, }, + { .hw =3D &pll_periph1_300M_clk.hw, }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(nand0_clk, "nand0", nand_mmc_parents= , 0xc80, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(nand1_clk, "nand1", nand_mmc_parents= , 0xc84, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc0_clk, "mmc0", nand_mmc_pa= rents, 0xd00, + 0, 5, /* M */ + 8, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 2, /* post div */ + 0); +static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc1_clk, "mmc1", nand_mmc_pa= rents, 0xd10, + 0, 5, /* M */ + 8, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 2, /* post div */ + 0); + +static const struct clk_parent_data mmc2_mmc3_parents[] =3D { + { .hw =3D &sys_24M_clk.hw, }, + { .hw =3D &pll_periph0_800M_clk.common.hw }, + { .hw =3D &pll_periph0_600M_clk.hw }, + { .hw =3D &pll_periph1_800M_clk.common.hw }, + { .hw =3D &pll_periph1_600M_clk.hw }, +}; +static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc2_clk, "mmc2", mmc2_mmc3_p= arents, 0xd20, + 0, 5, /* M */ + 8, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 2, /* post div */ + 0); +static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc3_clk, "mmc3", mmc2_mmc3_p= arents, 0xd30, + 0, 5, /* M */ + 8, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 2, /* post div */ + 0); + +static const struct clk_hw *ufs_axi_parents[] =3D { + &pll_periph0_300M_clk.hw, + &pll_periph0_200M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(ufs_axi_clk, "ufs-axi", ufs_axi_parent= s, 0xd80, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data ufs_cfg_parents[] =3D { + { .hw =3D &pll_periph0_480M_clk.common.hw }, + { .fw_name =3D "hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ufs_cfg_clk, "ufs-cfg", ufs_cfg_pare= nts, 0xd84, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data spi_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .hw =3D &pll_periph0_300M_clk.hw }, + { .hw =3D &pll_periph0_200M_clk.hw }, + { .hw =3D &pll_periph1_300M_clk.hw }, + { .hw =3D &pll_periph1_200M_clk.hw }, + { .hw =3D &pll_periph0_480M_clk.common.hw }, + { .hw =3D &pll_periph1_480M_clk.common.hw }, + { .fw_name =3D "hosc"}, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(spi0_clk, "spi0", spi_parents, 0xf00, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_DUALDIV_MUX_GATE(spi1_clk, "spi1", spi_parents, 0xf08, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_DUALDIV_MUX_GATE(spi2_clk, "spi2", spi_parents, 0xf10, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_DUALDIV_MUX_GATE(spi3_clk, "spi3", spi_parents, 0xf20, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_DUALDIV_MUX_GATE(spi4_clk, "spi4", spi_parents, 0xf28, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data spif_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .hw =3D &pll_periph0_400M_clk.hw }, + { .hw =3D &pll_periph0_300M_clk.hw }, + { .hw =3D &pll_periph1_400M_clk.hw }, + { .hw =3D &pll_periph1_300M_clk.hw }, + { .hw =3D &pll_periph0_160M_clk.hw }, + { .hw =3D &pll_periph1_160M_clk.hw }, + { .fw_name =3D "hosc"}, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(spif_clk, "spif", spif_parents, 0xf18, + 0, 5, /* M */ + 8, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data gpadc_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .fw_name =3D "hosc"}, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(gpadc_clk, "gpadc", gpadc_parents, 0= xfc0, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data irrx_parents[] =3D { + { .fw_name =3D "losc"}, + { .hw =3D &sys_24M_clk.hw }, + { .fw_name =3D "hosc"}, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(irrx_clk, "irrx", irrx_parents, 0x10= 00, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data irtx_parents[] =3D { + { .fw_name =3D "losc"}, + { .hw =3D &pll_periph1_600M_clk.hw }, + { .fw_name =3D "hosc"}, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(irtx_clk, "irtx", irtx_parents, 0x10= 08, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data sgpio_parents[] =3D { + { .fw_name =3D "losc"}, + { .hw =3D &sys_24M_clk.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(sgpio_clk, "sgpio", sgpio_parents, 0= x1060, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *lpc_parents[] =3D { + &pll_video0_3x_clk.common.hw, + &pll_video1_3x_clk.common.hw, + &pll_video2_3x_clk.common.hw, + &pll_periph0_300M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(lpc_clk, "lpc", lpc_parents, 0x1080, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *i2spcm_parents[] =3D { + &pll_audio0_4x_clk.common.hw, + &pll_audio1_div2_clk.common.hw, + &pll_audio1_div5_clk.common.hw, + &pll_periph0_200M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm0_clk, "i2spcm0", i2spcm_parents= , 0x1200, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm1_clk, "i2spcm1", i2spcm_parents= , 0x1210, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm2_clk, "i2spcm2", i2spcm_parents= , 0x1220, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm3_clk, "i2spcm3", i2spcm_parents= , 0x1230, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm4_clk, "i2spcm4", i2spcm_parents= , 0x1240, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *i2spcm2_asrc_parents[] =3D { + &pll_audio0_4x_clk.common.hw, + &pll_audio1_div2_clk.common.hw, + &pll_audio1_div5_clk.common.hw, + &pll_periph0_300M_clk.hw, + &pll_periph1_300M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm2_asrc_clk, "i2spcm2_asrc", i2sp= cm2_asrc_parents, 0x1224, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *owa_tx_parents[] =3D { + &pll_audio0_4x_clk.common.hw, + &pll_audio1_div2_clk.common.hw, + &pll_audio1_div5_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(owa_tx_clk, "owa_tx", owa_tx_parents, = 0x1280, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *owa_rx_parents[] =3D { + &pll_periph0_200M_clk.hw, + &pll_periph0_300M_clk.hw, + &pll_periph0_400M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(owa_rx_clk, "owa_rx", owa_rx_parents, = 0x1284, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *dmic_parents[] =3D { + &pll_audio0_4x_clk.common.hw, + &pll_audio1_div2_clk.common.hw, + &pll_audio1_div5_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(dmic_clk, "dmic", dmic_parents, 0x12c0, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +/* + * The first parent is a 48 MHz input clock divided by 4. That 48 MHz cloc= k is + * a 2x multiplier from pll-ref synchronized by pll-periph0, and is also u= sed by + * the OHCI module. + */ +static const struct clk_parent_data usb_ohci_parents[] =3D { + { .hw =3D &pll_periph0_4x_clk.common.hw }, + { .hw =3D &sys_24M_clk.hw }, + { .fw_name =3D "losc" }, + { .fw_name =3D "iosc" }, +}; +static const struct ccu_mux_fixed_prediv usb_ohci_predivs[] =3D { + { .index =3D 0, .div =3D 200 }, + { .index =3D 1, .div =3D 2 }, +}; + +static struct ccu_mux usb_ohci0_clk =3D { + .enable =3D BIT(31), + .mux =3D { + .shift =3D 24, + .width =3D 2, + .fixed_predivs =3D usb_ohci_predivs, + .n_predivs =3D ARRAY_SIZE(usb_ohci_predivs), + }, + .common =3D { + .reg =3D 0x1300, + .features =3D CCU_FEATURE_FIXED_PREDIV, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("usb-ohci0", usb_ohci_parents, + &ccu_mux_ops, 0), + }, +}; + +static struct ccu_mux usb_ohci1_clk =3D { + .enable =3D BIT(31), + .mux =3D { + .shift =3D 24, + .width =3D 2, + .fixed_predivs =3D usb_ohci_predivs, + .n_predivs =3D ARRAY_SIZE(usb_ohci_predivs), + }, + .common =3D { + .reg =3D 0x1308, + .features =3D CCU_FEATURE_FIXED_PREDIV, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("usb-ohci1", usb_ohci_parents, + &ccu_mux_ops, 0), + }, +}; + +static const struct clk_parent_data usb_ref_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .fw_name =3D "hosc" }, +}; +static SUNXI_CCU_MUX_DATA(usb_ref_clk, "usb-ref", usb_ref_parents, 0x1340,= 24, 3, 0); + +static SUNXI_CCU_MUX_DATA(usb2_u2_ref_clk, "usb2-u2-ref", usb_ref_parents,= 0x1348, 24, 3, 0); + +static const struct clk_parent_data usb2_suspend_parents[] =3D { + { .fw_name =3D "losc" }, + { .hw =3D &sys_24M_clk.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_suspend_clk, "usb2-suspend", us= b2_suspend_parents, + 0x1350, + 0, 5, /* M */ + 24, 1, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data usb2_mf_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .hw =3D &pll_periph0_300M_clk.hw }, + { .fw_name =3D "hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_mf_clk, "usb2-mf", usb2_mf_pare= nts, + 0x1354, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data usb2_u3_utmi_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .hw =3D &pll_periph0_300M_clk.hw }, + { .fw_name =3D "hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_u3_utmi_clk, "usb2-u3-utmi", us= b2_u3_utmi_parents, + 0x1360, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data usb2_u2_pipe_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .hw =3D &pll_periph0_480M_clk.common.hw }, + { .fw_name =3D "hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_u2_pipe_clk, "usb2-u2-pipe", us= b2_u2_pipe_parents, + 0x1364, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data pcie_aux_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .fw_name =3D "losc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(pcie_aux_clk, "pcie-aux", pcie_aux_p= arents, 0x1380, + 0, 5, /* M */ + 24, 1, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *pcie_axi_slv_parents[] =3D { + &pll_periph0_600M_clk.hw, + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(pcie_axi_slv_clk, "pcie-axi-slv", pcie= _axi_slv_parents, 0x1384, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *serdes_phy_parents[] =3D { + &sys_24M_clk.hw, + &pll_periph0_600M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(serdes_phy_clk, "serdes-phy", serdes_p= hy_parents, 0x13c0, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data gmac_ptp_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .hw =3D &pll_periph0_200M_clk.hw }, + { .fw_name =3D "hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(gmac_ptp_clk, "gmac-ptp", gmac_ptp_p= arents, 0x1400, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_M_HWS_WITH_GATE(gmac0_phy_clk, "gmac0-phy", pll_periph0_1= 50M_hws, 0x1410, + 0, 5, /* M */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HWS_WITH_GATE(gmac1_phy_clk, "gmac1-phy", pll_periph0_1= 50M_hws, 0x1420, + 0, 5, /* M */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *tcon_lcd_parents[] =3D { + &pll_video0_4x_clk.common.hw, + &pll_video1_4x_clk.common.hw, + &pll_video2_4x_clk.common.hw, + &pll_periph0_2x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_lcd_p= arents, 0x1500, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_lcd_p= arents, 0x1508, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd2_clk, "tcon-lcd2", tcon_lcd_p= arents, 0x1510, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *dsi_parents[] =3D { + &sys_24M_clk.hw, + &pll_periph0_200M_clk.hw, + &pll_periph0_150M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(dsi0_clk, "dsi0", dsi_parents, 0x1580, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(dsi1_clk, "dsi1", dsi_parents, 0x1588, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *combphy_parents[] =3D { + &pll_video0_4x_clk.common.hw, + &pll_video1_4x_clk.common.hw, + &pll_video2_4x_clk.common.hw, + &pll_periph0_2x_clk.common.hw, + &pll_video0_3x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(combphy0_clk, "combphy0", combphy_pare= nts, 0x15c0, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(combphy1_clk, "combphy1", combphy_pare= nts, 0x15c4, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *edp_tv_parents[] =3D { + &pll_video0_4x_clk.common.hw, + &pll_video1_4x_clk.common.hw, + &pll_video2_4x_clk.common.hw, + &pll_periph0_2x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(edp_tv_clk, "edp-tv", edp_tv_parents, = 0x1640, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(hdmi_cec_32k_clk, "hdmi-cec-32k", pl= l_periph0_2x_hws, 0x1680, + BIT(30), /* gate */ + 36621, /* pre div */ + 0); + +static const struct clk_parent_data hdmi_cec_parents[] =3D { + { .fw_name =3D "losc" }, + { .hw =3D &hdmi_cec_32k_clk.common.hw }, +}; +static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_cec_clk, "hdmi-cec", hdmi_cec_par= ents, 0x1680, + 24, 1, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data hdmi_tv_parents[] =3D { + { .hw =3D &pll_video0_4x_clk.common.hw }, + { .hw =3D &pll_video1_4x_clk.common.hw }, + { .hw =3D &pll_video2_4x_clk.common.hw }, + { .hw =3D &pll_periph0_2x_clk.common.hw }, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(hdmi_tv_clk, "hdmi-tv", hdmi_tv_parents,= 0x1684, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data hdmi_sfr_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .fw_name =3D "hosc" }, +}; +static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_sfr_clk, "hdmi-sfr", hdmi_sfr_par= ents, 0x1690, + 24, 1, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_GATE_HWS(hdmi_esm_clk, "hdmi-esm", pll_periph0_300M_hws, = 0x1694, BIT(31), 0); + +static const struct clk_parent_data ledc_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .hw =3D &pll_periph0_600M_clk.hw }, + { .fw_name =3D "hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ledc_clk, "ledc", ledc_parents, 0x17= 00, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data csi_master_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .hw =3D &pll_video0_4x_clk.common.hw }, + { .hw =3D &pll_video0_3x_clk.common.hw }, + { .hw =3D &pll_video1_4x_clk.common.hw }, + { .hw =3D &pll_video1_3x_clk.common.hw }, + { .hw =3D &pll_video2_4x_clk.common.hw }, + { .hw =3D &pll_video2_3x_clk.common.hw }, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(csi_master0_clk, "csi_master0", csi_mast= er_parents, 0x1800, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_DUALDIV_MUX_GATE(csi_master1_clk, "csi_master1", csi_mast= er_parents, 0x1804, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_DUALDIV_MUX_GATE(csi_master2_clk, "csi_master2", csi_mast= er_parents, 0x1808, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *csi_parents[] =3D { + &pll_video2_4x_clk.common.hw, + &pll_de_4x_clk.common.hw, + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, + &pll_periph0_600M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_clk, "csi", csi_parents, 0x1840, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *isp_parents[] =3D { + &pll_video2_4x_clk.common.hw, + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, + &pll_periph0_600M_clk.hw, + &pll_video0_4x_clk.common.hw, + &pll_video1_4x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(isp_clk, "isp", isp_parents, 0x1860, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data apb2jtag_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .fw_name =3D "losc" }, + { .fw_name =3D "iosc" }, + { .hw =3D &pll_periph0_480M_clk.common.hw }, + { .hw =3D &pll_periph1_480M_clk.common.hw }, + { .hw =3D &pll_periph0_200M_clk.hw }, + { .hw =3D &pll_periph1_200M_clk.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(apb2jtag_clk, "apb2jtag", apb2jtag_p= arents, 0x1c00, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_GATE_HWS(fanout_24M_clk, "fanout-24M", sys_24M_hws, 0x1f3= 0, BIT(0), 0); +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_12M_clk, "fanout-12M", sys_24= M_hws, 0x1f30, + BIT(1), 2, 0); +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M", pll_pe= riph0_480M_hws, 0x1f30, + BIT(2), 30, 0); +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M", pll_pe= riph0_2x_hws, 0x1f30, + BIT(3), 48, 0); + +static const struct clk_parent_data fanout_27M_parents[] =3D { + { .hw =3D &pll_video0_4x_clk.common.hw }, + { .hw =3D &pll_video1_4x_clk.common.hw }, + { .hw =3D &pll_video2_4x_clk.common.hw }, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_27M_clk, "fanout-27M", fanout_27M= _parents, 0x1f34, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data fanout_pclk_parents[] =3D { + { .hw =3D &apb0_clk.common.hw } +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_pclk_clk, "fanout-pclk", fanout_p= clk_parents, 0x1f38, + 0, 5, /* M */ + 5, 5, /* N */ + 0, 0, /* no mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data fanout_parents[] =3D { + { .fw_name =3D "losc-fanout" }, + { .hw =3D &fanout_12M_clk.common.hw, }, + { .hw =3D &fanout_16M_clk.common.hw, }, + { .hw =3D &fanout_24M_clk.common.hw, }, + { .hw =3D &fanout_25M_clk.common.hw, }, + { .hw =3D &fanout_27M_clk.common.hw, }, + { .hw =3D &fanout_pclk_clk.common.hw, }, +}; +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout0_clk, "fanout0", fanout_parents= , 0x1f3c, + 0, 3, /* mux */ + BIT(21), /* gate */ + 0); +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout1_clk, "fanout1", fanout_parents= , 0x1f3c, + 3, 3, /* mux */ + BIT(22), /* gate */ + 0); +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout2_clk, "fanout2", fanout_parents= , 0x1f3c, + 6, 3, /* mux */ + BIT(23), /* gate */ + 0); +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout3_clk, "fanout3", fanout_parents= , 0x1f3c, + 9, 3, /* mux */ + BIT(24), /* gate */ + 0); + /* * Contains all clocks that are controlled by a hardware register. They * have a (sunxi) .common member, which needs to be initialised by the com= mon @@ -528,6 +1448,100 @@ static struct ccu_common *sun60i_a733_ccu_clks[] =3D= { &cpu_peri_clk.common, &nsi_clk.common, &mbus_clk.common, + &timer0_clk.common, + &timer1_clk.common, + &timer2_clk.common, + &timer3_clk.common, + &timer4_clk.common, + &timer5_clk.common, + &timer6_clk.common, + &timer7_clk.common, + &timer8_clk.common, + &timer9_clk.common, + &avs_clk.common, + &de_clk.common, + &di_clk.common, + &g2d_clk.common, + &eink_clk.common, + &eink_panel_clk.common, + &ve_enc_clk.common, + &ve_dec_clk.common, + &ce_clk.common, + &npu_clk.common, + &gpu_clk.common, + &dram_clk.common, + &nand0_clk.common, + &nand1_clk.common, + &mmc0_clk.common, + &mmc1_clk.common, + &mmc2_clk.common, + &mmc3_clk.common, + &ufs_axi_clk.common, + &ufs_cfg_clk.common, + &spi0_clk.common, + &spi1_clk.common, + &spi2_clk.common, + &spi3_clk.common, + &spi4_clk.common, + &spif_clk.common, + &gpadc_clk.common, + &irrx_clk.common, + &irtx_clk.common, + &sgpio_clk.common, + &lpc_clk.common, + &i2spcm0_clk.common, + &i2spcm1_clk.common, + &i2spcm2_clk.common, + &i2spcm3_clk.common, + &i2spcm4_clk.common, + &i2spcm2_asrc_clk.common, + &owa_tx_clk.common, + &owa_rx_clk.common, + &dmic_clk.common, + &usb_ohci0_clk.common, + &usb_ohci1_clk.common, + &usb_ref_clk.common, + &usb2_u2_ref_clk.common, + &usb2_suspend_clk.common, + &usb2_mf_clk.common, + &usb2_u3_utmi_clk.common, + &usb2_u2_pipe_clk.common, + &pcie_aux_clk.common, + &pcie_axi_slv_clk.common, + &serdes_phy_clk.common, + &gmac_ptp_clk.common, + &gmac0_phy_clk.common, + &gmac1_phy_clk.common, + &tcon_lcd0_clk.common, + &tcon_lcd1_clk.common, + &tcon_lcd2_clk.common, + &dsi0_clk.common, + &dsi1_clk.common, + &combphy0_clk.common, + &combphy1_clk.common, + &edp_tv_clk.common, + &hdmi_cec_32k_clk.common, + &hdmi_cec_clk.common, + &hdmi_tv_clk.common, + &hdmi_sfr_clk.common, + &hdmi_esm_clk.common, + &ledc_clk.common, + &csi_master0_clk.common, + &csi_master1_clk.common, + &csi_master2_clk.common, + &csi_clk.common, + &isp_clk.common, + &apb2jtag_clk.common, + &fanout_24M_clk.common, + &fanout_12M_clk.common, + &fanout_16M_clk.common, + &fanout_25M_clk.common, + &fanout_27M_clk.common, + &fanout_pclk_clk.common, + &fanout0_clk.common, + &fanout1_clk.common, + &fanout2_clk.common, + &fanout3_clk.common, }; =20 static struct clk_hw_onecell_data sun60i_a733_hw_clks =3D { @@ -584,6 +1598,100 @@ static struct clk_hw_onecell_data sun60i_a733_hw_clk= s =3D { [CLK_CPU_PERI] =3D &cpu_peri_clk.common.hw, [CLK_NSI] =3D &nsi_clk.common.hw, [CLK_MBUS] =3D &mbus_clk.common.hw, + [CLK_TIMER0] =3D &timer0_clk.common.hw, + [CLK_TIMER1] =3D &timer1_clk.common.hw, + [CLK_TIMER2] =3D &timer2_clk.common.hw, + [CLK_TIMER3] =3D &timer3_clk.common.hw, + [CLK_TIMER4] =3D &timer4_clk.common.hw, + [CLK_TIMER5] =3D &timer5_clk.common.hw, + [CLK_TIMER6] =3D &timer6_clk.common.hw, + [CLK_TIMER7] =3D &timer7_clk.common.hw, + [CLK_TIMER8] =3D &timer8_clk.common.hw, + [CLK_TIMER9] =3D &timer9_clk.common.hw, + [CLK_AVS] =3D &avs_clk.common.hw, + [CLK_DE] =3D &de_clk.common.hw, + [CLK_DI] =3D &di_clk.common.hw, + [CLK_G2D] =3D &g2d_clk.common.hw, + [CLK_EINK] =3D &eink_clk.common.hw, + [CLK_EINK_PANEL] =3D &eink_panel_clk.common.hw, + [CLK_VE_ENC] =3D &ve_enc_clk.common.hw, + [CLK_VE_DEC] =3D &ve_dec_clk.common.hw, + [CLK_CE] =3D &ce_clk.common.hw, + [CLK_NPU] =3D &npu_clk.common.hw, + [CLK_GPU] =3D &gpu_clk.common.hw, + [CLK_DRAM] =3D &dram_clk.common.hw, + [CLK_NAND0] =3D &nand0_clk.common.hw, + [CLK_NAND1] =3D &nand1_clk.common.hw, + [CLK_MMC0] =3D &mmc0_clk.common.hw, + [CLK_MMC1] =3D &mmc1_clk.common.hw, + [CLK_MMC2] =3D &mmc2_clk.common.hw, + [CLK_MMC3] =3D &mmc3_clk.common.hw, + [CLK_UFS_AXI] =3D &ufs_axi_clk.common.hw, + [CLK_UFS_CFG] =3D &ufs_cfg_clk.common.hw, + [CLK_SPI0] =3D &spi0_clk.common.hw, + [CLK_SPI1] =3D &spi1_clk.common.hw, + [CLK_SPI2] =3D &spi2_clk.common.hw, + [CLK_SPI3] =3D &spi3_clk.common.hw, + [CLK_SPI4] =3D &spi4_clk.common.hw, + [CLK_SPIF] =3D &spif_clk.common.hw, + [CLK_GPADC] =3D &gpadc_clk.common.hw, + [CLK_IRRX] =3D &irrx_clk.common.hw, + [CLK_IRTX] =3D &irtx_clk.common.hw, + [CLK_SGPIO] =3D &sgpio_clk.common.hw, + [CLK_LPC] =3D &lpc_clk.common.hw, + [CLK_I2SPCM0] =3D &i2spcm0_clk.common.hw, + [CLK_I2SPCM1] =3D &i2spcm1_clk.common.hw, + [CLK_I2SPCM2] =3D &i2spcm2_clk.common.hw, + [CLK_I2SPCM3] =3D &i2spcm3_clk.common.hw, + [CLK_I2SPCM4] =3D &i2spcm4_clk.common.hw, + [CLK_I2SPCM2_ASRC] =3D &i2spcm2_asrc_clk.common.hw, + [CLK_OWA_TX] =3D &owa_tx_clk.common.hw, + [CLK_OWA_RX] =3D &owa_rx_clk.common.hw, + [CLK_DMIC] =3D &dmic_clk.common.hw, + [CLK_USB_OHCI0] =3D &usb_ohci0_clk.common.hw, + [CLK_USB_OHCI1] =3D &usb_ohci1_clk.common.hw, + [CLK_USB_REF] =3D &usb_ref_clk.common.hw, + [CLK_USB2_U2_REF] =3D &usb2_u2_ref_clk.common.hw, + [CLK_USB2_SUSPEND] =3D &usb2_suspend_clk.common.hw, + [CLK_USB2_MF] =3D &usb2_mf_clk.common.hw, + [CLK_USB2_U3_UTMI] =3D &usb2_u3_utmi_clk.common.hw, + [CLK_USB2_U2_PIPE] =3D &usb2_u2_pipe_clk.common.hw, + [CLK_PCIE_AUX] =3D &pcie_aux_clk.common.hw, + [CLK_PCIE_AXI_SLV] =3D &pcie_axi_slv_clk.common.hw, + [CLK_SERDES_PHY] =3D &serdes_phy_clk.common.hw, + [CLK_GMAC_PTP] =3D &gmac_ptp_clk.common.hw, + [CLK_GMAC0_PHY] =3D &gmac0_phy_clk.common.hw, + [CLK_GMAC1_PHY] =3D &gmac1_phy_clk.common.hw, + [CLK_TCON_LCD0] =3D &tcon_lcd0_clk.common.hw, + [CLK_TCON_LCD1] =3D &tcon_lcd1_clk.common.hw, + [CLK_TCON_LCD2] =3D &tcon_lcd2_clk.common.hw, + [CLK_DSI0] =3D &dsi0_clk.common.hw, + [CLK_DSI1] =3D &dsi1_clk.common.hw, + [CLK_COMBPHY0] =3D &combphy0_clk.common.hw, + [CLK_COMBPHY1] =3D &combphy1_clk.common.hw, + [CLK_EDP_TV] =3D &edp_tv_clk.common.hw, + [CLK_HDMI_CEC_32K] =3D &hdmi_cec_32k_clk.common.hw, + [CLK_HDMI_CEC] =3D &hdmi_cec_clk.common.hw, + [CLK_HDMI_TV] =3D &hdmi_tv_clk.common.hw, + [CLK_HDMI_SFR] =3D &hdmi_sfr_clk.common.hw, + [CLK_HDMI_ESM] =3D &hdmi_esm_clk.common.hw, + [CLK_LEDC] =3D &ledc_clk.common.hw, + [CLK_CSI_MASTER0] =3D &csi_master0_clk.common.hw, + [CLK_CSI_MASTER1] =3D &csi_master1_clk.common.hw, + [CLK_CSI_MASTER2] =3D &csi_master2_clk.common.hw, + [CLK_CSI] =3D &csi_clk.common.hw, + [CLK_ISP] =3D &isp_clk.common.hw, + [CLK_APB2JTAG] =3D &apb2jtag_clk.common.hw, + [CLK_FANOUT_24M] =3D &fanout_24M_clk.common.hw, + [CLK_FANOUT_12M] =3D &fanout_12M_clk.common.hw, + [CLK_FANOUT_16M] =3D &fanout_16M_clk.common.hw, + [CLK_FANOUT_25M] =3D &fanout_25M_clk.common.hw, + [CLK_FANOUT_27M] =3D &fanout_27M_clk.common.hw, + [CLK_FANOUT_PCLK] =3D &fanout_pclk_clk.common.hw, + [CLK_FANOUT0] =3D &fanout0_clk.common.hw, + [CLK_FANOUT1] =3D &fanout1_clk.common.hw, + [CLK_FANOUT2] =3D &fanout2_clk.common.hw, + [CLK_FANOUT3] =3D &fanout3_clk.common.hw, }, .num =3D CLK_FANOUT3 + 1, }; --=20 2.52.0