From nobody Sat Apr 11 12:45:37 2026 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2D2A42EEC7; Tue, 10 Mar 2026 08:42:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.12 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773132178; cv=pass; b=rmen7rrgSSA9lfWLF9AF9r2VwwiD0lTLYzrVM27nrD26Tze+LhtGJNGRN1BZ9NizQSa0dTiXnXLiWMFJWjA6mNfSFtlcEFXbsvJfFRF6TrF+pnHN8UCKrJD64UqAO1XayJ5/+swRAChNlCNBqnwjlNRb0LgdBuqpcwiPby5FaLg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773132178; c=relaxed/simple; bh=M0KAonTmbGPysXsS5EwjIyqlzYOD3loSPaLLHsVEOUI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UhadL/veG0P4J80LbW0N4068SDfioqWOs7NWViCiFoWCIYIzIPRc14VgKXu3OdfyXw55Agy3GHYBxpNStUmhiSqHDllX9k7XlJ2bPUes8klbAN1tg/EagQCdTgKwEMgo+bSj2FrNG+X9Q045G632aqKTU1+4gsEhWuJOeja6KjQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=LGxTnajr; arc=pass smtp.client-ip=136.143.188.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="LGxTnajr" ARC-Seal: i=1; a=rsa-sha256; t=1773132142; cv=none; d=zohomail.com; s=zohoarc; b=ZPVQwYBgiUp3+rGsWOunImWhR8yfTx8VEqldiDyjOyVtt/3W4k3kdjdTfkl3v9SZlqQjgNDBNbU9jXDIkIKkHTBHhp+Wkspb+XvW+zGbyU9i/xoUePvFX8ic2vtijuL4sbDt6z3pWDbL/k6sjRY2Mjb8g2JXA07YRA44YWfPfEg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1773132142; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=vkpyO/6uu6avl0J1aXoXbQHkRMSznGU/rKhcEysW68g=; b=F9ig+tmKJQ9JlhRLcVGG+hkW8ivsBmfpToNAO7BishNwV7qPl0TTszYnvBsCHL7GWh1m7G0pI1RMuruh+wkdwnuoZOAkUrvOfrNP47t+4GOPIaDTCBJnRfWGih2fpB9GZo9b1hshhcCV3gbZfZtDxEDn8vc57N1Xno9m6yKxk28= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1773132142; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=vkpyO/6uu6avl0J1aXoXbQHkRMSznGU/rKhcEysW68g=; b=LGxTnajr2XrB+pWUBtVYgTzFJvpSMCLK33kGlv4W5+8OkSg529d2Pb0A0DJ7BCi+ 5QfPmxB2GmkGTlnWka4RvWxfkAQCBSnIzkLDd0jwyrzXd9Qh1ktOmvisMrqP/P+Krzb NC7M6RL7s4+9G9ybGePiTHPENQJ9jz33jVRB9g5Y= Received: by mx.zohomail.com with SMTPS id 1773132140688250.10555558560816; Tue, 10 Mar 2026 01:42:20 -0700 (PDT) From: Junhui Liu Date: Tue, 10 Mar 2026 16:33:57 +0800 Subject: [PATCH RFC 4/8] clk: sunxi-ng: a733: Add PLL clocks support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260310-a733-clk-v1-4-36b4e9b24457@pigmoral.tech> References: <20260310-a733-clk-v1-0-36b4e9b24457@pigmoral.tech> In-Reply-To: <20260310-a733-clk-v1-0-36b4e9b24457@pigmoral.tech> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773132092; l=21536; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=M0KAonTmbGPysXsS5EwjIyqlzYOD3loSPaLLHsVEOUI=; b=bpfuVHa0NuLiMcmYEIwS+rZSZwUSAgT1RFRvRQZi1uMkUHO2G2fM2Q2CqoDFlLZcsbpBzAlGP kdRp9mkHIrCAqtyIN28r/8cE/SErihATzdlCo04atl8OrgOxfBS8SdC X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External Add PLL clock support for the main CCU of the Allwinner A733 SoC. The structure is mostly similar to the sun55i, with the addition of a PLL_REF clock that normalizes the hardware-detected DCXO/hosc frequency (19.2MHz, 24MHz, or 26MHz) into a consistent 24MHz reference for all subsequent PLLs. The behaviors of PLL_AUDIO0 and PLL_AUDIO1 are ported from the vendor driver. Specifically, PLL_AUDIO0 is configured with SDM parameters to provide a 22.5792MHz * 4 output, while PLL_AUDIO1 is integrated into the main CCU without using SDM. Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/sunxi-ng/Makefile | 2 + drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 535 +++++++++++++++++++++++++++++= ++++ 3 files changed, 542 insertions(+) diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 202e793dc754..cffa83056934 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -67,6 +67,11 @@ config SUN55I_A523_R_CCU default ARCH_SUNXI depends on ARM64 || COMPILE_TEST =20 +config SUN60I_A733_CCU + tristate "Support for the Allwinner A733 CCU" + default ARCH_SUNXI + depends on ARM64 || COMPILE_TEST + config SUN60I_A733_R_CCU tristate "Support for the Allwinner A733 PRCM CCU" default ARCH_SUNXI diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index d3702bdb7a23..3a39eb9287da 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_SUN50I_H616_CCU) +=3D sun50i-h616-ccu.o obj-$(CONFIG_SUN55I_A523_CCU) +=3D sun55i-a523-ccu.o obj-$(CONFIG_SUN55I_A523_MCU_CCU) +=3D sun55i-a523-mcu-ccu.o obj-$(CONFIG_SUN55I_A523_R_CCU) +=3D sun55i-a523-r-ccu.o +obj-$(CONFIG_SUN60I_A733_CCU) +=3D sun60i-a733-ccu.o obj-$(CONFIG_SUN60I_A733_R_CCU) +=3D sun60i-a733-r-ccu.o obj-$(CONFIG_SUN4I_A10_CCU) +=3D sun4i-a10-ccu.o obj-$(CONFIG_SUN5I_CCU) +=3D sun5i-ccu.o @@ -65,6 +66,7 @@ sun50i-h616-ccu-y +=3D ccu-sun50i-h616.o sun55i-a523-ccu-y +=3D ccu-sun55i-a523.o sun55i-a523-mcu-ccu-y +=3D ccu-sun55i-a523-mcu.o sun55i-a523-r-ccu-y +=3D ccu-sun55i-a523-r.o +sun60i-a733-ccu-y +=3D ccu-sun60i-a733.o sun60i-a733-r-ccu-y +=3D ccu-sun60i-a733-r.o sun4i-a10-ccu-y +=3D ccu-sun4i-a10.o sun5i-ccu-y +=3D ccu-sun5i.o diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c b/drivers/clk/sunxi-ng/= ccu-sun60i-a733.c new file mode 100644 index 000000000000..cf819504c51f --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c @@ -0,0 +1,535 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 rengaomin@allwinnertech.com + * Copyright (C) 2026 Junhui Liu + * Based on the A523 CCU driver: + * Copyright (C) 2023-2024 Arm Ltd. + */ + +#include +#include +#include +#include + +#include +#include + +#include "../clk.h" + +#include "ccu_common.h" + +#include "ccu_div.h" +#include "ccu_mult.h" +#include "ccu_nkmp.h" +#include "ccu_nm.h" + +/* + * The DCXO oscillator, the root of most of the clock tree. + * The physical crystal frequency (19.2MHz, 24MHz, or 26MHz) is + * hardware-detected by the RTC and represented here as "hosc". + */ +static const struct clk_parent_data hosc[] =3D { + { .fw_name =3D "hosc" } +}; + +/************************************************************************** + * PLLs * + *************************************************************************= */ + +#define SUN60I_A733_PLL_REF_REG 0x000 +static struct ccu_nkmp pll_ref_clk =3D { + .enable =3D BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT(8, 8), + .m =3D _SUNXI_CCU_DIV(16, 7), /* output divider */ + .p =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_REF_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("pll-ref", hosc, + &ccu_nkmp_ops, + CLK_SET_RATE_GATE), + }, +}; + +/* + * Most clock-defining macros expect an *array* of parent clocks, even if + * they do not contain a muxer to select between different parents. + * The macros ending in just _HW take a simple clock pointer, but then cre= ate + * a single-entry array out of that. The macros using _HWS take such an + * array (even when it is a single entry one), this avoids having those + * helper arrays created inside *every* clock definition. + * This means for every clock that is referenced more than once it is + * useful to create such a dummy array and use _HWS. + */ +static const struct clk_hw *pll_ref_hws[] =3D { + &pll_ref_clk.common.hw +}; + +#define SUN60I_A733_PLL_DDR_REG 0x020 +static struct ccu_nkmp pll_ddr_clk =3D { + .enable =3D BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(20, 3), /* output divider */ + .p =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_DDR_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-ddr", pll_ref_hws, + &ccu_nkmp_ops, + CLK_SET_RATE_GATE | + CLK_IS_CRITICAL), + }, +}; + +/* + * There is no actual clock output with that frequency (2.4 GHz), instead = it + * has multiple outputs with adjustable dividers from that base frequency. + * Model them separately as divider clocks based on that parent here. + */ +#define SUN60I_A733_PLL_PERIPH0_REG 0x0a0 +static struct ccu_nm pll_periph0_4x_clk =3D { + .enable =3D BIT(25) | BIT(26) | BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_PERIPH0_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-periph0-4x", + pll_ref_hws, &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_periph0_4x_hws[] =3D { + &pll_periph0_4x_clk.common.hw +}; + +static SUNXI_CCU_M_HWS(pll_periph0_2x_clk, "pll-periph0-2x", pll_periph0_4= x_hws, + SUN60I_A733_PLL_PERIPH0_REG, 20, 3, 0); +static const struct clk_hw *pll_periph0_2x_hws[] =3D { + &pll_periph0_2x_clk.common.hw +}; +static SUNXI_CCU_M_HWS(pll_periph0_800M_clk, "pll-periph0-800M", pll_perip= h0_4x_hws, + SUN60I_A733_PLL_PERIPH0_REG, 16, 3, 0); +static SUNXI_CCU_M_HWS(pll_periph0_480M_clk, "pll-periph0-480M", pll_perip= h0_4x_hws, + SUN60I_A733_PLL_PERIPH0_REG, 2, 3, 0); +static const struct clk_hw *pll_periph0_480M_hws[] =3D { + &pll_periph0_480M_clk.common.hw +}; +static CLK_FIXED_FACTOR_HWS(pll_periph0_600M_clk, "pll-periph0-600M", + pll_periph0_2x_hws, 2, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph0_400M_clk, "pll-periph0-400M", + pll_periph0_2x_hws, 3, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph0_300M_clk, "pll-periph0-300M", + pll_periph0_2x_hws, 4, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph0_200M_clk, "pll-periph0-200M", + pll_periph0_2x_hws, 6, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph0_150M_clk, "pll-periph0-150M", + pll_periph0_2x_hws, 8, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph0_160M_clk, "pll-periph0-160M", + pll_periph0_480M_hws, 3, 1, 0); + +#define SUN60I_A733_PLL_PERIPH1_REG 0x0c0 +static struct ccu_nm pll_periph1_4x_clk =3D { + .enable =3D BIT(25) | BIT(26) | BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_PERIPH1_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-periph1-4x", + pll_ref_hws, &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_periph1_4x_hws[] =3D { + &pll_periph1_4x_clk.common.hw +}; + +static SUNXI_CCU_M_HWS(pll_periph1_2x_clk, "pll-periph1-2x", pll_periph1_4= x_hws, + SUN60I_A733_PLL_PERIPH1_REG, 20, 3, 0); +static const struct clk_hw *pll_periph1_2x_hws[] =3D { + &pll_periph1_2x_clk.common.hw +}; +static SUNXI_CCU_M_HWS(pll_periph1_800M_clk, "pll-periph1-800M", pll_perip= h1_4x_hws, + SUN60I_A733_PLL_PERIPH1_REG, 16, 3, 0); +static SUNXI_CCU_M_HWS(pll_periph1_480M_clk, "pll-periph1-480M", pll_perip= h1_4x_hws, + SUN60I_A733_PLL_PERIPH1_REG, 2, 3, 0); +static const struct clk_hw *pll_periph1_480M_hws[] =3D { + &pll_periph1_480M_clk.common.hw +}; +static CLK_FIXED_FACTOR_HWS(pll_periph1_600M_clk, "pll-periph1-600M", + pll_periph1_2x_hws, 2, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph1_400M_clk, "pll-periph1-400M", + pll_periph1_2x_hws, 3, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph1_300M_clk, "pll-periph1-300M", + pll_periph1_2x_hws, 4, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph1_200M_clk, "pll-periph1-200M", + pll_periph1_2x_hws, 6, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph1_150M_clk, "pll-periph1-150M", + pll_periph1_2x_hws, 8, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph1_160M_clk, "pll-periph1-160M", + pll_periph1_480M_hws, 3, 1, 0); + +#define SUN60I_A733_PLL_GPU_REG 0x0e0 +static struct ccu_nkmp pll_gpu_clk =3D { + .enable =3D BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(20, 3), /* output divider */ + .p =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_GPU_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-gpu", pll_ref_hws, + &ccu_nkmp_ops, + CLK_SET_RATE_GATE), + }, +}; + +#define SUN60I_A733_PLL_VIDEO0_REG 0x120 +static struct ccu_nm pll_video0_8x_clk =3D { + .enable =3D BIT(26) | BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_VIDEO0_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-video0-8x", pll_ref_hws, + &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_video0_8x_hws[] =3D { + &pll_video0_8x_clk.common.hw +}; +static SUNXI_CCU_M_HWS(pll_video0_4x_clk, "pll-video0-4x", pll_video0_8x_h= ws, + SUN60I_A733_PLL_VIDEO0_REG, 20, 3, 0); +static SUNXI_CCU_M_HWS(pll_video0_3x_clk, "pll-video0-3x", pll_video0_8x_h= ws, + SUN60I_A733_PLL_VIDEO0_REG, 16, 3, 0); + +#define SUN60I_A733_PLL_VIDEO1_REG 0x140 +static struct ccu_nm pll_video1_8x_clk =3D { + .enable =3D BIT(26) | BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_VIDEO1_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-video1-8x", pll_ref_hws, + &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_video1_8x_hws[] =3D { + &pll_video1_8x_clk.common.hw +}; +static SUNXI_CCU_M_HWS(pll_video1_4x_clk, "pll-video1-4x", pll_video1_8x_h= ws, + SUN60I_A733_PLL_VIDEO1_REG, 20, 3, 0); +static SUNXI_CCU_M_HWS(pll_video1_3x_clk, "pll-video1-3x", pll_video1_8x_h= ws, + SUN60I_A733_PLL_VIDEO1_REG, 16, 3, 0); + +#define SUN60I_A733_PLL_VIDEO2_REG 0x160 +static struct ccu_nm pll_video2_8x_clk =3D { + .enable =3D BIT(26) | BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_VIDEO2_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-video2-8x", pll_ref_hws, + &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_video2_8x_hws[] =3D { + &pll_video2_8x_clk.common.hw +}; +static SUNXI_CCU_M_HWS(pll_video2_4x_clk, "pll-video2-4x", pll_video2_8x_h= ws, + SUN60I_A733_PLL_VIDEO2_REG, 20, 3, 0); +static SUNXI_CCU_M_HWS(pll_video2_3x_clk, "pll-video2-3x", pll_video2_8x_h= ws, + SUN60I_A733_PLL_VIDEO2_REG, 16, 3, 0); + +#define SUN60I_A733_PLL_VE0_REG 0x220 +static struct ccu_nkmp pll_ve0_clk =3D { + .enable =3D BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(20, 3), /* output divider */ + .p =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_VE0_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-ve0", pll_ref_hws, + &ccu_nkmp_ops, + CLK_SET_RATE_GATE), + }, +}; + +#define SUN60I_A733_PLL_VE1_REG 0x240 +static struct ccu_nkmp pll_ve1_clk =3D { + .enable =3D BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(20, 3), /* output divider */ + .p =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_VE1_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-ve1", pll_ref_hws, + &ccu_nkmp_ops, + CLK_SET_RATE_GATE), + }, +}; + +/* + * PLL_AUDIO0 has a m1 divider in addition to the usual N, M factors. + * Since we only need some fixed frequency from this PLL (22.5792MHz x 4), + * ignore the divider and force it to 1 (encoded as 0), in the probe funct= ion + * below. + * The M factor must be an even number to produce a 50% duty cycle output. + */ +#define SUN60I_A733_PLL_AUDIO0_REG 0x260 +static struct ccu_sdm_setting pll_audio0_sdm_table[] =3D { + { .rate =3D 90316800, .pattern =3D 0xa002872b, .m =3D 20, .n =3D 75 }, /*= 22.5792 * 4 */ +}; + +static struct ccu_nm pll_audio0_4x_clk =3D { + .enable =3D BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(16, 7), + .sdm =3D _SUNXI_CCU_SDM_DUAL_PAT(pll_audio0_sdm_table, + 0x268, BIT(31), + 0x26c, BIT(27) | BIT(31)), + .common =3D { + .reg =3D SUN60I_A733_PLL_AUDIO0_REG, + .features =3D CCU_FEATURE_SIGMA_DELTA_MOD, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-audio0-4x", pll_ref_hws, + &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +#define SUN60I_A733_PLL_AUDIO1_REG 0x280 +static struct ccu_nm pll_audio1_clk =3D { + .enable =3D BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_AUDIO1_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-audio1", pll_ref_hws, + &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_audio1_hws[] =3D { + &pll_audio1_clk.common.hw +}; +static SUNXI_CCU_M_HWS(pll_audio1_div2_clk, "pll-audio1-div2", pll_audio1_= hws, + SUN60I_A733_PLL_AUDIO1_REG, 20, 3, 0); +static SUNXI_CCU_M_HWS(pll_audio1_div5_clk, "pll-audio1-div5", pll_audio1_= hws, + SUN60I_A733_PLL_AUDIO1_REG, 16, 3, 0); + +#define SUN60I_A733_PLL_NPU_REG 0x2a0 +static struct ccu_nkmp pll_npu_clk =3D { + .enable =3D BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(20, 3), /* output divider */ + .p =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_NPU_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-npu", pll_ref_hws, + &ccu_nkmp_ops, + CLK_SET_RATE_GATE), + }, +}; + +#define SUN60I_A733_PLL_DE_REG 0x2e0 +static struct ccu_nm pll_de_clk =3D { + .enable =3D BIT(26) | BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_DE_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-de", pll_ref_hws, + &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_de_hws[] =3D { + &pll_de_clk.common.hw +}; +static SUNXI_CCU_M_HWS(pll_de_4x_clk, "pll-de-4x", pll_de_hws, + SUN60I_A733_PLL_DE_REG, 20, 3, 0); +static SUNXI_CCU_M_HWS(pll_de_3x_clk, "pll-de-3x", pll_de_hws, + SUN60I_A733_PLL_DE_REG, 16, 3, 0); + +/* + * Contains all clocks that are controlled by a hardware register. They + * have a (sunxi) .common member, which needs to be initialised by the com= mon + * sunxi CCU code, to be filled with the MMIO base address and the shared = lock. + */ +static struct ccu_common *sun60i_a733_ccu_clks[] =3D { + &pll_ref_clk.common, + &pll_ddr_clk.common, + &pll_periph0_4x_clk.common, + &pll_periph0_2x_clk.common, + &pll_periph0_800M_clk.common, + &pll_periph0_480M_clk.common, + &pll_periph1_4x_clk.common, + &pll_periph1_2x_clk.common, + &pll_periph1_800M_clk.common, + &pll_periph1_480M_clk.common, + &pll_gpu_clk.common, + &pll_video0_8x_clk.common, + &pll_video0_4x_clk.common, + &pll_video0_3x_clk.common, + &pll_video1_8x_clk.common, + &pll_video1_4x_clk.common, + &pll_video1_3x_clk.common, + &pll_video2_8x_clk.common, + &pll_video2_4x_clk.common, + &pll_video2_3x_clk.common, + &pll_ve0_clk.common, + &pll_ve1_clk.common, + &pll_audio0_4x_clk.common, + &pll_audio1_clk.common, + &pll_audio1_div2_clk.common, + &pll_audio1_div5_clk.common, + &pll_npu_clk.common, + &pll_de_clk.common, + &pll_de_4x_clk.common, + &pll_de_3x_clk.common, +}; + +static struct clk_hw_onecell_data sun60i_a733_hw_clks =3D { + .hws =3D { + [CLK_PLL_REF] =3D &pll_ref_clk.common.hw, + [CLK_PLL_DDR] =3D &pll_ddr_clk.common.hw, + [CLK_PLL_PERIPH0_4X] =3D &pll_periph0_4x_clk.common.hw, + [CLK_PLL_PERIPH0_2X] =3D &pll_periph0_2x_clk.common.hw, + [CLK_PLL_PERIPH0_800M] =3D &pll_periph0_800M_clk.common.hw, + [CLK_PLL_PERIPH0_480M] =3D &pll_periph0_480M_clk.common.hw, + [CLK_PLL_PERIPH0_600M] =3D &pll_periph0_600M_clk.hw, + [CLK_PLL_PERIPH0_400M] =3D &pll_periph0_400M_clk.hw, + [CLK_PLL_PERIPH0_300M] =3D &pll_periph0_300M_clk.hw, + [CLK_PLL_PERIPH0_200M] =3D &pll_periph0_200M_clk.hw, + [CLK_PLL_PERIPH0_160M] =3D &pll_periph0_160M_clk.hw, + [CLK_PLL_PERIPH0_150M] =3D &pll_periph0_150M_clk.hw, + [CLK_PLL_PERIPH1_4X] =3D &pll_periph1_4x_clk.common.hw, + [CLK_PLL_PERIPH1_2X] =3D &pll_periph1_2x_clk.common.hw, + [CLK_PLL_PERIPH1_800M] =3D &pll_periph1_800M_clk.common.hw, + [CLK_PLL_PERIPH1_480M] =3D &pll_periph1_480M_clk.common.hw, + [CLK_PLL_PERIPH1_600M] =3D &pll_periph1_600M_clk.hw, + [CLK_PLL_PERIPH1_400M] =3D &pll_periph1_400M_clk.hw, + [CLK_PLL_PERIPH1_300M] =3D &pll_periph1_300M_clk.hw, + [CLK_PLL_PERIPH1_200M] =3D &pll_periph1_200M_clk.hw, + [CLK_PLL_PERIPH1_160M] =3D &pll_periph1_160M_clk.hw, + [CLK_PLL_PERIPH1_150M] =3D &pll_periph1_150M_clk.hw, + [CLK_PLL_GPU] =3D &pll_gpu_clk.common.hw, + [CLK_PLL_VIDEO0_8X] =3D &pll_video0_8x_clk.common.hw, + [CLK_PLL_VIDEO0_4X] =3D &pll_video0_4x_clk.common.hw, + [CLK_PLL_VIDEO0_3X] =3D &pll_video0_3x_clk.common.hw, + [CLK_PLL_VIDEO1_8X] =3D &pll_video1_8x_clk.common.hw, + [CLK_PLL_VIDEO1_4X] =3D &pll_video1_4x_clk.common.hw, + [CLK_PLL_VIDEO1_3X] =3D &pll_video1_3x_clk.common.hw, + [CLK_PLL_VIDEO2_8X] =3D &pll_video2_8x_clk.common.hw, + [CLK_PLL_VIDEO2_4X] =3D &pll_video2_4x_clk.common.hw, + [CLK_PLL_VIDEO2_3X] =3D &pll_video2_3x_clk.common.hw, + [CLK_PLL_VE0] =3D &pll_ve0_clk.common.hw, + [CLK_PLL_VE1] =3D &pll_ve1_clk.common.hw, + [CLK_PLL_AUDIO0_4X] =3D &pll_audio0_4x_clk.common.hw, + [CLK_PLL_AUDIO1] =3D &pll_audio1_clk.common.hw, + [CLK_PLL_AUDIO1_DIV2] =3D &pll_audio1_div2_clk.common.hw, + [CLK_PLL_AUDIO1_DIV5] =3D &pll_audio1_div5_clk.common.hw, + [CLK_PLL_NPU] =3D &pll_npu_clk.common.hw, + [CLK_PLL_DE] =3D &pll_de_clk.common.hw, + [CLK_PLL_DE_4X] =3D &pll_de_4x_clk.common.hw, + [CLK_PLL_DE_3X] =3D &pll_de_3x_clk.common.hw, + }, + .num =3D CLK_FANOUT3 + 1, +}; + +static const struct sunxi_ccu_desc sun60i_a733_ccu_desc =3D { + .ccu_clks =3D sun60i_a733_ccu_clks, + .num_ccu_clks =3D ARRAY_SIZE(sun60i_a733_ccu_clks), + + .hw_clks =3D &sun60i_a733_hw_clks, +}; + +static const u32 pll_regs[] =3D { + SUN60I_A733_PLL_REF_REG, + SUN60I_A733_PLL_DDR_REG, + SUN60I_A733_PLL_PERIPH0_REG, + SUN60I_A733_PLL_PERIPH1_REG, + SUN60I_A733_PLL_GPU_REG, + SUN60I_A733_PLL_VIDEO0_REG, + SUN60I_A733_PLL_VIDEO1_REG, + SUN60I_A733_PLL_VIDEO2_REG, + SUN60I_A733_PLL_VE0_REG, + SUN60I_A733_PLL_VE1_REG, + SUN60I_A733_PLL_AUDIO0_REG, + SUN60I_A733_PLL_AUDIO1_REG, + SUN60I_A733_PLL_NPU_REG, + SUN60I_A733_PLL_DE_REG, +}; + +static int sun60i_a733_ccu_probe(struct platform_device *pdev) +{ + void __iomem *reg; + u32 val; + int i, ret; + + reg =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(reg)) + return PTR_ERR(reg); + + /* + * The PLL clock code does not model all bits, for instance it does + * not support a separate enable and gate bit. We present the + * gate bit(27) as the enable bit, but then have to set the + * PLL Enable, LDO Enable, and Lock Enable bits on all PLLs here. + */ + for (i =3D 0; i < ARRAY_SIZE(pll_regs); i++) { + val =3D readl(reg + pll_regs[i]); + val |=3D BIT(31) | BIT(30) | BIT(29); + writel(val, reg + pll_regs[i]); + } + + /* Enforce m1 =3D 0 for PLL_AUDIO0 */ + val =3D readl(reg + SUN60I_A733_PLL_AUDIO0_REG); + val &=3D ~BIT(1); + writel(val, reg + SUN60I_A733_PLL_AUDIO0_REG); + + ret =3D devm_sunxi_ccu_probe(&pdev->dev, reg, &sun60i_a733_ccu_desc); + if (ret) + return ret; + + return 0; +} + +static const struct of_device_id sun60i_a733_ccu_ids[] =3D { + { .compatible =3D "allwinner,sun60i-a733-ccu" }, + { /* sentinel */ } +}; + +static struct platform_driver sun60i_a733_ccu_driver =3D { + .probe =3D sun60i_a733_ccu_probe, + .driver =3D { + .name =3D "sun60i-a733-ccu", + .suppress_bind_attrs =3D true, + .of_match_table =3D sun60i_a733_ccu_ids, + }, +}; +module_platform_driver(sun60i_a733_ccu_driver); + +MODULE_IMPORT_NS("SUNXI_CCU"); +MODULE_DESCRIPTION("Support for the Allwinner A733 CCU"); +MODULE_LICENSE("GPL"); --=20 2.52.0