From nobody Sat Apr 11 10:32:53 2026 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 348F7254AFF; Tue, 10 Mar 2026 08:42:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.12 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773132139; cv=pass; b=VSdYVGizB4+72899MppZlQKLFIoMoaWgY3SSzhMdZPiRVuLq7MeRaGd6lFJY/4EfjvTKbtV+LRqShMu9dH6IlcZiWDO5PbXwV+aV6P+rxwAh1akBGgIzIvnUnwer1F3H707af4SjC7u9P3U9Luq/2oI2h1J6Qby2/ENs6cFAbKQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773132139; c=relaxed/simple; bh=jzY0MrwTsMV3x5En1zOm/w8FpmhJKLYY3avhAHLTIMw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=V3g1m58ZMgMDcQbW7PjfkDzr4Xxgi0KRu2NPHi3UzYHxw6G2XFsbqO0fSuc/yYIJmFTX1l6Re8ZOgE/s0SzixM0ezbOPQ5tRmmi9grDv06BUfKI4PYU9/omYfoIOzjqKm72ojllwSYFSg4rDpY+uGi3G9AWnrDrxqS0wDNdmAFo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech; spf=pass smtp.mailfrom=pigmoral.tech; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b=AoSSp5UU; arc=pass smtp.client-ip=136.143.188.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pigmoral.tech Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=pigmoral.tech header.i=junhui.liu@pigmoral.tech header.b="AoSSp5UU" ARC-Seal: i=1; a=rsa-sha256; t=1773132114; cv=none; d=zohomail.com; s=zohoarc; b=fjyTlIMtB/Pugk5GPLgHLsfNdcY2wWSz2W3SFScKmDdPe2UUI5bT1lY9WB+5Smr59bf/1HqGeoNDyhhQaaIs7RZPVROnFrPB1S6Sr4si593OMPMUHu/cF3wolT+mu+Ro4aOpPgaqIsPorfdWM8uSvj1pLTmAm/Kx15QPjAxnlNM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1773132114; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=/GKE/5Vy5rvMzqCLP4HD5HJ2pRY4KuZqKqAV6U6txtE=; b=fquY+FCGcW0SrM15X9w0ay2rVO+4NElZd0njsMfyhfsipqRWVs4xyIqJG2/WDqLz/XLqfs4YtNCHMey5cxoDsWLGlQx68lOdgrHWZNr8cJS3eE7djkjz0iMz7I94ZRlMYImGnu5SfRQvyN+etRuMqVOuCNOomTNNDR8RbB7+4qg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=pigmoral.tech; spf=pass smtp.mailfrom=junhui.liu@pigmoral.tech; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1773132114; s=zmail; d=pigmoral.tech; i=junhui.liu@pigmoral.tech; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=/GKE/5Vy5rvMzqCLP4HD5HJ2pRY4KuZqKqAV6U6txtE=; b=AoSSp5UUsByE6ebLTNMPdpZcPre9j3qIet8FbtkSpbqpujriuVHixfhdC5z7h9uI W+Ue7ijLNfOBM8InCbmZ08sUDBJ0PMi/mZWc9nPrdtZv5i5Ih5AHiyy+VZg6ObbfKep OvrLphc5rFd03/OGicnjUDInpxOS+iz32+ZB41JE= Received: by mx.zohomail.com with SMTPS id 1773132111547988.6413668944255; Tue, 10 Mar 2026 01:41:51 -0700 (PDT) From: Junhui Liu Date: Tue, 10 Mar 2026 16:33:54 +0800 Subject: [PATCH RFC 1/8] dt-bindings: clk: sun60i-a733-ccu: Add allwinner A733 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260310-a733-clk-v1-1-36b4e9b24457@pigmoral.tech> References: <20260310-a733-clk-v1-0-36b4e9b24457@pigmoral.tech> In-Reply-To: <20260310-a733-clk-v1-0-36b4e9b24457@pigmoral.tech> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773132092; l=18765; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=jzY0MrwTsMV3x5En1zOm/w8FpmhJKLYY3avhAHLTIMw=; b=p/YGyZ9D1nHvkqOFETjFGn7RWqho1Mr6+o4+NdUcxdHrlOMzf9xx0Od9hdPwFEvGeN+lH++lT PZ++IQClVhlATNlln+OooHfahDqTX92j5D8RBv8sNJL8IvTbK5beKED X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External The CCU and R-CCU (PRCM) modules provide clocks and reset functions for the Allwinner A733 SoC. The clock architecture of the A733 is evolved from the A523, though the root clocking strategy transitions from a static oscillator frequency in the Devicetree to the "hosc" clock, which is determined by choosing from three possible frequencies (19.2MHz, 24MHz, or 26MHz) by the RTC hardware, and finally feeds the CCU and R-CCU. Additionally, the MCU_CCU module found in previous designs is removed from the A733, and the clock tree is expanded with more clock outputs to support new functional modules. Signed-off-by: Junhui Liu --- .../bindings/clock/allwinner,sun60i-a733-ccu.yaml | 107 ++++++++ include/dt-bindings/clock/sun60i-a733-ccu.h | 289 +++++++++++++++++= ++++ include/dt-bindings/clock/sun60i-a733-r-ccu.h | 39 +++ include/dt-bindings/reset/sun60i-a733-ccu.h | 131 ++++++++++ include/dt-bindings/reset/sun60i-a733-r-ccu.h | 23 ++ 5 files changed, 589 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-= ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-cc= u.yaml new file mode 100644 index 000000000000..aff3ff731285 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun60i-a733-ccu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A733 Clock Control Unit + +maintainers: + - Junhui Liu + +properties: + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + compatible: + enum: + - allwinner,sun60i-a733-ccu + - allwinner,sun60i-a733-r-ccu + + reg: + maxItems: 1 + + clocks: + minItems: 4 + maxItems: 7 + + clock-names: + minItems: 4 + maxItems: 7 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-names + +allOf: + - if: + properties: + compatible: + enum: + - allwinner,sun60i-a733-ccu + + then: + properties: + clocks: + items: + - description: High Frequency Oscillator (19.2MHz, 24MHz, or 2= 6MHz) + - description: Low Frequency Oscillator (usually at 32kHz) + - description: Internal Oscillator + - description: Low Frequency Oscillator fanout + + clock-names: + items: + - const: hosc + - const: losc + - const: iosc + - const: losc-fanout + + - if: + properties: + compatible: + enum: + - allwinner,sun60i-a733-r-ccu + + then: + properties: + clocks: + items: + - description: High Frequency Oscillator (19.2MHz, 24MHz, or 2= 6MHz) + - description: Low Frequency Oscillator (usually at 32kHz) + - description: Internal Oscillator + - description: System 24MHz Clock + - description: Peripherals PLL 0 (200 MHz output) + - description: Peripherals PLL 0 (300 MHz output) + - description: Peripherals PLL 1 (300 MHz output) + + clock-names: + items: + - const: hosc + - const: losc + - const: iosc + - const: sys-24m + - const: pll-periph0-200m + - const: pll-periph0-300m + - const: pll-periph1-300m + +additionalProperties: false + +examples: + - | + clock-controller@2002000 { + compatible =3D "allwinner,sun60i-a733-ccu"; + reg =3D <0x02002000 0x2000>; + clocks =3D <&rtc 2>, <&rtc 1>, <&rtc 0>, <&rtc 4>; + clock-names =3D "hosc", "losc", "iosc", "losc-fanout"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + +... diff --git a/include/dt-bindings/clock/sun60i-a733-ccu.h b/include/dt-bindi= ngs/clock/sun60i-a733-ccu.h new file mode 100644 index 000000000000..1a98bea8ca9a --- /dev/null +++ b/include/dt-bindings/clock/sun60i-a733-ccu.h @@ -0,0 +1,289 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2026 Junhui Liu + */ + +#ifndef _DT_BINDINGS_CLK_SUN60I_A733_CCU_H_ +#define _DT_BINDINGS_CLK_SUN60I_A733_CCU_H_ + +#define CLK_PLL_REF 0 +#define CLK_SYS_24M 1 +#define CLK_PLL_DDR 2 +#define CLK_PLL_PERIPH0_4X 3 +#define CLK_PLL_PERIPH0_2X 4 +#define CLK_PLL_PERIPH0_800M 5 +#define CLK_PLL_PERIPH0_480M 6 +#define CLK_PLL_PERIPH0_600M 7 +#define CLK_PLL_PERIPH0_400M 8 +#define CLK_PLL_PERIPH0_300M 9 +#define CLK_PLL_PERIPH0_200M 10 +#define CLK_PLL_PERIPH0_160M 11 +#define CLK_PLL_PERIPH0_150M 12 +#define CLK_PLL_PERIPH1_4X 13 +#define CLK_PLL_PERIPH1_2X 14 +#define CLK_PLL_PERIPH1_800M 15 +#define CLK_PLL_PERIPH1_480M 16 +#define CLK_PLL_PERIPH1_600M 17 +#define CLK_PLL_PERIPH1_400M 18 +#define CLK_PLL_PERIPH1_300M 19 +#define CLK_PLL_PERIPH1_200M 20 +#define CLK_PLL_PERIPH1_160M 21 +#define CLK_PLL_PERIPH1_150M 22 +#define CLK_PLL_GPU 23 +#define CLK_PLL_VIDEO0_8X 24 +#define CLK_PLL_VIDEO0_4X 25 +#define CLK_PLL_VIDEO0_3X 26 +#define CLK_PLL_VIDEO1_8X 27 +#define CLK_PLL_VIDEO1_4X 28 +#define CLK_PLL_VIDEO1_3X 29 +#define CLK_PLL_VIDEO2_8X 30 +#define CLK_PLL_VIDEO2_4X 31 +#define CLK_PLL_VIDEO2_3X 32 +#define CLK_PLL_VE0 33 +#define CLK_PLL_VE1 34 +#define CLK_PLL_AUDIO0_4X 35 +#define CLK_PLL_AUDIO1 36 +#define CLK_PLL_AUDIO1_DIV2 37 +#define CLK_PLL_AUDIO1_DIV5 38 +#define CLK_PLL_NPU 39 +#define CLK_PLL_DE 40 +#define CLK_PLL_DE_4X 41 +#define CLK_PLL_DE_3X 42 +#define CLK_AHB 43 +#define CLK_APB0 44 +#define CLK_APB1 45 +#define CLK_APB_UART 46 +#define CLK_TRACE 47 +#define CLK_GIC 48 +#define CLK_CPU_PERI 49 +#define CLK_BUS_ITS_PCIE 50 +#define CLK_NSI 51 +#define CLK_BUS_NSI 52 +#define CLK_MBUS 53 +#define CLK_MBUS_IOMMU0_SYS 54 +#define CLK_APB_IOMMU0_SYS 55 +#define CLK_AHB_IOMMU0_SYS 56 +#define CLK_BUS_MSI_LITE0 57 +#define CLK_BUS_MSI_LITE1 58 +#define CLK_BUS_MSI_LITE2 59 +#define CLK_MBUS_IOMMU1_SYS 60 +#define CLK_APB_IOMMU1_SYS 61 +#define CLK_AHB_IOMMU1_SYS 62 +#define CLK_AHB_VE_DEC 63 +#define CLK_AHB_VE_ENC 64 +#define CLK_AHB_VID_IN 65 +#define CLK_AHB_VID_COUT0 66 +#define CLK_AHB_VID_COUT1 67 +#define CLK_AHB_DE 68 +#define CLK_AHB_NPU 69 +#define CLK_AHB_GPU0 70 +#define CLK_AHB_SERDES 71 +#define CLK_AHB_USB_SYS 72 +#define CLK_AHB_MSI_LITE0 73 +#define CLK_AHB_STORE 74 +#define CLK_AHB_CPUS 75 +#define CLK_MBUS_IOMMU0 76 +#define CLK_MBUS_IOMMU1 77 +#define CLK_MBUS_DESYS 78 +#define CLK_MBUS_VE_ENC_GATE 79 +#define CLK_MBUS_VE_DEC_GATE 80 +#define CLK_MBUS_GPU0 81 +#define CLK_MBUS_NPU 82 +#define CLK_MBUS_VID_IN 83 +#define CLK_MBUS_SERDES 84 +#define CLK_MBUS_MSI_LITE0 85 +#define CLK_MBUS_STORE 86 +#define CLK_MBUS_MSI_LITE2 87 +#define CLK_MBUS_DMA0 88 +#define CLK_MBUS_VE_ENC 89 +#define CLK_MBUS_CE 90 +#define CLK_MBUS_DMA1 91 +#define CLK_MBUS_NAND 92 +#define CLK_MBUS_CSI 93 +#define CLK_MBUS_ISP 94 +#define CLK_MBUS_GMAC0 95 +#define CLK_MBUS_GMAC1 96 +#define CLK_MBUS_VE_DEC 97 +#define CLK_BUS_DMA0 98 +#define CLK_BUS_DMA1 99 +#define CLK_BUS_SPINLOCK 100 +#define CLK_BUS_MSGBOX 101 +#define CLK_BUS_PWM0 102 +#define CLK_BUS_PWM1 103 +#define CLK_BUS_DBG 104 +#define CLK_BUS_SYSDAP 105 +#define CLK_TIMER0 106 +#define CLK_TIMER1 107 +#define CLK_TIMER2 108 +#define CLK_TIMER3 109 +#define CLK_TIMER4 110 +#define CLK_TIMER5 111 +#define CLK_TIMER6 112 +#define CLK_TIMER7 113 +#define CLK_TIMER8 114 +#define CLK_TIMER9 115 +#define CLK_BUS_TIMER 116 +#define CLK_AVS 117 +#define CLK_DE 118 +#define CLK_BUS_DE 119 +#define CLK_DI 120 +#define CLK_BUS_DI 121 +#define CLK_G2D 122 +#define CLK_BUS_G2D 123 +#define CLK_EINK 124 +#define CLK_EINK_PANEL 125 +#define CLK_BUS_EINK 126 +#define CLK_VE_ENC 127 +#define CLK_VE_DEC 128 +#define CLK_BUS_VE_ENC 129 +#define CLK_BUS_VE_DEC 130 +#define CLK_CE 131 +#define CLK_BUS_CE 132 +#define CLK_BUS_CE_SYS 133 +#define CLK_NPU 134 +#define CLK_BUS_NPU 135 +#define CLK_GPU 136 +#define CLK_BUS_GPU 137 +#define CLK_DRAM 138 +#define CLK_BUS_DRAM 139 +#define CLK_NAND0 140 +#define CLK_NAND1 141 +#define CLK_BUS_NAND 142 +#define CLK_MMC0 143 +#define CLK_MMC1 144 +#define CLK_MMC2 145 +#define CLK_MMC3 146 +#define CLK_BUS_MMC0 147 +#define CLK_BUS_MMC1 148 +#define CLK_BUS_MMC2 149 +#define CLK_BUS_MMC3 150 +#define CLK_UFS_AXI 151 +#define CLK_UFS_CFG 152 +#define CLK_BUS_UFS 153 +#define CLK_BUS_UART0 154 +#define CLK_BUS_UART1 155 +#define CLK_BUS_UART2 156 +#define CLK_BUS_UART3 157 +#define CLK_BUS_UART4 158 +#define CLK_BUS_UART5 159 +#define CLK_BUS_UART6 160 +#define CLK_BUS_I2C0 161 +#define CLK_BUS_I2C1 162 +#define CLK_BUS_I2C2 163 +#define CLK_BUS_I2C3 164 +#define CLK_BUS_I2C4 165 +#define CLK_BUS_I2C5 166 +#define CLK_BUS_I2C6 167 +#define CLK_BUS_I2C7 168 +#define CLK_BUS_I2C8 169 +#define CLK_BUS_I2C9 170 +#define CLK_BUS_I2C10 171 +#define CLK_BUS_I2C11 172 +#define CLK_BUS_I2C12 173 +#define CLK_SPI0 174 +#define CLK_SPI1 175 +#define CLK_SPI2 176 +#define CLK_SPI3 177 +#define CLK_SPI4 178 +#define CLK_BUS_SPI0 179 +#define CLK_BUS_SPI1 180 +#define CLK_BUS_SPI2 181 +#define CLK_BUS_SPI3 182 +#define CLK_BUS_SPI4 183 +#define CLK_SPIF 184 +#define CLK_BUS_SPIF 185 +#define CLK_GPADC 186 +#define CLK_BUS_GPADC 187 +#define CLK_BUS_THS 188 +#define CLK_IRRX 189 +#define CLK_BUS_IRRX 190 +#define CLK_IRTX 191 +#define CLK_BUS_IRTX 192 +#define CLK_BUS_LRADC 193 +#define CLK_SGPIO 194 +#define CLK_BUS_SGPIO 195 +#define CLK_LPC 196 +#define CLK_BUS_LPC 197 +#define CLK_I2SPCM0 198 +#define CLK_I2SPCM1 199 +#define CLK_I2SPCM2 200 +#define CLK_I2SPCM3 201 +#define CLK_I2SPCM4 202 +#define CLK_BUS_I2SPCM0 203 +#define CLK_BUS_I2SPCM1 204 +#define CLK_BUS_I2SPCM2 205 +#define CLK_BUS_I2SPCM3 206 +#define CLK_BUS_I2SPCM4 207 +#define CLK_I2SPCM2_ASRC 208 +#define CLK_OWA_TX 209 +#define CLK_OWA_RX 210 +#define CLK_BUS_OWA 211 +#define CLK_DMIC 212 +#define CLK_BUS_DMIC 213 +#define CLK_USB_OHCI0 214 +#define CLK_BUS_OTG 215 +#define CLK_BUS_EHCI0 216 +#define CLK_BUS_OHCI0 217 +#define CLK_USB_OHCI1 218 +#define CLK_BUS_EHCI1 219 +#define CLK_BUS_OHCI1 220 +#define CLK_USB_REF 221 +#define CLK_USB2_U2_REF 222 +#define CLK_USB2_SUSPEND 223 +#define CLK_USB2_MF 224 +#define CLK_USB2_U3_UTMI 225 +#define CLK_USB2_U2_PIPE 226 +#define CLK_PCIE_AUX 227 +#define CLK_PCIE_AXI_SLV 228 +#define CLK_SERDES_PHY 229 +#define CLK_GMAC_PTP 230 +#define CLK_GMAC0_PHY 231 +#define CLK_GMAC1_PHY 232 +#define CLK_BUS_GMAC0 233 +#define CLK_BUS_GMAC1 234 +#define CLK_TCON_LCD0 235 +#define CLK_TCON_LCD1 236 +#define CLK_TCON_LCD2 237 +#define CLK_BUS_TCON_LCD0 238 +#define CLK_BUS_TCON_LCD1 239 +#define CLK_BUS_TCON_LCD2 240 +#define CLK_DSI0 241 +#define CLK_DSI1 242 +#define CLK_BUS_DSI0 243 +#define CLK_BUS_DSI1 244 +#define CLK_COMBPHY0 245 +#define CLK_COMBPHY1 246 +#define CLK_BUS_TCON_TV0 247 +#define CLK_BUS_TCON_TV1 248 +#define CLK_EDP_TV 249 +#define CLK_BUS_EDP_TV 250 +#define CLK_HDMI_CEC_32K 251 +#define CLK_HDMI_CEC 252 +#define CLK_HDMI_TV 253 +#define CLK_BUS_HDMI_TV 254 +#define CLK_HDMI_SFR 255 +#define CLK_HDMI_ESM 256 +#define CLK_BUS_DPSS_TOP0 257 +#define CLK_BUS_DPSS_TOP1 258 +#define CLK_LEDC 259 +#define CLK_BUS_LEDC 260 +#define CLK_BUS_DSC 261 +#define CLK_CSI_MASTER0 262 +#define CLK_CSI_MASTER1 263 +#define CLK_CSI_MASTER2 264 +#define CLK_CSI 265 +#define CLK_BUS_CSI 266 +#define CLK_ISP 267 +#define CLK_APB2JTAG 268 +#define CLK_FANOUT_24M 269 +#define CLK_FANOUT_12M 270 +#define CLK_FANOUT_16M 271 +#define CLK_FANOUT_25M 272 +#define CLK_FANOUT_27M 273 +#define CLK_FANOUT_PCLK 274 +#define CLK_FANOUT0 275 +#define CLK_FANOUT1 276 +#define CLK_FANOUT2 277 +#define CLK_FANOUT3 278 + +#endif /* _DT_BINDINGS_CLK_SUN60I_A733_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun60i-a733-r-ccu.h b/include/dt-bin= dings/clock/sun60i-a733-r-ccu.h new file mode 100644 index 000000000000..1c717cc588b8 --- /dev/null +++ b/include/dt-bindings/clock/sun60i-a733-r-ccu.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2026 Junhui Liu + */ + +#ifndef _DT_BINDINGS_CLK_SUN60I_A733_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN60I_A733_R_CCU_H_ + +#define CLK_R_AHB 0 +#define CLK_R_APB0 1 +#define CLK_R_APB1 2 +#define CLK_R_TIMER0 3 +#define CLK_R_TIMER1 4 +#define CLK_R_TIMER2 5 +#define CLK_R_TIMER3 6 +#define CLK_BUS_R_TIMER 7 +#define CLK_BUS_R_TWD 8 +#define CLK_R_PWMCTRL 9 +#define CLK_BUS_R_PWMCTRL 10 +#define CLK_R_SPI 11 +#define CLK_BUS_R_SPI 12 +#define CLK_BUS_R_MSGBOX 13 +#define CLK_BUS_R_UART0 14 +#define CLK_BUS_R_UART1 15 +#define CLK_BUS_R_I2C0 16 +#define CLK_BUS_R_I2C1 17 +#define CLK_BUS_R_I2C2 18 +#define CLK_BUS_R_PPU 19 +#define CLK_BUS_R_TZMA 20 +#define CLK_BUS_R_CPU_BIST 21 +#define CLK_R_IR_RX 22 +#define CLK_BUS_R_IR_RX 23 +#define CLK_BUS_R_RTC 24 +#define CLK_R_RISCV 25 +#define CLK_BUS_R_RISCV 26 +#define CLK_BUS_R_RISCV_CFG 27 +#define CLK_BUS_R_CPUCFG 28 + +#endif /* _DT_BINDINGS_CLK_SUN60I_A733_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun60i-a733-ccu.h b/include/dt-bindi= ngs/reset/sun60i-a733-ccu.h new file mode 100644 index 000000000000..11ce78cf04dd --- /dev/null +++ b/include/dt-bindings/reset/sun60i-a733-ccu.h @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2026 Junhui Liu + */ + +#ifndef _DT_BINDINGS_RST_SUN60I_A733_CCU_H_ +#define _DT_BINDINGS_RST_SUN60I_A733_CCU_H_ + +#define RST_BUS_ITS_PCIE 0 +#define RST_BUS_NSI 1 +#define RST_BUS_NSI_CFG 2 +#define RST_BUS_IOMMU0_SYS 3 +#define RST_BUS_MSI_LITE0_AHB 4 +#define RST_BUS_MSI_LITE0_MBUS 5 +#define RST_BUS_MSI_LITE1_AHB 6 +#define RST_BUS_MSI_LITE1_MBUS 7 +#define RST_BUS_MSI_LITE2_AHB 8 +#define RST_BUS_MSI_LITE2_MBUS 9 +#define RST_BUS_IOMMU1_SYS 10 +#define RST_BUS_DMA0 11 +#define RST_BUS_DMA1 12 +#define RST_BUS_SPINLOCK 13 +#define RST_BUS_MSGBOX 14 +#define RST_BUS_PWM0 15 +#define RST_BUS_PWM1 16 +#define RST_BUS_DBG 17 +#define RST_BUS_SYSDAP 18 +#define RST_BUS_TIMER0 19 +#define RST_BUS_DE 20 +#define RST_BUS_DI 21 +#define RST_BUS_G2D 22 +#define RST_BUS_EINK 23 +#define RST_BUS_DE_SYS 24 +#define RST_BUS_VE_ENC 25 +#define RST_BUS_VE_DEC 26 +#define RST_BUS_CE 27 +#define RST_BUS_CE_SYS 28 +#define RST_BUS_NPU_CORE 29 +#define RST_BUS_NPU_AXI 30 +#define RST_BUS_NPU_AHB 31 +#define RST_BUS_NPU_SRAM 32 +#define RST_BUS_GPU 33 +#define RST_BUS_DRAM 34 +#define RST_BUS_NAND 35 +#define RST_BUS_MMC0 36 +#define RST_BUS_MMC1 37 +#define RST_BUS_MMC2 38 +#define RST_BUS_MMC3 39 +#define RST_BUS_UFS_AHB 40 +#define RST_BUS_UFS_AXI 41 +#define RST_BUS_UFS_PHY 42 +#define RST_BUS_UFS_CORE 43 +#define RST_BUS_UART0 44 +#define RST_BUS_UART1 45 +#define RST_BUS_UART2 46 +#define RST_BUS_UART3 47 +#define RST_BUS_UART4 48 +#define RST_BUS_UART5 49 +#define RST_BUS_UART6 50 +#define RST_BUS_I2C0 51 +#define RST_BUS_I2C1 52 +#define RST_BUS_I2C2 53 +#define RST_BUS_I2C3 54 +#define RST_BUS_I2C4 55 +#define RST_BUS_I2C5 56 +#define RST_BUS_I2C6 57 +#define RST_BUS_I2C7 58 +#define RST_BUS_I2C8 59 +#define RST_BUS_I2C9 60 +#define RST_BUS_I2C10 61 +#define RST_BUS_I2C11 62 +#define RST_BUS_I2C12 63 +#define RST_BUS_SPI0 64 +#define RST_BUS_SPI1 65 +#define RST_BUS_SPI2 66 +#define RST_BUS_SPIF 67 +#define RST_BUS_SPI3 68 +#define RST_BUS_SPI4 69 +#define RST_BUS_GPADC 70 +#define RST_BUS_THS 71 +#define RST_BUS_IRRX 72 +#define RST_BUS_IRTX 73 +#define RST_BUS_LRADC 74 +#define RST_BUS_SGPIO 75 +#define RST_BUS_LPC 76 +#define RST_BUS_I2SPCM0 77 +#define RST_BUS_I2SPCM1 78 +#define RST_BUS_I2SPCM2 79 +#define RST_BUS_I2SPCM3 80 +#define RST_BUS_I2SPCM4 81 +#define RST_BUS_OWA 82 +#define RST_BUS_DMIC 83 +#define RST_USB_PHY0 84 +#define RST_BUS_OHCI0 85 +#define RST_BUS_EHCI0 86 +#define RST_BUS_OTG 87 +#define RST_USB_PHY1 88 +#define RST_BUS_OHCI1 89 +#define RST_BUS_EHCI1 90 +#define RST_BUS_USB2 91 +#define RST_BUS_PCIE 92 +#define RST_BUS_PCIE_PWRUP 93 +#define RST_BUS_SERDES 94 +#define RST_BUS_GMAC0 95 +#define RST_BUS_GMAC0_AXI 96 +#define RST_BUS_GMAC1 97 +#define RST_BUS_GMAC1_AXI 98 +#define RST_BUS_TCON_LCD0 99 +#define RST_BUS_TCON_LCD1 100 +#define RST_BUS_TCON_LCD2 101 +#define RST_BUS_LVDS0 102 +#define RST_BUS_LVDS1 103 +#define RST_BUS_DSI0 104 +#define RST_BUS_DSI1 105 +#define RST_BUS_TCON_TV0 106 +#define RST_BUS_TCON_TV1 107 +#define RST_BUS_EDP 108 +#define RST_BUS_HDMI_MAIN 109 +#define RST_BUS_HDMI_SUB 110 +#define RST_BUS_HDMI_HDCP 111 +#define RST_BUS_DPSS_TOP0 112 +#define RST_BUS_DPSS_TOP1 113 +#define RST_BUS_VIDEO_OUT0 114 +#define RST_BUS_VIDEO_OUT1 115 +#define RST_BUS_LEDC 116 +#define RST_BUS_DSC 117 +#define RST_BUS_CSI 118 +#define RST_BUS_VIDEO_IN 119 +#define RST_BUS_APB2JTAG 120 + +#endif /* _DT_BINDINGS_RST_SUN60I_A733_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun60i-a733-r-ccu.h b/include/dt-bin= dings/reset/sun60i-a733-r-ccu.h new file mode 100644 index 000000000000..629e546d1998 --- /dev/null +++ b/include/dt-bindings/reset/sun60i-a733-r-ccu.h @@ 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16:33:55 +0800 Subject: [PATCH RFC 2/8] clk: sunxi-ng: sdm: Add dual patterns support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260310-a733-clk-v1-2-36b4e9b24457@pigmoral.tech> References: <20260310-a733-clk-v1-0-36b4e9b24457@pigmoral.tech> In-Reply-To: <20260310-a733-clk-v1-0-36b4e9b24457@pigmoral.tech> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773132092; l=6019; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=zzT6qLQz5v4GiQuUfSzl8hxhZinQmgUWrgxWzt3zb5Q=; b=ZAnmzntcBAIdnAQKtbrdA8sDq/2rLHFpsYPmLJTOgrJB1M/V6J1i1kWkQzYMq1xPoAaaqHTlQ QP5RxipryO4BeHFuhmHPzZcwevhMB6hxGqqJ29WjTsY5ECJICHy1DTf X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External On newer Allwinner platforms like the A733, the Sigma-Delta Modulation (SDM) control logic is more complex. The SDM enable bit, which was previously located in the PLL register, is now moved to a second pattern register (PATTERN1). To support this, rename the existing "tuning" members to "pattern0" to align with the datasheet, and introduce the _SUNXI_CCU_SDM_DUAL_PAT macro to provide pattern1 register support. Related operations are also updated. Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/ccu_sdm.c | 51 +++++++++++++++++++++++++++++---------= ---- drivers/clk/sunxi-ng/ccu_sdm.h | 32 +++++++++++++++++--------- 2 files changed, 57 insertions(+), 26 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu_sdm.c b/drivers/clk/sunxi-ng/ccu_sdm.c index c564e5f9e610..204e25feaa36 100644 --- a/drivers/clk/sunxi-ng/ccu_sdm.c +++ b/drivers/clk/sunxi-ng/ccu_sdm.c @@ -18,7 +18,10 @@ bool ccu_sdm_helper_is_enabled(struct ccu_common *common, if (sdm->enable && !(readl(common->base + common->reg) & sdm->enable)) return false; =20 - return !!(readl(common->base + sdm->tuning_reg) & sdm->tuning_enable); + if (sdm->pat1_enable && !(readl(common->base + sdm->pat1_reg) & sdm->pat1= _enable)) + return false; + + return !!(readl(common->base + sdm->pat0_reg) & sdm->pat0_enable); } EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_is_enabled, "SUNXI_CCU"); =20 @@ -37,18 +40,27 @@ void ccu_sdm_helper_enable(struct ccu_common *common, for (i =3D 0; i < sdm->table_size; i++) if (sdm->table[i].rate =3D=3D rate) writel(sdm->table[i].pattern, - common->base + sdm->tuning_reg); + common->base + sdm->pat0_reg); =20 /* Make sure SDM is enabled */ spin_lock_irqsave(common->lock, flags); - reg =3D readl(common->base + sdm->tuning_reg); - writel(reg | sdm->tuning_enable, common->base + sdm->tuning_reg); + reg =3D readl(common->base + sdm->pat0_reg); + writel(reg | sdm->pat0_enable, common->base + sdm->pat0_reg); spin_unlock_irqrestore(common->lock, flags); =20 - spin_lock_irqsave(common->lock, flags); - reg =3D readl(common->base + common->reg); - writel(reg | sdm->enable, common->base + common->reg); - spin_unlock_irqrestore(common->lock, flags); + if (sdm->enable) { + spin_lock_irqsave(common->lock, flags); + reg =3D readl(common->base + common->reg); + writel(reg | sdm->enable, common->base + common->reg); + spin_unlock_irqrestore(common->lock, flags); + } + + if (sdm->pat1_enable) { + spin_lock_irqsave(common->lock, flags); + reg =3D readl(common->base + sdm->pat1_reg); + writel(reg | sdm->pat1_enable, common->base + sdm->pat1_reg); + spin_unlock_irqrestore(common->lock, flags); + } } EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_enable, "SUNXI_CCU"); =20 @@ -61,14 +73,23 @@ void ccu_sdm_helper_disable(struct ccu_common *common, if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD)) return; =20 - spin_lock_irqsave(common->lock, flags); - reg =3D readl(common->base + common->reg); - writel(reg & ~sdm->enable, common->base + common->reg); - spin_unlock_irqrestore(common->lock, flags); + if (sdm->enable) { + spin_lock_irqsave(common->lock, flags); + reg =3D readl(common->base + common->reg); + writel(reg & ~sdm->enable, common->base + common->reg); + spin_unlock_irqrestore(common->lock, flags); + } + + if (sdm->pat1_enable) { + spin_lock_irqsave(common->lock, flags); + reg =3D readl(common->base + sdm->pat1_reg); + writel(reg & ~sdm->pat1_enable, common->base + sdm->pat1_reg); + spin_unlock_irqrestore(common->lock, flags); + } =20 spin_lock_irqsave(common->lock, flags); - reg =3D readl(common->base + sdm->tuning_reg); - writel(reg & ~sdm->tuning_enable, common->base + sdm->tuning_reg); + reg =3D readl(common->base + sdm->pat0_reg); + writel(reg & ~sdm->pat0_enable, common->base + sdm->pat0_reg); spin_unlock_irqrestore(common->lock, flags); } EXPORT_SYMBOL_NS_GPL(ccu_sdm_helper_disable, "SUNXI_CCU"); @@ -123,7 +144,7 @@ unsigned long ccu_sdm_helper_read_rate(struct ccu_commo= n *common, pr_debug("%s: clock is sigma-delta modulated\n", clk_hw_get_name(&common->hw)); =20 - reg =3D readl(common->base + sdm->tuning_reg); + reg =3D readl(common->base + sdm->pat0_reg); =20 pr_debug("%s: pattern reg is 0x%x", clk_hw_get_name(&common->hw), reg); diff --git a/drivers/clk/sunxi-ng/ccu_sdm.h b/drivers/clk/sunxi-ng/ccu_sdm.h index c1a7159b89c3..c289be28e1b4 100644 --- a/drivers/clk/sunxi-ng/ccu_sdm.h +++ b/drivers/clk/sunxi-ng/ccu_sdm.h @@ -33,21 +33,31 @@ struct ccu_sdm_internal { u32 table_size; /* early SoCs don't have the SDM enable bit in the PLL register */ u32 enable; - /* second enable bit in tuning register */ - u32 tuning_enable; - u16 tuning_reg; + /* second enable bit in pattern0 register */ + u32 pat0_enable; + u16 pat0_reg; + /* on some platforms, the sdm enable bit in pattern1 register */ + u32 pat1_enable; + u16 pat1_reg; }; =20 -#define _SUNXI_CCU_SDM(_table, _enable, \ - _reg, _reg_enable) \ - { \ - .table =3D _table, \ - .table_size =3D ARRAY_SIZE(_table), \ - .enable =3D _enable, \ - .tuning_enable =3D _reg_enable, \ - .tuning_reg =3D _reg, \ +#define __SUNXI_CCU_SDM(_table, _enable, _pat0, _pat0_enable, _pat1, _pat1= _enable) \ + { \ + .table =3D _table, \ + .table_size =3D ARRAY_SIZE(_table), \ + .enable =3D _enable, \ + .pat0_enable =3D _pat0_enable, \ + .pat0_reg =3D _pat0, \ + .pat1_enable =3D _pat1_enable, \ + .pat1_reg =3D _pat1, \ } =20 +#define _SUNXI_CCU_SDM(_table, _enable, _pat0, _pat0_enable) \ + __SUNXI_CCU_SDM(_table, _enable, _pat0, _pat0_enable, 0, 0) + +#define _SUNXI_CCU_SDM_DUAL_PAT(_table, _pat0, _pat0_enable, _pat1, _pat1_= enable) \ + __SUNXI_CCU_SDM(_table, 0, _pat0, _pat0_enable, _pat1, _pat1_enable) + bool ccu_sdm_helper_is_enabled(struct ccu_common *common, struct ccu_sdm_internal *sdm); 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Tue, 10 Mar 2026 01:42:11 -0700 (PDT) From: Junhui Liu Date: Tue, 10 Mar 2026 16:33:56 +0800 Subject: [PATCH RFC 3/8] clk: sunxi-ng: a733: Add PRCM CCU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260310-a733-clk-v1-3-36b4e9b24457@pigmoral.tech> References: <20260310-a733-clk-v1-0-36b4e9b24457@pigmoral.tech> In-Reply-To: <20260310-a733-clk-v1-0-36b4e9b24457@pigmoral.tech> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773132092; l=12305; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=i6GPRxBukKlemF/25P9vZMqH46GM2kRueFPk0VKiS8c=; b=VDag9ZsHfEtyRbtHBdu/kr1fWH1tgKXP135UxKIcw8GAQTW+0AXuZl2ELXvYivu9Qd2UXbYYS m15R6bR63dRBrThPW64dtKsouZf/m9OiTNa/qhP9p3voAhhvAtMcmgN X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External Add support for the Power Reset Clock Management (PRCM) module found in the Allwinner A733 SoC. This clock controller manages the clock control and reset functions for device modules within the CPUS domain. The PRCM module includes the management of three primary buses: r-ahb, r-apb0, and r-apb1. It also provides clocking for several key peripherals, such as R-UART, R-I2C, R-SPI, and the R-RISCV subsystem. Additionally, the reset lines for these modules are integrated. Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/sunxi-ng/Makefile | 2 + drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c | 276 +++++++++++++++++++++++++++= ++++ 3 files changed, 283 insertions(+) diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 6af2d020e03e..202e793dc754 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -67,6 +67,11 @@ config SUN55I_A523_R_CCU default ARCH_SUNXI depends on ARM64 || COMPILE_TEST =20 +config SUN60I_A733_R_CCU + tristate "Support for the Allwinner A733 PRCM CCU" + default ARCH_SUNXI + depends on ARM64 || COMPILE_TEST + config SUN4I_A10_CCU tristate "Support for the Allwinner A10/A20 CCU" default ARCH_SUNXI diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index a1c4087d7241..d3702bdb7a23 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_SUN50I_H616_CCU) +=3D sun50i-h616-ccu.o obj-$(CONFIG_SUN55I_A523_CCU) +=3D sun55i-a523-ccu.o obj-$(CONFIG_SUN55I_A523_MCU_CCU) +=3D sun55i-a523-mcu-ccu.o obj-$(CONFIG_SUN55I_A523_R_CCU) +=3D sun55i-a523-r-ccu.o +obj-$(CONFIG_SUN60I_A733_R_CCU) +=3D sun60i-a733-r-ccu.o obj-$(CONFIG_SUN4I_A10_CCU) +=3D sun4i-a10-ccu.o obj-$(CONFIG_SUN5I_CCU) +=3D sun5i-ccu.o obj-$(CONFIG_SUN6I_A31_CCU) +=3D sun6i-a31-ccu.o @@ -64,6 +65,7 @@ sun50i-h616-ccu-y +=3D ccu-sun50i-h616.o sun55i-a523-ccu-y +=3D ccu-sun55i-a523.o sun55i-a523-mcu-ccu-y +=3D ccu-sun55i-a523-mcu.o sun55i-a523-r-ccu-y +=3D ccu-sun55i-a523-r.o +sun60i-a733-r-ccu-y +=3D ccu-sun60i-a733-r.o sun4i-a10-ccu-y +=3D ccu-sun4i-a10.o sun5i-ccu-y +=3D ccu-sun5i.o sun6i-a31-ccu-y +=3D ccu-sun6i-a31.o diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c b/drivers/clk/sunxi-n= g/ccu-sun60i-a733-r.c new file mode 100644 index 000000000000..06679be1eaae --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 rengaomin@allwinnertech.com + * Copyright (C) 2026 Junhui Liu + * Based on the A523 CCU driver: + * Copyright (C) 2024 Arm Ltd. + */ + +#include +#include +#include + +#include +#include + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_gate.h" +#include "ccu_mp.h" + +static const struct clk_parent_data r_ahb_parents[] =3D { + { .fw_name =3D "hosc" }, + { .fw_name =3D "losc" }, + { .fw_name =3D "iosc" }, + { .fw_name =3D "pll-periph0-200m" }, + { .fw_name =3D "pll-periph0-300m" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX(r_ahb_clk, "r-ahb", r_ahb_parents, 0x000, + 0, 5, /* M */ + 24, 3, /* mux */ + 0); + +static const struct clk_parent_data r_apb_parents[] =3D { + { .fw_name =3D "hosc" }, + { .fw_name =3D "losc" }, + { .fw_name =3D "iosc" }, + { .fw_name =3D "pll-periph0-200m" }, + { .fw_name =3D "sys-24m" }, +}; + +static SUNXI_CCU_M_DATA_WITH_MUX(r_apb0_clk, "r-apb0", r_apb_parents, 0x00= c, + 0, 5, /* M */ + 24, 3, /* mux */ + 0); + +static SUNXI_CCU_M_DATA_WITH_MUX(r_apb1_clk, "r-apb1", r_apb_parents, 0x01= 0, + 0, 5, /* M */ + 24, 3, /* mux */ + 0); + +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer0, "r-timer0", r_apb_par= ents, 0x100, + 0, 0, /* no M */ + 1, 3, /* P */ + 4, 3, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer1, "r-timer1", r_apb_par= ents, 0x104, + 0, 0, /* no M */ + 1, 3, /* P */ + 4, 3, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer2, "r-timer2", r_apb_par= ents, 0x108, + 0, 0, /* no M */ + 1, 3, /* P */ + 4, 3, /* mux */ + BIT(0), /* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer3, "r-timer3", r_apb_par= ents, 0x10c, + 0, 0, /* no M */ + 1, 3, /* P */ + 4, 3, /* mux */ + BIT(0), /* gate */ + 0); + +static SUNXI_CCU_GATE_HW(bus_r_timer_clk, "bus-r-timer", &r_ahb_clk.common= .hw, 0x11c, BIT(0), 0); +static SUNXI_CCU_GATE_HW(bus_r_twd_clk, "bus-r-twd", &r_apb0_clk.common.hw= , 0x12c, BIT(0), 0); + +static const struct clk_parent_data r_pwmctrl_parents[] =3D { + { .fw_name =3D "hosc" }, + { .fw_name =3D "losc" }, + { .fw_name =3D "iosc" }, + { .fw_name =3D "sys-24m" }, +}; +static SUNXI_CCU_MUX_DATA_WITH_GATE(r_pwmctrl_clk, "r-pwmctrl", r_pwmctrl_= parents, 0x130, + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_GATE_HW(bus_r_pwmctrl_clk, "bus-r-pwmctrl", + &r_apb0_clk.common.hw, 0x13c, BIT(0), 0); + +static const struct clk_parent_data r_spi_parents[] =3D { + { .fw_name =3D "hosc" }, + { .fw_name =3D "pll-periph0-200m" }, + { .fw_name =3D "pll-periph0-300m" }, + { .fw_name =3D "pll-periph1-300m" }, + { .fw_name =3D "sys-24m" }, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(r_spi_clk, "r-spi", r_spi_parents, 0x150, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_GATE_HW(bus_r_spi_clk, "bus-r-spi", &r_ahb_clk.common.hw,= 0x15c, BIT(0), 0); + +static SUNXI_CCU_GATE_HW(bus_r_msgbox_clk, "bus-r-msgbox", &r_ahb_clk.comm= on.hw, 0x17c, BIT(0), 0); + +static SUNXI_CCU_GATE_HW(bus_r_uart0_clk, "bus-r-uart0", &r_apb1_clk.commo= n.hw, 0x18c, BIT(0), 0); +static SUNXI_CCU_GATE_HW(bus_r_uart1_clk, "bus-r-uart1", &r_apb1_clk.commo= n.hw, 0x18c, BIT(1), 0); + +static SUNXI_CCU_GATE_HW(bus_r_i2c0_clk, "bus-r-i2c0", &r_apb1_clk.common.= hw, 0x19c, BIT(0), 0); +static SUNXI_CCU_GATE_HW(bus_r_i2c1_clk, "bus-r-i2c1", &r_apb1_clk.common.= hw, 0x19c, BIT(1), 0); +static SUNXI_CCU_GATE_HW(bus_r_i2c2_clk, "bus-r-i2c2", &r_apb1_clk.common.= hw, 0x19c, BIT(2), 0); + +static SUNXI_CCU_GATE_HW(bus_r_ppu_clk, "bus-r-ppu", &r_apb0_clk.common.hw= , 0x1ac, BIT(0), 0); + +static SUNXI_CCU_GATE_HW(bus_r_tzma_clk, "bus-r-tzma", &r_apb0_clk.common.= hw, 0x1b0, BIT(0), 0); +static SUNXI_CCU_GATE_HW(bus_r_cpu_bist_clk, "bus-r-cpu-bist", &r_apb0_clk= .common.hw, + 0x1bc, BIT(0), 0); + +static const struct clk_parent_data r_ir_rx_parents[] =3D { + { .fw_name =3D "losc" }, + { .fw_name =3D "hosc" }, + { .fw_name =3D "sys-24m" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(r_ir_rx_clk, "r-ir-rx", r_ir_rx_pare= nts, 0x1c0, + 0, 5, /* M */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_GATE_HW(bus_r_ir_rx_clk, "bus-r-ir-rx", &r_apb0_clk.commo= n.hw, 0x1cc, BIT(0), 0); + +static SUNXI_CCU_GATE_HW(bus_r_rtc_clk, "bus-r-rtc", &r_ahb_clk.common.hw,= 0x20c, BIT(0), 0); + +static const struct clk_parent_data r_riscv_parents[] =3D { + { .fw_name =3D "hosc" }, + { .fw_name =3D "losc" }, + { .fw_name =3D "iosc" }, +}; +static SUNXI_CCU_MUX_DATA_WITH_GATE(r_riscv_clk, "r-riscv", r_riscv_parent= s, 0x210, + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_GATE_HW(bus_r_riscv_clk, "bus-r-riscv", &r_apb0_clk.commo= n.hw, + 0x21c, BIT(0), 0); +static SUNXI_CCU_GATE_HW(bus_r_riscv_cfg_clk, "bus-r-riscv-cfg", &r_apb0_c= lk.common.hw, + 0x21c, BIT(1), 0); + +static SUNXI_CCU_GATE_HW(bus_r_cpucfg_clk, "bus-r-cpucfg", &r_apb0_clk.com= mon.hw, + 0x22c, BIT(0), CLK_IS_CRITICAL); + +static struct ccu_common *sun60i_a733_r_ccu_clks[] =3D { + &r_ahb_clk.common, + &r_apb0_clk.common, + &r_apb1_clk.common, + &r_cpu_timer0.common, + &r_cpu_timer1.common, + &r_cpu_timer2.common, + &r_cpu_timer3.common, + &bus_r_timer_clk.common, + &bus_r_twd_clk.common, + &r_pwmctrl_clk.common, + &bus_r_pwmctrl_clk.common, + &r_spi_clk.common, + &bus_r_spi_clk.common, + &bus_r_msgbox_clk.common, + &bus_r_uart0_clk.common, + &bus_r_uart1_clk.common, + &bus_r_i2c0_clk.common, + &bus_r_i2c1_clk.common, + &bus_r_i2c2_clk.common, + &bus_r_ppu_clk.common, + &bus_r_tzma_clk.common, + &bus_r_cpu_bist_clk.common, + &r_ir_rx_clk.common, + &bus_r_ir_rx_clk.common, + &bus_r_rtc_clk.common, + &r_riscv_clk.common, + &bus_r_riscv_clk.common, + &bus_r_riscv_cfg_clk.common, + &bus_r_cpucfg_clk.common, +}; + +static struct clk_hw_onecell_data sun60i_a733_r_hw_clks =3D { + .hws =3D { + [CLK_R_AHB] =3D &r_ahb_clk.common.hw, + [CLK_R_APB0] =3D &r_apb0_clk.common.hw, + [CLK_R_APB1] =3D &r_apb1_clk.common.hw, + [CLK_R_TIMER0] =3D &r_cpu_timer0.common.hw, + [CLK_R_TIMER1] =3D &r_cpu_timer1.common.hw, + [CLK_R_TIMER2] =3D &r_cpu_timer2.common.hw, + [CLK_R_TIMER3] =3D &r_cpu_timer3.common.hw, + [CLK_BUS_R_TIMER] =3D &bus_r_timer_clk.common.hw, + [CLK_BUS_R_TWD] =3D &bus_r_twd_clk.common.hw, + [CLK_R_PWMCTRL] =3D &r_pwmctrl_clk.common.hw, + [CLK_BUS_R_PWMCTRL] =3D &bus_r_pwmctrl_clk.common.hw, + [CLK_R_SPI] =3D &r_spi_clk.common.hw, + [CLK_BUS_R_SPI] =3D &bus_r_spi_clk.common.hw, + [CLK_BUS_R_MSGBOX] =3D &bus_r_msgbox_clk.common.hw, + [CLK_BUS_R_UART0] =3D &bus_r_uart0_clk.common.hw, + [CLK_BUS_R_UART1] =3D &bus_r_uart1_clk.common.hw, + [CLK_BUS_R_I2C0] =3D &bus_r_i2c0_clk.common.hw, + [CLK_BUS_R_I2C1] =3D &bus_r_i2c1_clk.common.hw, + [CLK_BUS_R_I2C2] =3D &bus_r_i2c2_clk.common.hw, + [CLK_BUS_R_PPU] =3D &bus_r_ppu_clk.common.hw, + [CLK_BUS_R_TZMA] =3D &bus_r_tzma_clk.common.hw, + [CLK_BUS_R_CPU_BIST] =3D &bus_r_cpu_bist_clk.common.hw, + [CLK_R_IR_RX] =3D &r_ir_rx_clk.common.hw, + [CLK_BUS_R_IR_RX] =3D &bus_r_ir_rx_clk.common.hw, + [CLK_BUS_R_RTC] =3D &bus_r_rtc_clk.common.hw, + [CLK_R_RISCV] =3D &r_riscv_clk.common.hw, + [CLK_BUS_R_RISCV] =3D &bus_r_riscv_clk.common.hw, + [CLK_BUS_R_RISCV_CFG] =3D &bus_r_riscv_cfg_clk.common.hw, + [CLK_BUS_R_CPUCFG] =3D &bus_r_cpucfg_clk.common.hw, + }, + .num =3D CLK_BUS_R_CPUCFG + 1, +}; + +static struct ccu_reset_map sun60i_a733_r_ccu_resets[] =3D { + [RST_BUS_R_TIMER] =3D { 0x11c, BIT(16) }, + [RST_BUS_R_PWM] =3D { 0x13c, BIT(16) }, + [RST_BUS_R_SPI] =3D { 0x15c, BIT(16) }, + [RST_BUS_R_MSGBOX] =3D { 0x17c, BIT(16) }, + [RST_BUS_R_UART0] =3D { 0x18c, BIT(16) }, + [RST_BUS_R_UART1] =3D { 0x18c, BIT(17) }, + [RST_BUS_R_I2C0] =3D { 0x19c, BIT(16) }, + [RST_BUS_R_I2C1] =3D { 0x19c, BIT(17) }, + [RST_BUS_R_I2C2] =3D { 0x19c, BIT(18) }, + [RST_BUS_R_IR_RX] =3D { 0x1cc, BIT(16) }, + [RST_BUS_R_RTC] =3D { 0x20c, BIT(16) }, + [RST_BUS_R_RISCV_CFG] =3D { 0x21c, BIT(16) }, + [RST_BUS_R_CPUCFG] =3D { 0x22c, BIT(16) }, +}; + +static const struct sunxi_ccu_desc sun60i_a733_r_ccu_desc =3D { + .ccu_clks =3D sun60i_a733_r_ccu_clks, + .num_ccu_clks =3D ARRAY_SIZE(sun60i_a733_r_ccu_clks), + + .hw_clks =3D &sun60i_a733_r_hw_clks, + + .resets =3D sun60i_a733_r_ccu_resets, + .num_resets =3D ARRAY_SIZE(sun60i_a733_r_ccu_resets), +}; + +static int sun60i_a733_r_ccu_probe(struct platform_device *pdev) +{ + void __iomem *reg; + + reg =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(reg)) + return PTR_ERR(reg); + + return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun60i_a733_r_ccu_desc); +} + +static const struct of_device_id sun60i_a733_r_ccu_ids[] =3D { + { .compatible =3D "allwinner,sun60i-a733-r-ccu" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, sun60i_a733_r_ccu_ids); + +static struct platform_driver sun60i_a733_r_ccu_driver =3D { + .probe =3D sun60i_a733_r_ccu_probe, + .driver =3D { + .name =3D "sun60i-a733-r-ccu", + .suppress_bind_attrs =3D true, + .of_match_table =3D sun60i_a733_r_ccu_ids, + }, +}; +module_platform_driver(sun60i_a733_r_ccu_driver); + +MODULE_IMPORT_NS("SUNXI_CCU"); +MODULE_DESCRIPTION("Support for the Allwinner A733 PRCM CCU"); +MODULE_LICENSE("GPL"); --=20 2.52.0 From nobody Sat Apr 11 10:32:53 2026 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2D2A42EEC7; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260310-a733-clk-v1-4-36b4e9b24457@pigmoral.tech> References: <20260310-a733-clk-v1-0-36b4e9b24457@pigmoral.tech> In-Reply-To: <20260310-a733-clk-v1-0-36b4e9b24457@pigmoral.tech> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773132092; l=21536; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=M0KAonTmbGPysXsS5EwjIyqlzYOD3loSPaLLHsVEOUI=; b=bpfuVHa0NuLiMcmYEIwS+rZSZwUSAgT1RFRvRQZi1uMkUHO2G2fM2Q2CqoDFlLZcsbpBzAlGP kdRp9mkHIrCAqtyIN28r/8cE/SErihATzdlCo04atl8OrgOxfBS8SdC X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External Add PLL clock support for the main CCU of the Allwinner A733 SoC. The structure is mostly similar to the sun55i, with the addition of a PLL_REF clock that normalizes the hardware-detected DCXO/hosc frequency (19.2MHz, 24MHz, or 26MHz) into a consistent 24MHz reference for all subsequent PLLs. The behaviors of PLL_AUDIO0 and PLL_AUDIO1 are ported from the vendor driver. Specifically, PLL_AUDIO0 is configured with SDM parameters to provide a 22.5792MHz * 4 output, while PLL_AUDIO1 is integrated into the main CCU without using SDM. Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/sunxi-ng/Makefile | 2 + drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 535 +++++++++++++++++++++++++++++= ++++ 3 files changed, 542 insertions(+) diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 202e793dc754..cffa83056934 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -67,6 +67,11 @@ config SUN55I_A523_R_CCU default ARCH_SUNXI depends on ARM64 || COMPILE_TEST =20 +config SUN60I_A733_CCU + tristate "Support for the Allwinner A733 CCU" + default ARCH_SUNXI + depends on ARM64 || COMPILE_TEST + config SUN60I_A733_R_CCU tristate "Support for the Allwinner A733 PRCM CCU" default ARCH_SUNXI diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index d3702bdb7a23..3a39eb9287da 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_SUN50I_H616_CCU) +=3D sun50i-h616-ccu.o obj-$(CONFIG_SUN55I_A523_CCU) +=3D sun55i-a523-ccu.o obj-$(CONFIG_SUN55I_A523_MCU_CCU) +=3D sun55i-a523-mcu-ccu.o obj-$(CONFIG_SUN55I_A523_R_CCU) +=3D sun55i-a523-r-ccu.o +obj-$(CONFIG_SUN60I_A733_CCU) +=3D sun60i-a733-ccu.o obj-$(CONFIG_SUN60I_A733_R_CCU) +=3D sun60i-a733-r-ccu.o obj-$(CONFIG_SUN4I_A10_CCU) +=3D sun4i-a10-ccu.o obj-$(CONFIG_SUN5I_CCU) +=3D sun5i-ccu.o @@ -65,6 +66,7 @@ sun50i-h616-ccu-y +=3D ccu-sun50i-h616.o sun55i-a523-ccu-y +=3D ccu-sun55i-a523.o sun55i-a523-mcu-ccu-y +=3D ccu-sun55i-a523-mcu.o sun55i-a523-r-ccu-y +=3D ccu-sun55i-a523-r.o +sun60i-a733-ccu-y +=3D ccu-sun60i-a733.o sun60i-a733-r-ccu-y +=3D ccu-sun60i-a733-r.o sun4i-a10-ccu-y +=3D ccu-sun4i-a10.o sun5i-ccu-y +=3D ccu-sun5i.o diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c b/drivers/clk/sunxi-ng/= ccu-sun60i-a733.c new file mode 100644 index 000000000000..cf819504c51f --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c @@ -0,0 +1,535 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 rengaomin@allwinnertech.com + * Copyright (C) 2026 Junhui Liu + * Based on the A523 CCU driver: + * Copyright (C) 2023-2024 Arm Ltd. + */ + +#include +#include +#include +#include + +#include +#include + +#include "../clk.h" + +#include "ccu_common.h" + +#include "ccu_div.h" +#include "ccu_mult.h" +#include "ccu_nkmp.h" +#include "ccu_nm.h" + +/* + * The DCXO oscillator, the root of most of the clock tree. + * The physical crystal frequency (19.2MHz, 24MHz, or 26MHz) is + * hardware-detected by the RTC and represented here as "hosc". + */ +static const struct clk_parent_data hosc[] =3D { + { .fw_name =3D "hosc" } +}; + +/************************************************************************** + * PLLs * + *************************************************************************= */ + +#define SUN60I_A733_PLL_REF_REG 0x000 +static struct ccu_nkmp pll_ref_clk =3D { + .enable =3D BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT(8, 8), + .m =3D _SUNXI_CCU_DIV(16, 7), /* output divider */ + .p =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_REF_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("pll-ref", hosc, + &ccu_nkmp_ops, + CLK_SET_RATE_GATE), + }, +}; + +/* + * Most clock-defining macros expect an *array* of parent clocks, even if + * they do not contain a muxer to select between different parents. + * The macros ending in just _HW take a simple clock pointer, but then cre= ate + * a single-entry array out of that. The macros using _HWS take such an + * array (even when it is a single entry one), this avoids having those + * helper arrays created inside *every* clock definition. + * This means for every clock that is referenced more than once it is + * useful to create such a dummy array and use _HWS. + */ +static const struct clk_hw *pll_ref_hws[] =3D { + &pll_ref_clk.common.hw +}; + +#define SUN60I_A733_PLL_DDR_REG 0x020 +static struct ccu_nkmp pll_ddr_clk =3D { + .enable =3D BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(20, 3), /* output divider */ + .p =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_DDR_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-ddr", pll_ref_hws, + &ccu_nkmp_ops, + CLK_SET_RATE_GATE | + CLK_IS_CRITICAL), + }, +}; + +/* + * There is no actual clock output with that frequency (2.4 GHz), instead = it + * has multiple outputs with adjustable dividers from that base frequency. + * Model them separately as divider clocks based on that parent here. + */ +#define SUN60I_A733_PLL_PERIPH0_REG 0x0a0 +static struct ccu_nm pll_periph0_4x_clk =3D { + .enable =3D BIT(25) | BIT(26) | BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_PERIPH0_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-periph0-4x", + pll_ref_hws, &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_periph0_4x_hws[] =3D { + &pll_periph0_4x_clk.common.hw +}; + +static SUNXI_CCU_M_HWS(pll_periph0_2x_clk, "pll-periph0-2x", pll_periph0_4= x_hws, + SUN60I_A733_PLL_PERIPH0_REG, 20, 3, 0); +static const struct clk_hw *pll_periph0_2x_hws[] =3D { + &pll_periph0_2x_clk.common.hw +}; +static SUNXI_CCU_M_HWS(pll_periph0_800M_clk, "pll-periph0-800M", pll_perip= h0_4x_hws, + SUN60I_A733_PLL_PERIPH0_REG, 16, 3, 0); +static SUNXI_CCU_M_HWS(pll_periph0_480M_clk, "pll-periph0-480M", pll_perip= h0_4x_hws, + SUN60I_A733_PLL_PERIPH0_REG, 2, 3, 0); +static const struct clk_hw *pll_periph0_480M_hws[] =3D { + &pll_periph0_480M_clk.common.hw +}; +static CLK_FIXED_FACTOR_HWS(pll_periph0_600M_clk, "pll-periph0-600M", + pll_periph0_2x_hws, 2, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph0_400M_clk, "pll-periph0-400M", + pll_periph0_2x_hws, 3, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph0_300M_clk, "pll-periph0-300M", + pll_periph0_2x_hws, 4, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph0_200M_clk, "pll-periph0-200M", + pll_periph0_2x_hws, 6, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph0_150M_clk, "pll-periph0-150M", + pll_periph0_2x_hws, 8, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph0_160M_clk, "pll-periph0-160M", + pll_periph0_480M_hws, 3, 1, 0); + +#define SUN60I_A733_PLL_PERIPH1_REG 0x0c0 +static struct ccu_nm pll_periph1_4x_clk =3D { + .enable =3D BIT(25) | BIT(26) | BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_PERIPH1_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-periph1-4x", + pll_ref_hws, &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_periph1_4x_hws[] =3D { + &pll_periph1_4x_clk.common.hw +}; + +static SUNXI_CCU_M_HWS(pll_periph1_2x_clk, "pll-periph1-2x", pll_periph1_4= x_hws, + SUN60I_A733_PLL_PERIPH1_REG, 20, 3, 0); +static const struct clk_hw *pll_periph1_2x_hws[] =3D { + &pll_periph1_2x_clk.common.hw +}; +static SUNXI_CCU_M_HWS(pll_periph1_800M_clk, "pll-periph1-800M", pll_perip= h1_4x_hws, + SUN60I_A733_PLL_PERIPH1_REG, 16, 3, 0); +static SUNXI_CCU_M_HWS(pll_periph1_480M_clk, "pll-periph1-480M", pll_perip= h1_4x_hws, + SUN60I_A733_PLL_PERIPH1_REG, 2, 3, 0); +static const struct clk_hw *pll_periph1_480M_hws[] =3D { + &pll_periph1_480M_clk.common.hw +}; +static CLK_FIXED_FACTOR_HWS(pll_periph1_600M_clk, "pll-periph1-600M", + pll_periph1_2x_hws, 2, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph1_400M_clk, "pll-periph1-400M", + pll_periph1_2x_hws, 3, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph1_300M_clk, "pll-periph1-300M", + pll_periph1_2x_hws, 4, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph1_200M_clk, "pll-periph1-200M", + pll_periph1_2x_hws, 6, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph1_150M_clk, "pll-periph1-150M", + pll_periph1_2x_hws, 8, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph1_160M_clk, "pll-periph1-160M", + pll_periph1_480M_hws, 3, 1, 0); + +#define SUN60I_A733_PLL_GPU_REG 0x0e0 +static struct ccu_nkmp pll_gpu_clk =3D { + .enable =3D BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(20, 3), /* output divider */ + .p =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_GPU_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-gpu", pll_ref_hws, + &ccu_nkmp_ops, + CLK_SET_RATE_GATE), + }, +}; + +#define SUN60I_A733_PLL_VIDEO0_REG 0x120 +static struct ccu_nm pll_video0_8x_clk =3D { + .enable =3D BIT(26) | BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_VIDEO0_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-video0-8x", pll_ref_hws, + &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_video0_8x_hws[] =3D { + &pll_video0_8x_clk.common.hw +}; +static SUNXI_CCU_M_HWS(pll_video0_4x_clk, "pll-video0-4x", pll_video0_8x_h= ws, + SUN60I_A733_PLL_VIDEO0_REG, 20, 3, 0); +static SUNXI_CCU_M_HWS(pll_video0_3x_clk, "pll-video0-3x", pll_video0_8x_h= ws, + SUN60I_A733_PLL_VIDEO0_REG, 16, 3, 0); + +#define SUN60I_A733_PLL_VIDEO1_REG 0x140 +static struct ccu_nm pll_video1_8x_clk =3D { + .enable =3D BIT(26) | BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_VIDEO1_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-video1-8x", pll_ref_hws, + &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_video1_8x_hws[] =3D { + &pll_video1_8x_clk.common.hw +}; +static SUNXI_CCU_M_HWS(pll_video1_4x_clk, "pll-video1-4x", pll_video1_8x_h= ws, + SUN60I_A733_PLL_VIDEO1_REG, 20, 3, 0); +static SUNXI_CCU_M_HWS(pll_video1_3x_clk, "pll-video1-3x", pll_video1_8x_h= ws, + SUN60I_A733_PLL_VIDEO1_REG, 16, 3, 0); + +#define SUN60I_A733_PLL_VIDEO2_REG 0x160 +static struct ccu_nm pll_video2_8x_clk =3D { + .enable =3D BIT(26) | BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_VIDEO2_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-video2-8x", pll_ref_hws, + &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_video2_8x_hws[] =3D { + &pll_video2_8x_clk.common.hw +}; +static SUNXI_CCU_M_HWS(pll_video2_4x_clk, "pll-video2-4x", pll_video2_8x_h= ws, + SUN60I_A733_PLL_VIDEO2_REG, 20, 3, 0); +static SUNXI_CCU_M_HWS(pll_video2_3x_clk, "pll-video2-3x", pll_video2_8x_h= ws, + SUN60I_A733_PLL_VIDEO2_REG, 16, 3, 0); + +#define SUN60I_A733_PLL_VE0_REG 0x220 +static struct ccu_nkmp pll_ve0_clk =3D { + .enable =3D BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(20, 3), /* output divider */ + .p =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_VE0_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-ve0", pll_ref_hws, + &ccu_nkmp_ops, + CLK_SET_RATE_GATE), + }, +}; + +#define SUN60I_A733_PLL_VE1_REG 0x240 +static struct ccu_nkmp pll_ve1_clk =3D { + .enable =3D BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(20, 3), /* output divider */ + .p =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_VE1_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-ve1", pll_ref_hws, + &ccu_nkmp_ops, + CLK_SET_RATE_GATE), + }, +}; + +/* + * PLL_AUDIO0 has a m1 divider in addition to the usual N, M factors. + * Since we only need some fixed frequency from this PLL (22.5792MHz x 4), + * ignore the divider and force it to 1 (encoded as 0), in the probe funct= ion + * below. + * The M factor must be an even number to produce a 50% duty cycle output. + */ +#define SUN60I_A733_PLL_AUDIO0_REG 0x260 +static struct ccu_sdm_setting pll_audio0_sdm_table[] =3D { + { .rate =3D 90316800, .pattern =3D 0xa002872b, .m =3D 20, .n =3D 75 }, /*= 22.5792 * 4 */ +}; + +static struct ccu_nm pll_audio0_4x_clk =3D { + .enable =3D BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(16, 7), + .sdm =3D _SUNXI_CCU_SDM_DUAL_PAT(pll_audio0_sdm_table, + 0x268, BIT(31), + 0x26c, BIT(27) | BIT(31)), + .common =3D { + .reg =3D SUN60I_A733_PLL_AUDIO0_REG, + .features =3D CCU_FEATURE_SIGMA_DELTA_MOD, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-audio0-4x", pll_ref_hws, + &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +#define SUN60I_A733_PLL_AUDIO1_REG 0x280 +static struct ccu_nm pll_audio1_clk =3D { + .enable =3D BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_AUDIO1_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-audio1", pll_ref_hws, + &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_audio1_hws[] =3D { + &pll_audio1_clk.common.hw +}; +static SUNXI_CCU_M_HWS(pll_audio1_div2_clk, "pll-audio1-div2", pll_audio1_= hws, + SUN60I_A733_PLL_AUDIO1_REG, 20, 3, 0); +static SUNXI_CCU_M_HWS(pll_audio1_div5_clk, "pll-audio1-div5", pll_audio1_= hws, + SUN60I_A733_PLL_AUDIO1_REG, 16, 3, 0); + +#define SUN60I_A733_PLL_NPU_REG 0x2a0 +static struct ccu_nkmp pll_npu_clk =3D { + .enable =3D BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(20, 3), /* output divider */ + .p =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_NPU_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-npu", pll_ref_hws, + &ccu_nkmp_ops, + CLK_SET_RATE_GATE), + }, +}; + +#define SUN60I_A733_PLL_DE_REG 0x2e0 +static struct ccu_nm pll_de_clk =3D { + .enable =3D BIT(26) | BIT(27), + .lock =3D BIT(28), + .n =3D _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m =3D _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common =3D { + .reg =3D SUN60I_A733_PLL_DE_REG, + .hw.init =3D CLK_HW_INIT_PARENTS_HW("pll-de", pll_ref_hws, + &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_de_hws[] =3D { + &pll_de_clk.common.hw +}; +static SUNXI_CCU_M_HWS(pll_de_4x_clk, "pll-de-4x", pll_de_hws, + SUN60I_A733_PLL_DE_REG, 20, 3, 0); +static SUNXI_CCU_M_HWS(pll_de_3x_clk, "pll-de-3x", pll_de_hws, + SUN60I_A733_PLL_DE_REG, 16, 3, 0); + +/* + * Contains all clocks that are controlled by a hardware register. They + * have a (sunxi) .common member, which needs to be initialised by the com= mon + * sunxi CCU code, to be filled with the MMIO base address and the shared = lock. + */ +static struct ccu_common *sun60i_a733_ccu_clks[] =3D { + &pll_ref_clk.common, + &pll_ddr_clk.common, + &pll_periph0_4x_clk.common, + &pll_periph0_2x_clk.common, + &pll_periph0_800M_clk.common, + &pll_periph0_480M_clk.common, + &pll_periph1_4x_clk.common, + &pll_periph1_2x_clk.common, + &pll_periph1_800M_clk.common, + &pll_periph1_480M_clk.common, + &pll_gpu_clk.common, + &pll_video0_8x_clk.common, + &pll_video0_4x_clk.common, + &pll_video0_3x_clk.common, + &pll_video1_8x_clk.common, + &pll_video1_4x_clk.common, + &pll_video1_3x_clk.common, + &pll_video2_8x_clk.common, + &pll_video2_4x_clk.common, + &pll_video2_3x_clk.common, + &pll_ve0_clk.common, + &pll_ve1_clk.common, + &pll_audio0_4x_clk.common, + &pll_audio1_clk.common, + &pll_audio1_div2_clk.common, + &pll_audio1_div5_clk.common, + &pll_npu_clk.common, + &pll_de_clk.common, + &pll_de_4x_clk.common, + &pll_de_3x_clk.common, +}; + +static struct clk_hw_onecell_data sun60i_a733_hw_clks =3D { + .hws =3D { + [CLK_PLL_REF] =3D &pll_ref_clk.common.hw, + [CLK_PLL_DDR] =3D &pll_ddr_clk.common.hw, + [CLK_PLL_PERIPH0_4X] =3D &pll_periph0_4x_clk.common.hw, + [CLK_PLL_PERIPH0_2X] =3D &pll_periph0_2x_clk.common.hw, + [CLK_PLL_PERIPH0_800M] =3D &pll_periph0_800M_clk.common.hw, + [CLK_PLL_PERIPH0_480M] =3D &pll_periph0_480M_clk.common.hw, + [CLK_PLL_PERIPH0_600M] =3D &pll_periph0_600M_clk.hw, + [CLK_PLL_PERIPH0_400M] =3D &pll_periph0_400M_clk.hw, + [CLK_PLL_PERIPH0_300M] =3D &pll_periph0_300M_clk.hw, + [CLK_PLL_PERIPH0_200M] =3D &pll_periph0_200M_clk.hw, + [CLK_PLL_PERIPH0_160M] =3D &pll_periph0_160M_clk.hw, + [CLK_PLL_PERIPH0_150M] =3D &pll_periph0_150M_clk.hw, + [CLK_PLL_PERIPH1_4X] =3D &pll_periph1_4x_clk.common.hw, + [CLK_PLL_PERIPH1_2X] =3D &pll_periph1_2x_clk.common.hw, + [CLK_PLL_PERIPH1_800M] =3D &pll_periph1_800M_clk.common.hw, + [CLK_PLL_PERIPH1_480M] =3D &pll_periph1_480M_clk.common.hw, + [CLK_PLL_PERIPH1_600M] =3D &pll_periph1_600M_clk.hw, + [CLK_PLL_PERIPH1_400M] =3D &pll_periph1_400M_clk.hw, + [CLK_PLL_PERIPH1_300M] =3D &pll_periph1_300M_clk.hw, + [CLK_PLL_PERIPH1_200M] =3D &pll_periph1_200M_clk.hw, + [CLK_PLL_PERIPH1_160M] =3D &pll_periph1_160M_clk.hw, + [CLK_PLL_PERIPH1_150M] =3D &pll_periph1_150M_clk.hw, + [CLK_PLL_GPU] =3D &pll_gpu_clk.common.hw, + [CLK_PLL_VIDEO0_8X] =3D &pll_video0_8x_clk.common.hw, + [CLK_PLL_VIDEO0_4X] =3D &pll_video0_4x_clk.common.hw, + [CLK_PLL_VIDEO0_3X] =3D &pll_video0_3x_clk.common.hw, + [CLK_PLL_VIDEO1_8X] =3D &pll_video1_8x_clk.common.hw, + [CLK_PLL_VIDEO1_4X] =3D &pll_video1_4x_clk.common.hw, + [CLK_PLL_VIDEO1_3X] =3D &pll_video1_3x_clk.common.hw, + [CLK_PLL_VIDEO2_8X] =3D &pll_video2_8x_clk.common.hw, + [CLK_PLL_VIDEO2_4X] =3D &pll_video2_4x_clk.common.hw, + [CLK_PLL_VIDEO2_3X] =3D &pll_video2_3x_clk.common.hw, + [CLK_PLL_VE0] =3D &pll_ve0_clk.common.hw, + [CLK_PLL_VE1] =3D &pll_ve1_clk.common.hw, + [CLK_PLL_AUDIO0_4X] =3D &pll_audio0_4x_clk.common.hw, + [CLK_PLL_AUDIO1] =3D &pll_audio1_clk.common.hw, + [CLK_PLL_AUDIO1_DIV2] =3D &pll_audio1_div2_clk.common.hw, + [CLK_PLL_AUDIO1_DIV5] =3D &pll_audio1_div5_clk.common.hw, + [CLK_PLL_NPU] =3D &pll_npu_clk.common.hw, + [CLK_PLL_DE] =3D &pll_de_clk.common.hw, + [CLK_PLL_DE_4X] =3D &pll_de_4x_clk.common.hw, + [CLK_PLL_DE_3X] =3D &pll_de_3x_clk.common.hw, + }, + .num =3D CLK_FANOUT3 + 1, +}; + +static const struct sunxi_ccu_desc sun60i_a733_ccu_desc =3D { + .ccu_clks =3D sun60i_a733_ccu_clks, + .num_ccu_clks =3D ARRAY_SIZE(sun60i_a733_ccu_clks), + + .hw_clks =3D &sun60i_a733_hw_clks, +}; + +static const u32 pll_regs[] =3D { + SUN60I_A733_PLL_REF_REG, + SUN60I_A733_PLL_DDR_REG, + SUN60I_A733_PLL_PERIPH0_REG, + SUN60I_A733_PLL_PERIPH1_REG, + SUN60I_A733_PLL_GPU_REG, + SUN60I_A733_PLL_VIDEO0_REG, + SUN60I_A733_PLL_VIDEO1_REG, + SUN60I_A733_PLL_VIDEO2_REG, + SUN60I_A733_PLL_VE0_REG, + SUN60I_A733_PLL_VE1_REG, + SUN60I_A733_PLL_AUDIO0_REG, + SUN60I_A733_PLL_AUDIO1_REG, + SUN60I_A733_PLL_NPU_REG, + SUN60I_A733_PLL_DE_REG, +}; + +static int sun60i_a733_ccu_probe(struct platform_device *pdev) +{ + void __iomem *reg; + u32 val; + int i, ret; + + reg =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(reg)) + return PTR_ERR(reg); + + /* + * The PLL clock code does not model all bits, for instance it does + * not support a separate enable and gate bit. We present the + * gate bit(27) as the enable bit, but then have to set the + * PLL Enable, LDO Enable, and Lock Enable bits on all PLLs here. + */ + for (i =3D 0; i < ARRAY_SIZE(pll_regs); i++) { + val =3D readl(reg + pll_regs[i]); + val |=3D BIT(31) | BIT(30) | BIT(29); + writel(val, reg + pll_regs[i]); + } + + /* Enforce m1 =3D 0 for PLL_AUDIO0 */ + val =3D readl(reg + SUN60I_A733_PLL_AUDIO0_REG); + val &=3D ~BIT(1); + writel(val, reg + SUN60I_A733_PLL_AUDIO0_REG); + + ret =3D devm_sunxi_ccu_probe(&pdev->dev, reg, &sun60i_a733_ccu_desc); + if (ret) + return ret; + + return 0; +} + +static const struct of_device_id sun60i_a733_ccu_ids[] =3D { + { .compatible =3D "allwinner,sun60i-a733-ccu" }, + { /* sentinel */ } +}; + +static struct platform_driver sun60i_a733_ccu_driver =3D { + .probe =3D sun60i_a733_ccu_probe, + .driver =3D { + .name =3D "sun60i-a733-ccu", + .suppress_bind_attrs =3D true, + .of_match_table =3D sun60i_a733_ccu_ids, + }, +}; +module_platform_driver(sun60i_a733_ccu_driver); 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Tue, 10 Mar 2026 01:42:31 -0700 (PDT) From: Junhui Liu Date: Tue, 10 Mar 2026 16:33:58 +0800 Subject: [PATCH RFC 5/8] clk: sunxi-ng: a733: Add bus clocks support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260310-a733-clk-v1-5-36b4e9b24457@pigmoral.tech> References: <20260310-a733-clk-v1-0-36b4e9b24457@pigmoral.tech> In-Reply-To: <20260310-a733-clk-v1-0-36b4e9b24457@pigmoral.tech> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773132092; l=6909; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=HtxmFOI8Q42PtnTwtZVDl7nJsFiJiS6vOTLzORmX4tY=; b=fvujAYfom/CLtvUNwlxRK5z0pP279E297wEIHqzeUeANEuAlo78UAKS4ABEJUO8q8S3KQbO/9 dUPw3gsMPpRDLTHE9S9fSaIM56oaUpkbJ8/DyEbkDXwdXAnIV4K2yoj X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External Add the essential bus clocks in the Allwinner A733 CCU, including AHB, APB0, APB1, APB_UART, NSI, and MBUS. These buses are necessary for many other functional modules. Additionally clocks such as trace, gic and cpu_peri are also added as they fall within the register address range of the bus clocks, even though they are not strictly bus clocks. The MBUS clock is marked as critical to ensure the memory bus remains operational at all times. For the NSI and MBUS clocks, the hardware requires an update bit (bit 27) to be set so that the configuration takes effect and the updated parameters can be correctly read back. Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 131 +++++++++++++++++++++++++++++= ++++ 1 file changed, 131 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c b/drivers/clk/sunxi-ng/= ccu-sun60i-a733.c index cf819504c51f..68457813dbbb 100644 --- a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c @@ -19,6 +19,7 @@ #include "ccu_common.h" =20 #include "ccu_div.h" +#include "ccu_mp.h" #include "ccu_mult.h" #include "ccu_nkmp.h" #include "ccu_nm.h" @@ -65,6 +66,16 @@ static const struct clk_hw *pll_ref_hws[] =3D { &pll_ref_clk.common.hw }; =20 +/* + * There is a non-software-configurable mux selecting between the DCXO and= the + * PLL_REF in hardware, whose output is fed to the sys-24M clock. Although= both + * sys-24M and pll-ref are fixed at 24 MHz, define a 1:1 fixed factor cloc= k to + * provide logical separation: + * - pll-ref is dedicated to feeding other PLLs + * - sys-24M serves as reference clock for downstream functional modules + */ +static CLK_FIXED_FACTOR_HWS(sys_24M_clk, "sys-24M", pll_ref_hws, 1, 1, 0); + #define SUN60I_A733_PLL_DDR_REG 0x020 static struct ccu_nkmp pll_ddr_clk =3D { .enable =3D BIT(27), @@ -371,6 +382,107 @@ static SUNXI_CCU_M_HWS(pll_de_4x_clk, "pll-de-4x", pl= l_de_hws, static SUNXI_CCU_M_HWS(pll_de_3x_clk, "pll-de-3x", pll_de_hws, SUN60I_A733_PLL_DE_REG, 16, 3, 0); =20 +/************************************************************************** + * bus clocks * + *************************************************************************= */ + +static const struct clk_parent_data ahb_apb_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .fw_name =3D "losc" }, + { .fw_name =3D "iosc" }, + { .hw =3D &pll_periph0_600M_clk.hw }, +}; + +static SUNXI_CCU_M_DATA_WITH_MUX(ahb_clk, "ahb", ahb_apb_parents, 0x500, + 0, 5, /* M */ + 24, 2, /* mux */ + 0); + +static SUNXI_CCU_M_DATA_WITH_MUX(apb0_clk, "apb0", ahb_apb_parents, 0x510, + 0, 5, /* M */ + 24, 2, /* mux */ + 0); + +static SUNXI_CCU_M_DATA_WITH_MUX(apb1_clk, "apb1", ahb_apb_parents, 0x518, + 0, 5, /* M */ + 24, 2, /* mux */ + 0); + +static const struct clk_parent_data apb_uart_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .fw_name =3D "losc" }, + { .fw_name =3D "iosc" }, + { .hw =3D &pll_periph0_600M_clk.hw }, + { .hw =3D &pll_periph0_480M_clk.common.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX(apb_uart_clk, "apb-uart", apb_uart_parent= s, 0x538, + 0, 5, /* M */ + 24, 3, /* mux */ + 0); + +static const struct clk_parent_data trace_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .fw_name =3D "losc" }, + { .fw_name =3D "iosc" }, + { .hw =3D &pll_periph0_300M_clk.hw }, + { .hw =3D &pll_periph0_400M_clk.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(trace_clk, "trace", trace_parents, 0= x540, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data gic_cpu_peri_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .fw_name =3D "losc" }, + { .hw =3D &pll_periph0_600M_clk.hw }, + { .hw =3D &pll_periph0_480M_clk.common.hw }, + { .hw =3D &pll_periph0_400M_clk.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(gic_clk, "gic", gic_cpu_peri_parents= , 0x560, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(cpu_peri_clk, "cpu-peri", gic_cpu_pe= ri_parents, 0x568, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data nsi_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .hw =3D &pll_ddr_clk.common.hw }, + { .hw =3D &pll_periph0_800M_clk.common.hw }, + { .hw =3D &pll_periph0_600M_clk.hw }, + { .hw =3D &pll_periph0_480M_clk.common.hw }, + { .hw =3D &pll_de_3x_clk.common.hw }, +}; +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(nsi_clk, "nsi", nsi_parents, 0= x580, + 0, 5, /* M */ + 0, 0, /* no P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0, CCU_FEATURE_UPDATE_BIT); + +static const struct clk_parent_data mbus_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .hw =3D &pll_periph1_600M_clk.hw }, + { .hw =3D &pll_ddr_clk.common.hw }, + { .hw =3D &pll_periph1_480M_clk.common.hw }, + { .hw =3D &pll_periph1_400M_clk.hw }, + { .hw =3D &pll_npu_clk.common.hw }, +}; +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents= , 0x588, + 0, 5, /* M */ + 0, 0, /* no P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_IS_CRITICAL, + CCU_FEATURE_UPDATE_BIT); + /* * Contains all clocks that are controlled by a hardware register. They * have a (sunxi) .common member, which needs to be initialised by the com= mon @@ -407,11 +519,21 @@ static struct ccu_common *sun60i_a733_ccu_clks[] =3D { &pll_de_clk.common, &pll_de_4x_clk.common, &pll_de_3x_clk.common, + &ahb_clk.common, + &apb0_clk.common, + &apb1_clk.common, + &apb_uart_clk.common, + &trace_clk.common, + &gic_clk.common, + &cpu_peri_clk.common, + &nsi_clk.common, + &mbus_clk.common, }; =20 static struct clk_hw_onecell_data sun60i_a733_hw_clks =3D { .hws =3D { [CLK_PLL_REF] =3D &pll_ref_clk.common.hw, + [CLK_SYS_24M] =3D &sys_24M_clk.hw, [CLK_PLL_DDR] =3D &pll_ddr_clk.common.hw, [CLK_PLL_PERIPH0_4X] =3D &pll_periph0_4x_clk.common.hw, [CLK_PLL_PERIPH0_2X] =3D &pll_periph0_2x_clk.common.hw, @@ -453,6 +575,15 @@ static struct clk_hw_onecell_data sun60i_a733_hw_clks = =3D { [CLK_PLL_DE] =3D &pll_de_clk.common.hw, [CLK_PLL_DE_4X] =3D &pll_de_4x_clk.common.hw, [CLK_PLL_DE_3X] =3D &pll_de_3x_clk.common.hw, + [CLK_AHB] =3D &ahb_clk.common.hw, + [CLK_APB0] =3D &apb0_clk.common.hw, + [CLK_APB1] =3D &apb1_clk.common.hw, + [CLK_APB_UART] =3D &apb_uart_clk.common.hw, + [CLK_TRACE] =3D &trace_clk.common.hw, + [CLK_GIC] =3D &gic_clk.common.hw, + [CLK_CPU_PERI] =3D &cpu_peri_clk.common.hw, + [CLK_NSI] =3D &nsi_clk.common.hw, + [CLK_MBUS] =3D &mbus_clk.common.hw, }, .num =3D CLK_FANOUT3 + 1, }; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260310-a733-clk-v1-6-36b4e9b24457@pigmoral.tech> References: <20260310-a733-clk-v1-0-36b4e9b24457@pigmoral.tech> In-Reply-To: <20260310-a733-clk-v1-0-36b4e9b24457@pigmoral.tech> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773132092; l=38950; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=bDQQ07+q0sfEpEYyV7E3EisRqqof5mVY8dCFZ9d5GKQ=; b=t6cWjtq9MoHNfDfq+a8cf5hZYY12xWvcbS/w2ut1tOgvx+8CMulUGx8fAEKW+JaMiqSUoYNyQ podOeU+SWN9D3/PZ9bU8ft69fT9iZGo4QAzej3TtGwa+JGnnJK5thn3 X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External Add the module clocks found in the Allwinner A733 SoC, including video, storage, interfaces and others. While most of these clocks are similar to those in the A523 SoC, this implementation accounts for changes in register offsets and introduces support for new modules. Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 1108 ++++++++++++++++++++++++++++= ++++ 1 file changed, 1108 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c b/drivers/clk/sunxi-ng/= ccu-sun60i-a733.c index 68457813dbbb..36b44568a56f 100644 --- a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c @@ -19,8 +19,10 @@ #include "ccu_common.h" =20 #include "ccu_div.h" +#include "ccu_gate.h" #include "ccu_mp.h" #include "ccu_mult.h" +#include "ccu_mux.h" #include "ccu_nkmp.h" #include "ccu_nm.h" =20 @@ -75,6 +77,9 @@ static const struct clk_hw *pll_ref_hws[] =3D { * - sys-24M serves as reference clock for downstream functional modules */ static CLK_FIXED_FACTOR_HWS(sys_24M_clk, "sys-24M", pll_ref_hws, 1, 1, 0); +static const struct clk_hw *sys_24M_hws[] =3D { + &sys_24M_clk.hw +}; =20 #define SUN60I_A733_PLL_DDR_REG 0x020 static struct ccu_nkmp pll_ddr_clk =3D { @@ -133,10 +138,16 @@ static CLK_FIXED_FACTOR_HWS(pll_periph0_400M_clk, "pl= l-periph0-400M", pll_periph0_2x_hws, 3, 1, 0); static CLK_FIXED_FACTOR_HWS(pll_periph0_300M_clk, "pll-periph0-300M", pll_periph0_2x_hws, 4, 1, 0); +static const struct clk_hw *pll_periph0_300M_hws[] =3D { + &pll_periph0_300M_clk.hw +}; static CLK_FIXED_FACTOR_HWS(pll_periph0_200M_clk, "pll-periph0-200M", pll_periph0_2x_hws, 6, 1, 0); static CLK_FIXED_FACTOR_HWS(pll_periph0_150M_clk, "pll-periph0-150M", pll_periph0_2x_hws, 8, 1, 0); +static const struct clk_hw *pll_periph0_150M_hws[] =3D { + &pll_periph0_150M_clk.hw +}; static CLK_FIXED_FACTOR_HWS(pll_periph0_160M_clk, "pll-periph0-160M", pll_periph0_480M_hws, 3, 1, 0); =20 @@ -483,6 +494,915 @@ static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(mbus_clk,= "mbus", mbus_parents, 0x58 CLK_IS_CRITICAL, CCU_FEATURE_UPDATE_BIT); =20 +/************************************************************************** + * mod clocks * + *************************************************************************= */ + +static const struct clk_parent_data timer_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .fw_name =3D "iosc" }, + { .fw_name =3D "losc" }, + { .hw =3D &pll_periph0_200M_clk.hw }, + { .fw_name =3D "hosc" }, +}; +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer0_clk, "timer0", timer_parents= , 0x800, + 0, 0, /* no M */ + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer1_clk, "timer1", timer_parents= , 0x804, + 0, 0, /* no M */ + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer2_clk, "timer2", timer_parents= , 0x808, + 0, 0, /* no M */ + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer3_clk, "timer3", timer_parents= , 0x80c, + 0, 0, /* no M */ + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer4_clk, "timer4", timer_parents= , 0x810, + 0, 0, /* no M */ + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer5_clk, "timer5", timer_parents= , 0x814, + 0, 0, /* no M */ + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer6_clk, "timer6", timer_parents= , 0x818, + 0, 0, /* no M */ + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer7_clk, "timer7", timer_parents= , 0x81c, + 0, 0, /* no M */ + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer8_clk, "timer8", timer_parents= , 0x820, + 0, 0, /* no M */ + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer9_clk, "timer9", timer_parents= , 0x824, + 0, 0, /* no M */ + 0, 3, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data avs_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .fw_name =3D "hosc" }, +}; +static SUNXI_CCU_MUX_DATA_WITH_GATE(avs_clk, "avs-clk", avs_parents, 0x880, + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *de_parents[] =3D { + &pll_de_3x_clk.common.hw, + &pll_de_4x_clk.common.hw, + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, + &pll_periph0_300M_clk.hw, + &pll_video0_4x_clk.common.hw, + &pll_video2_4x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(de_clk, "de", de_parents, 0xa00, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *di_parents[] =3D { + &pll_periph0_600M_clk.hw, + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, + &pll_video0_4x_clk.common.hw, + &pll_video2_4x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(di_clk, "di", di_parents, 0xa20, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *g2d_parents[] =3D { + &pll_periph0_400M_clk.hw, + &pll_periph0_300M_clk.hw, + &pll_video0_4x_clk.common.hw, + &pll_video1_4x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(g2d_clk, "g2d", g2d_parents, 0xa40, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *eink_parents[] =3D { + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(eink_clk, "eink", eink_parents, 0xa60, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *eink_panel_parents[] =3D { + &pll_video0_4x_clk.common.hw, + &pll_video0_3x_clk.common.hw, + &pll_video1_4x_clk.common.hw, + &pll_video1_3x_clk.common.hw, + &pll_periph0_300M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(eink_panel_clk, "eink-panel", eink_pan= el_parents, 0xa64, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *ve_enc_parents[] =3D { + &pll_ve0_clk.common.hw, + &pll_ve1_clk.common.hw, + &pll_periph0_800M_clk.common.hw, + &pll_periph0_600M_clk.hw, + &pll_periph0_480M_clk.common.hw, + &pll_de_3x_clk.common.hw, + &pll_npu_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_enc_clk, "ve-enc", ve_enc_parents, = 0xa80, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *ve_dec_parents[] =3D { + &pll_ve1_clk.common.hw, + &pll_ve0_clk.common.hw, + &pll_periph0_800M_clk.common.hw, + &pll_periph0_600M_clk.hw, + &pll_periph0_480M_clk.common.hw, + &pll_de_3x_clk.common.hw, + &pll_npu_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_dec_clk, "ve-dec", ve_dec_parents, = 0xa88, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *ce_parents[] =3D { + &sys_24M_clk.hw, + &pll_periph0_400M_clk.hw, + &pll_periph0_600M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0xac0, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *npu_parents[] =3D { + &pll_npu_clk.common.hw, + &pll_periph0_800M_clk.common.hw, + &pll_periph0_600M_clk.hw, + &pll_periph0_480M_clk.common.hw, + &pll_ve0_clk.common.hw, + &pll_ve1_clk.common.hw, + &pll_de_3x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(npu_clk, "npu", npu_parents, 0xb00, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +/* + * GPU_CLK =3D ClockSource * ((16 - M) / 16) + * Here we use a div_table to select M values that result in integer divis= ors. + */ +static struct clk_div_table gpu_div_table[] =3D { + { .val =3D 0, .div =3D 1 }, + { .val =3D 8, .div =3D 2 }, + { .val =3D 12, .div =3D 4 }, + { .val =3D 14, .div =3D 8 }, + { .val =3D 15, .div =3D 16 }, + { /* sentinel */ }, +}; +static const struct clk_parent_data gpu_parents[] =3D { + { .hw =3D &pll_gpu_clk.common.hw, }, + { .hw =3D &pll_periph0_800M_clk.common.hw, }, + { .hw =3D &pll_periph0_600M_clk.hw, }, + { .hw =3D &pll_periph0_400M_clk.hw, }, + { .hw =3D &pll_periph0_300M_clk.hw, }, + { .hw =3D &pll_periph0_200M_clk.hw, }, +}; +static struct ccu_div gpu_clk =3D { + .enable =3D BIT(31), + .div =3D _SUNXI_CCU_DIV_TABLE(0, 4, gpu_div_table), + .mux =3D _SUNXI_CCU_MUX(24, 3), + .common =3D { + .reg =3D 0xb20, + .features =3D CCU_FEATURE_UPDATE_BIT, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("gpu", gpu_parents, + &ccu_div_ops, 0), + } +}; + +static const struct clk_parent_data dram_parents[] =3D { + { .hw =3D &pll_ddr_clk.common.hw, }, + { .hw =3D &pll_periph0_800M_clk.common.hw, }, + { .hw =3D &pll_periph0_600M_clk.hw, }, + { .hw =3D &pll_de_clk.common.hw, }, + { .hw =3D &pll_npu_clk.common.hw, }, +}; +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(dram_clk, "dram", dram_parents= , 0xc00, + 0, 4, /* M */ + 0, 0, /* no P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + CLK_IS_CRITICAL, + CCU_FEATURE_UPDATE_BIT); + +static const struct clk_parent_data nand_mmc_parents[] =3D { + { .hw =3D &sys_24M_clk.hw, }, + { .hw =3D &pll_periph0_400M_clk.hw, }, + { .hw =3D &pll_periph0_300M_clk.hw, }, + { .hw =3D &pll_periph1_400M_clk.hw, }, + { .hw =3D &pll_periph1_300M_clk.hw, }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(nand0_clk, "nand0", nand_mmc_parents= , 0xc80, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(nand1_clk, "nand1", nand_mmc_parents= , 0xc84, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc0_clk, "mmc0", nand_mmc_pa= rents, 0xd00, + 0, 5, /* M */ + 8, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 2, /* post div */ + 0); +static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc1_clk, "mmc1", nand_mmc_pa= rents, 0xd10, + 0, 5, /* M */ + 8, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 2, /* post div */ + 0); + +static const struct clk_parent_data mmc2_mmc3_parents[] =3D { + { .hw =3D &sys_24M_clk.hw, }, + { .hw =3D &pll_periph0_800M_clk.common.hw }, + { .hw =3D &pll_periph0_600M_clk.hw }, + { .hw =3D &pll_periph1_800M_clk.common.hw }, + { .hw =3D &pll_periph1_600M_clk.hw }, +}; +static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc2_clk, "mmc2", mmc2_mmc3_p= arents, 0xd20, + 0, 5, /* M */ + 8, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 2, /* post div */ + 0); +static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc3_clk, "mmc3", mmc2_mmc3_p= arents, 0xd30, + 0, 5, /* M */ + 8, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 2, /* post div */ + 0); + +static const struct clk_hw *ufs_axi_parents[] =3D { + &pll_periph0_300M_clk.hw, + &pll_periph0_200M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(ufs_axi_clk, "ufs-axi", ufs_axi_parent= s, 0xd80, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data ufs_cfg_parents[] =3D { + { .hw =3D &pll_periph0_480M_clk.common.hw }, + { .fw_name =3D "hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ufs_cfg_clk, "ufs-cfg", ufs_cfg_pare= nts, 0xd84, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data spi_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .hw =3D &pll_periph0_300M_clk.hw }, + { .hw =3D &pll_periph0_200M_clk.hw }, + { .hw =3D &pll_periph1_300M_clk.hw }, + { .hw =3D &pll_periph1_200M_clk.hw }, + { .hw =3D &pll_periph0_480M_clk.common.hw }, + { .hw =3D &pll_periph1_480M_clk.common.hw }, + { .fw_name =3D "hosc"}, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(spi0_clk, "spi0", spi_parents, 0xf00, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_DUALDIV_MUX_GATE(spi1_clk, "spi1", spi_parents, 0xf08, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_DUALDIV_MUX_GATE(spi2_clk, "spi2", spi_parents, 0xf10, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_DUALDIV_MUX_GATE(spi3_clk, "spi3", spi_parents, 0xf20, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_DUALDIV_MUX_GATE(spi4_clk, "spi4", spi_parents, 0xf28, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data spif_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .hw =3D &pll_periph0_400M_clk.hw }, + { .hw =3D &pll_periph0_300M_clk.hw }, + { .hw =3D &pll_periph1_400M_clk.hw }, + { .hw =3D &pll_periph1_300M_clk.hw }, + { .hw =3D &pll_periph0_160M_clk.hw }, + { .hw =3D &pll_periph1_160M_clk.hw }, + { .fw_name =3D "hosc"}, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(spif_clk, "spif", spif_parents, 0xf18, + 0, 5, /* M */ + 8, 5, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data gpadc_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .fw_name =3D "hosc"}, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(gpadc_clk, "gpadc", gpadc_parents, 0= xfc0, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data irrx_parents[] =3D { + { .fw_name =3D "losc"}, + { .hw =3D &sys_24M_clk.hw }, + { .fw_name =3D "hosc"}, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(irrx_clk, "irrx", irrx_parents, 0x10= 00, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data irtx_parents[] =3D { + { .fw_name =3D "losc"}, + { .hw =3D &pll_periph1_600M_clk.hw }, + { .fw_name =3D "hosc"}, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(irtx_clk, "irtx", irtx_parents, 0x10= 08, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data sgpio_parents[] =3D { + { .fw_name =3D "losc"}, + { .hw =3D &sys_24M_clk.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(sgpio_clk, "sgpio", sgpio_parents, 0= x1060, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *lpc_parents[] =3D { + &pll_video0_3x_clk.common.hw, + &pll_video1_3x_clk.common.hw, + &pll_video2_3x_clk.common.hw, + &pll_periph0_300M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(lpc_clk, "lpc", lpc_parents, 0x1080, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *i2spcm_parents[] =3D { + &pll_audio0_4x_clk.common.hw, + &pll_audio1_div2_clk.common.hw, + &pll_audio1_div5_clk.common.hw, + &pll_periph0_200M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm0_clk, "i2spcm0", i2spcm_parents= , 0x1200, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm1_clk, "i2spcm1", i2spcm_parents= , 0x1210, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm2_clk, "i2spcm2", i2spcm_parents= , 0x1220, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm3_clk, "i2spcm3", i2spcm_parents= , 0x1230, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm4_clk, "i2spcm4", i2spcm_parents= , 0x1240, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *i2spcm2_asrc_parents[] =3D { + &pll_audio0_4x_clk.common.hw, + &pll_audio1_div2_clk.common.hw, + &pll_audio1_div5_clk.common.hw, + &pll_periph0_300M_clk.hw, + &pll_periph1_300M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm2_asrc_clk, "i2spcm2_asrc", i2sp= cm2_asrc_parents, 0x1224, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *owa_tx_parents[] =3D { + &pll_audio0_4x_clk.common.hw, + &pll_audio1_div2_clk.common.hw, + &pll_audio1_div5_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(owa_tx_clk, "owa_tx", owa_tx_parents, = 0x1280, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *owa_rx_parents[] =3D { + &pll_periph0_200M_clk.hw, + &pll_periph0_300M_clk.hw, + &pll_periph0_400M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(owa_rx_clk, "owa_rx", owa_rx_parents, = 0x1284, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *dmic_parents[] =3D { + &pll_audio0_4x_clk.common.hw, + &pll_audio1_div2_clk.common.hw, + &pll_audio1_div5_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(dmic_clk, "dmic", dmic_parents, 0x12c0, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +/* + * The first parent is a 48 MHz input clock divided by 4. That 48 MHz cloc= k is + * a 2x multiplier from pll-ref synchronized by pll-periph0, and is also u= sed by + * the OHCI module. + */ +static const struct clk_parent_data usb_ohci_parents[] =3D { + { .hw =3D &pll_periph0_4x_clk.common.hw }, + { .hw =3D &sys_24M_clk.hw }, + { .fw_name =3D "losc" }, + { .fw_name =3D "iosc" }, +}; +static const struct ccu_mux_fixed_prediv usb_ohci_predivs[] =3D { + { .index =3D 0, .div =3D 200 }, + { .index =3D 1, .div =3D 2 }, +}; + +static struct ccu_mux usb_ohci0_clk =3D { + .enable =3D BIT(31), + .mux =3D { + .shift =3D 24, + .width =3D 2, + .fixed_predivs =3D usb_ohci_predivs, + .n_predivs =3D ARRAY_SIZE(usb_ohci_predivs), + }, + .common =3D { + .reg =3D 0x1300, + .features =3D CCU_FEATURE_FIXED_PREDIV, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("usb-ohci0", usb_ohci_parents, + &ccu_mux_ops, 0), + }, +}; + +static struct ccu_mux usb_ohci1_clk =3D { + .enable =3D BIT(31), + .mux =3D { + .shift =3D 24, + .width =3D 2, + .fixed_predivs =3D usb_ohci_predivs, + .n_predivs =3D ARRAY_SIZE(usb_ohci_predivs), + }, + .common =3D { + .reg =3D 0x1308, + .features =3D CCU_FEATURE_FIXED_PREDIV, + .hw.init =3D CLK_HW_INIT_PARENTS_DATA("usb-ohci1", usb_ohci_parents, + &ccu_mux_ops, 0), + }, +}; + +static const struct clk_parent_data usb_ref_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .fw_name =3D "hosc" }, +}; +static SUNXI_CCU_MUX_DATA(usb_ref_clk, "usb-ref", usb_ref_parents, 0x1340,= 24, 3, 0); + +static SUNXI_CCU_MUX_DATA(usb2_u2_ref_clk, "usb2-u2-ref", usb_ref_parents,= 0x1348, 24, 3, 0); + +static const struct clk_parent_data usb2_suspend_parents[] =3D { + { .fw_name =3D "losc" }, + { .hw =3D &sys_24M_clk.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_suspend_clk, "usb2-suspend", us= b2_suspend_parents, + 0x1350, + 0, 5, /* M */ + 24, 1, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data usb2_mf_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .hw =3D &pll_periph0_300M_clk.hw }, + { .fw_name =3D "hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_mf_clk, "usb2-mf", usb2_mf_pare= nts, + 0x1354, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data usb2_u3_utmi_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .hw =3D &pll_periph0_300M_clk.hw }, + { .fw_name =3D "hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_u3_utmi_clk, "usb2-u3-utmi", us= b2_u3_utmi_parents, + 0x1360, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data usb2_u2_pipe_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .hw =3D &pll_periph0_480M_clk.common.hw }, + { .fw_name =3D "hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_u2_pipe_clk, "usb2-u2-pipe", us= b2_u2_pipe_parents, + 0x1364, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data pcie_aux_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .fw_name =3D "losc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(pcie_aux_clk, "pcie-aux", pcie_aux_p= arents, 0x1380, + 0, 5, /* M */ + 24, 1, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *pcie_axi_slv_parents[] =3D { + &pll_periph0_600M_clk.hw, + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(pcie_axi_slv_clk, "pcie-axi-slv", pcie= _axi_slv_parents, 0x1384, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *serdes_phy_parents[] =3D { + &sys_24M_clk.hw, + &pll_periph0_600M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(serdes_phy_clk, "serdes-phy", serdes_p= hy_parents, 0x13c0, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data gmac_ptp_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .hw =3D &pll_periph0_200M_clk.hw }, + { .fw_name =3D "hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(gmac_ptp_clk, "gmac-ptp", gmac_ptp_p= arents, 0x1400, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_M_HWS_WITH_GATE(gmac0_phy_clk, "gmac0-phy", pll_periph0_1= 50M_hws, 0x1410, + 0, 5, /* M */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HWS_WITH_GATE(gmac1_phy_clk, "gmac1-phy", pll_periph0_1= 50M_hws, 0x1420, + 0, 5, /* M */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *tcon_lcd_parents[] =3D { + &pll_video0_4x_clk.common.hw, + &pll_video1_4x_clk.common.hw, + &pll_video2_4x_clk.common.hw, + &pll_periph0_2x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_lcd_p= arents, 0x1500, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_lcd_p= arents, 0x1508, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd2_clk, "tcon-lcd2", tcon_lcd_p= arents, 0x1510, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *dsi_parents[] =3D { + &sys_24M_clk.hw, + &pll_periph0_200M_clk.hw, + &pll_periph0_150M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(dsi0_clk, "dsi0", dsi_parents, 0x1580, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(dsi1_clk, "dsi1", dsi_parents, 0x1588, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *combphy_parents[] =3D { + &pll_video0_4x_clk.common.hw, + &pll_video1_4x_clk.common.hw, + &pll_video2_4x_clk.common.hw, + &pll_periph0_2x_clk.common.hw, + &pll_video0_3x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(combphy0_clk, "combphy0", combphy_pare= nts, 0x15c0, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(combphy1_clk, "combphy1", combphy_pare= nts, 0x15c4, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *edp_tv_parents[] =3D { + &pll_video0_4x_clk.common.hw, + &pll_video1_4x_clk.common.hw, + &pll_video2_4x_clk.common.hw, + &pll_periph0_2x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(edp_tv_clk, "edp-tv", edp_tv_parents, = 0x1640, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(hdmi_cec_32k_clk, "hdmi-cec-32k", pl= l_periph0_2x_hws, 0x1680, + BIT(30), /* gate */ + 36621, /* pre div */ + 0); + +static const struct clk_parent_data hdmi_cec_parents[] =3D { + { .fw_name =3D "losc" }, + { .hw =3D &hdmi_cec_32k_clk.common.hw }, +}; +static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_cec_clk, "hdmi-cec", hdmi_cec_par= ents, 0x1680, + 24, 1, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data hdmi_tv_parents[] =3D { + { .hw =3D &pll_video0_4x_clk.common.hw }, + { .hw =3D &pll_video1_4x_clk.common.hw }, + { .hw =3D &pll_video2_4x_clk.common.hw }, + { .hw =3D &pll_periph0_2x_clk.common.hw }, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(hdmi_tv_clk, "hdmi-tv", hdmi_tv_parents,= 0x1684, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data hdmi_sfr_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .fw_name =3D "hosc" }, +}; +static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_sfr_clk, "hdmi-sfr", hdmi_sfr_par= ents, 0x1690, + 24, 1, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_GATE_HWS(hdmi_esm_clk, "hdmi-esm", pll_periph0_300M_hws, = 0x1694, BIT(31), 0); + +static const struct clk_parent_data ledc_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .hw =3D &pll_periph0_600M_clk.hw }, + { .fw_name =3D "hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ledc_clk, "ledc", ledc_parents, 0x17= 00, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data csi_master_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .hw =3D &pll_video0_4x_clk.common.hw }, + { .hw =3D &pll_video0_3x_clk.common.hw }, + { .hw =3D &pll_video1_4x_clk.common.hw }, + { .hw =3D &pll_video1_3x_clk.common.hw }, + { .hw =3D &pll_video2_4x_clk.common.hw }, + { .hw =3D &pll_video2_3x_clk.common.hw }, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(csi_master0_clk, "csi_master0", csi_mast= er_parents, 0x1800, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_DUALDIV_MUX_GATE(csi_master1_clk, "csi_master1", csi_mast= er_parents, 0x1804, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); +static SUNXI_CCU_DUALDIV_MUX_GATE(csi_master2_clk, "csi_master2", csi_mast= er_parents, 0x1808, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *csi_parents[] =3D { + &pll_video2_4x_clk.common.hw, + &pll_de_4x_clk.common.hw, + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, + &pll_periph0_600M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_clk, "csi", csi_parents, 0x1840, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_hw *isp_parents[] =3D { + &pll_video2_4x_clk.common.hw, + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, + &pll_periph0_600M_clk.hw, + &pll_video0_4x_clk.common.hw, + &pll_video1_4x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(isp_clk, "isp", isp_parents, 0x1860, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data apb2jtag_parents[] =3D { + { .hw =3D &sys_24M_clk.hw }, + { .fw_name =3D "losc" }, + { .fw_name =3D "iosc" }, + { .hw =3D &pll_periph0_480M_clk.common.hw }, + { .hw =3D &pll_periph1_480M_clk.common.hw }, + { .hw =3D &pll_periph0_200M_clk.hw }, + { .hw =3D &pll_periph1_200M_clk.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(apb2jtag_clk, "apb2jtag", apb2jtag_p= arents, 0x1c00, + 0, 5, /* M */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 0); + +static SUNXI_CCU_GATE_HWS(fanout_24M_clk, "fanout-24M", sys_24M_hws, 0x1f3= 0, BIT(0), 0); +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_12M_clk, "fanout-12M", sys_24= M_hws, 0x1f30, + BIT(1), 2, 0); +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M", pll_pe= riph0_480M_hws, 0x1f30, + BIT(2), 30, 0); +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M", pll_pe= riph0_2x_hws, 0x1f30, + BIT(3), 48, 0); + +static const struct clk_parent_data fanout_27M_parents[] =3D { + { .hw =3D &pll_video0_4x_clk.common.hw }, + { .hw =3D &pll_video1_4x_clk.common.hw }, + { .hw =3D &pll_video2_4x_clk.common.hw }, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_27M_clk, "fanout-27M", fanout_27M= _parents, 0x1f34, + 0, 5, /* M */ + 8, 5, /* N */ + 24, 2, /* mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data fanout_pclk_parents[] =3D { + { .hw =3D &apb0_clk.common.hw } +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_pclk_clk, "fanout-pclk", fanout_p= clk_parents, 0x1f38, + 0, 5, /* M */ + 5, 5, /* N */ + 0, 0, /* no mux */ + BIT(31), /* gate */ + 0); + +static const struct clk_parent_data fanout_parents[] =3D { + { .fw_name =3D "losc-fanout" }, + { .hw =3D &fanout_12M_clk.common.hw, }, + { .hw =3D &fanout_16M_clk.common.hw, }, + { .hw =3D &fanout_24M_clk.common.hw, }, + { .hw =3D &fanout_25M_clk.common.hw, }, + { .hw =3D &fanout_27M_clk.common.hw, }, + { .hw =3D &fanout_pclk_clk.common.hw, }, +}; +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout0_clk, "fanout0", fanout_parents= , 0x1f3c, + 0, 3, /* mux */ + BIT(21), /* gate */ + 0); +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout1_clk, "fanout1", fanout_parents= , 0x1f3c, + 3, 3, /* mux */ + BIT(22), /* gate */ + 0); +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout2_clk, "fanout2", fanout_parents= , 0x1f3c, + 6, 3, /* mux */ + BIT(23), /* gate */ + 0); +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout3_clk, "fanout3", fanout_parents= , 0x1f3c, + 9, 3, /* mux */ + BIT(24), /* gate */ + 0); + /* * Contains all clocks that are controlled by a hardware register. They * have a (sunxi) .common member, which needs to be initialised by the com= mon @@ -528,6 +1448,100 @@ static struct ccu_common *sun60i_a733_ccu_clks[] =3D= { &cpu_peri_clk.common, &nsi_clk.common, &mbus_clk.common, + &timer0_clk.common, + &timer1_clk.common, + &timer2_clk.common, + &timer3_clk.common, + &timer4_clk.common, + &timer5_clk.common, + &timer6_clk.common, + &timer7_clk.common, + &timer8_clk.common, + &timer9_clk.common, + &avs_clk.common, + &de_clk.common, + &di_clk.common, + &g2d_clk.common, + &eink_clk.common, + &eink_panel_clk.common, + &ve_enc_clk.common, + &ve_dec_clk.common, + &ce_clk.common, + &npu_clk.common, + &gpu_clk.common, + &dram_clk.common, + &nand0_clk.common, + &nand1_clk.common, + &mmc0_clk.common, + &mmc1_clk.common, + &mmc2_clk.common, + &mmc3_clk.common, + &ufs_axi_clk.common, + &ufs_cfg_clk.common, + &spi0_clk.common, + &spi1_clk.common, + &spi2_clk.common, + &spi3_clk.common, + &spi4_clk.common, + &spif_clk.common, + &gpadc_clk.common, + &irrx_clk.common, + &irtx_clk.common, + &sgpio_clk.common, + &lpc_clk.common, + &i2spcm0_clk.common, + &i2spcm1_clk.common, + &i2spcm2_clk.common, + &i2spcm3_clk.common, + &i2spcm4_clk.common, + &i2spcm2_asrc_clk.common, + &owa_tx_clk.common, + &owa_rx_clk.common, + &dmic_clk.common, + &usb_ohci0_clk.common, + &usb_ohci1_clk.common, + &usb_ref_clk.common, + &usb2_u2_ref_clk.common, + &usb2_suspend_clk.common, + &usb2_mf_clk.common, + &usb2_u3_utmi_clk.common, + &usb2_u2_pipe_clk.common, + &pcie_aux_clk.common, + &pcie_axi_slv_clk.common, + &serdes_phy_clk.common, + &gmac_ptp_clk.common, + &gmac0_phy_clk.common, + &gmac1_phy_clk.common, + &tcon_lcd0_clk.common, + &tcon_lcd1_clk.common, + &tcon_lcd2_clk.common, + &dsi0_clk.common, + &dsi1_clk.common, + &combphy0_clk.common, + &combphy1_clk.common, + &edp_tv_clk.common, + &hdmi_cec_32k_clk.common, + &hdmi_cec_clk.common, + &hdmi_tv_clk.common, + &hdmi_sfr_clk.common, + &hdmi_esm_clk.common, + &ledc_clk.common, + &csi_master0_clk.common, + &csi_master1_clk.common, + &csi_master2_clk.common, + &csi_clk.common, + &isp_clk.common, + &apb2jtag_clk.common, + &fanout_24M_clk.common, + &fanout_12M_clk.common, + &fanout_16M_clk.common, + &fanout_25M_clk.common, + &fanout_27M_clk.common, + &fanout_pclk_clk.common, + &fanout0_clk.common, + &fanout1_clk.common, + &fanout2_clk.common, + &fanout3_clk.common, }; =20 static struct clk_hw_onecell_data sun60i_a733_hw_clks =3D { @@ -584,6 +1598,100 @@ static struct clk_hw_onecell_data sun60i_a733_hw_clk= s =3D { [CLK_CPU_PERI] =3D &cpu_peri_clk.common.hw, [CLK_NSI] =3D &nsi_clk.common.hw, [CLK_MBUS] =3D &mbus_clk.common.hw, + [CLK_TIMER0] =3D &timer0_clk.common.hw, + [CLK_TIMER1] =3D &timer1_clk.common.hw, + [CLK_TIMER2] =3D &timer2_clk.common.hw, + [CLK_TIMER3] =3D &timer3_clk.common.hw, + [CLK_TIMER4] =3D &timer4_clk.common.hw, + [CLK_TIMER5] =3D &timer5_clk.common.hw, + [CLK_TIMER6] =3D &timer6_clk.common.hw, + [CLK_TIMER7] =3D &timer7_clk.common.hw, + [CLK_TIMER8] =3D &timer8_clk.common.hw, + [CLK_TIMER9] =3D &timer9_clk.common.hw, + [CLK_AVS] =3D &avs_clk.common.hw, + [CLK_DE] =3D &de_clk.common.hw, + [CLK_DI] =3D &di_clk.common.hw, + [CLK_G2D] =3D &g2d_clk.common.hw, + [CLK_EINK] =3D &eink_clk.common.hw, + [CLK_EINK_PANEL] =3D &eink_panel_clk.common.hw, + [CLK_VE_ENC] =3D &ve_enc_clk.common.hw, + [CLK_VE_DEC] =3D &ve_dec_clk.common.hw, + [CLK_CE] =3D &ce_clk.common.hw, + [CLK_NPU] =3D &npu_clk.common.hw, + [CLK_GPU] =3D &gpu_clk.common.hw, + [CLK_DRAM] =3D &dram_clk.common.hw, + [CLK_NAND0] =3D &nand0_clk.common.hw, + [CLK_NAND1] =3D &nand1_clk.common.hw, + [CLK_MMC0] =3D &mmc0_clk.common.hw, + [CLK_MMC1] =3D &mmc1_clk.common.hw, + [CLK_MMC2] =3D &mmc2_clk.common.hw, + [CLK_MMC3] =3D &mmc3_clk.common.hw, + [CLK_UFS_AXI] =3D &ufs_axi_clk.common.hw, + [CLK_UFS_CFG] =3D &ufs_cfg_clk.common.hw, + [CLK_SPI0] =3D &spi0_clk.common.hw, + [CLK_SPI1] =3D &spi1_clk.common.hw, + [CLK_SPI2] =3D &spi2_clk.common.hw, + [CLK_SPI3] =3D &spi3_clk.common.hw, + [CLK_SPI4] =3D &spi4_clk.common.hw, + [CLK_SPIF] =3D &spif_clk.common.hw, + [CLK_GPADC] =3D &gpadc_clk.common.hw, + [CLK_IRRX] =3D &irrx_clk.common.hw, + [CLK_IRTX] =3D &irtx_clk.common.hw, + [CLK_SGPIO] =3D &sgpio_clk.common.hw, + [CLK_LPC] =3D &lpc_clk.common.hw, + [CLK_I2SPCM0] =3D &i2spcm0_clk.common.hw, + [CLK_I2SPCM1] =3D &i2spcm1_clk.common.hw, + [CLK_I2SPCM2] =3D &i2spcm2_clk.common.hw, + [CLK_I2SPCM3] =3D &i2spcm3_clk.common.hw, + [CLK_I2SPCM4] =3D &i2spcm4_clk.common.hw, + [CLK_I2SPCM2_ASRC] =3D &i2spcm2_asrc_clk.common.hw, + [CLK_OWA_TX] =3D &owa_tx_clk.common.hw, + [CLK_OWA_RX] =3D &owa_rx_clk.common.hw, + [CLK_DMIC] =3D &dmic_clk.common.hw, + [CLK_USB_OHCI0] =3D &usb_ohci0_clk.common.hw, + [CLK_USB_OHCI1] =3D &usb_ohci1_clk.common.hw, + [CLK_USB_REF] =3D &usb_ref_clk.common.hw, + [CLK_USB2_U2_REF] =3D &usb2_u2_ref_clk.common.hw, + [CLK_USB2_SUSPEND] =3D &usb2_suspend_clk.common.hw, + [CLK_USB2_MF] =3D &usb2_mf_clk.common.hw, + [CLK_USB2_U3_UTMI] =3D &usb2_u3_utmi_clk.common.hw, + [CLK_USB2_U2_PIPE] =3D &usb2_u2_pipe_clk.common.hw, + [CLK_PCIE_AUX] =3D &pcie_aux_clk.common.hw, + [CLK_PCIE_AXI_SLV] =3D &pcie_axi_slv_clk.common.hw, + [CLK_SERDES_PHY] =3D &serdes_phy_clk.common.hw, + [CLK_GMAC_PTP] =3D &gmac_ptp_clk.common.hw, + [CLK_GMAC0_PHY] =3D &gmac0_phy_clk.common.hw, + [CLK_GMAC1_PHY] =3D &gmac1_phy_clk.common.hw, + [CLK_TCON_LCD0] =3D &tcon_lcd0_clk.common.hw, + [CLK_TCON_LCD1] =3D &tcon_lcd1_clk.common.hw, + [CLK_TCON_LCD2] =3D &tcon_lcd2_clk.common.hw, + [CLK_DSI0] =3D &dsi0_clk.common.hw, + [CLK_DSI1] =3D &dsi1_clk.common.hw, + [CLK_COMBPHY0] =3D &combphy0_clk.common.hw, + [CLK_COMBPHY1] =3D &combphy1_clk.common.hw, + [CLK_EDP_TV] =3D &edp_tv_clk.common.hw, + [CLK_HDMI_CEC_32K] =3D &hdmi_cec_32k_clk.common.hw, + [CLK_HDMI_CEC] =3D &hdmi_cec_clk.common.hw, + [CLK_HDMI_TV] =3D &hdmi_tv_clk.common.hw, + [CLK_HDMI_SFR] =3D &hdmi_sfr_clk.common.hw, + [CLK_HDMI_ESM] =3D &hdmi_esm_clk.common.hw, + [CLK_LEDC] =3D &ledc_clk.common.hw, + [CLK_CSI_MASTER0] =3D &csi_master0_clk.common.hw, + [CLK_CSI_MASTER1] =3D &csi_master1_clk.common.hw, + [CLK_CSI_MASTER2] =3D &csi_master2_clk.common.hw, + [CLK_CSI] =3D &csi_clk.common.hw, + [CLK_ISP] =3D &isp_clk.common.hw, + [CLK_APB2JTAG] =3D &apb2jtag_clk.common.hw, + [CLK_FANOUT_24M] =3D &fanout_24M_clk.common.hw, + [CLK_FANOUT_12M] =3D &fanout_12M_clk.common.hw, + [CLK_FANOUT_16M] =3D &fanout_16M_clk.common.hw, + [CLK_FANOUT_25M] =3D &fanout_25M_clk.common.hw, + [CLK_FANOUT_27M] =3D &fanout_27M_clk.common.hw, + [CLK_FANOUT_PCLK] =3D &fanout_pclk_clk.common.hw, + [CLK_FANOUT0] =3D &fanout0_clk.common.hw, + [CLK_FANOUT1] =3D &fanout1_clk.common.hw, + [CLK_FANOUT2] =3D &fanout2_clk.common.hw, + [CLK_FANOUT3] =3D &fanout3_clk.common.hw, }, .num =3D CLK_FANOUT3 + 1, }; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260310-a733-clk-v1-7-36b4e9b24457@pigmoral.tech> References: <20260310-a733-clk-v1-0-36b4e9b24457@pigmoral.tech> In-Reply-To: <20260310-a733-clk-v1-0-36b4e9b24457@pigmoral.tech> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773132092; l=39976; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=B5PUX9xqRU8sud9G1NNdl0cx6pTO3OY4ybqJDNFVk0U=; b=k67cz339oHDW9BWfJ+Y+0Y12rON57/yXolFlQuJ3qbYqyeSm+IuR1/hiU78+Ry+aiyqfclo0M zWTf8IgJjGoBsVGgrOPjKyBPXMVwvM71HSkfPi0v4Z1x+qJ7xCNTep/ X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External Add the bus clock gates that control access to the devices' register interface on the Allwinner A733 SoC. These clocks are typically single-bit controls in the BGR registers, covering UARTs, SPI, I2C, and various multimedia engines. It also includes bus gates for system components like the IOMMU and MSI-lite interfaces. Signed-off-by: Junhui Liu --- The parents of some bus clocks are difficult to determine, as the user manual only describes the clock source for a few instances. The current configurations are based on references to previous Allwinner SoCs and information gathered from the manual. Where documentation is lacking, vendor practices are followed by setting the parent to "hosc" for now. --- drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 475 +++++++++++++++++++++++++++++= +++- 1 file changed, 474 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c b/drivers/clk/sunxi-ng/= ccu-sun60i-a733.c index 36b44568a56f..c0b09f9197d1 100644 --- a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c @@ -408,16 +408,19 @@ static SUNXI_CCU_M_DATA_WITH_MUX(ahb_clk, "ahb", ahb_= apb_parents, 0x500, 0, 5, /* M */ 24, 2, /* mux */ 0); +static const struct clk_hw *ahb_hws[] =3D { &ahb_clk.common.hw }; =20 static SUNXI_CCU_M_DATA_WITH_MUX(apb0_clk, "apb0", ahb_apb_parents, 0x510, 0, 5, /* M */ 24, 2, /* mux */ 0); +static const struct clk_hw *apb0_hws[] =3D { &apb0_clk.common.hw }; =20 static SUNXI_CCU_M_DATA_WITH_MUX(apb1_clk, "apb1", ahb_apb_parents, 0x518, 0, 5, /* M */ 24, 2, /* mux */ 0); +static const struct clk_hw *apb1_hws[] =3D { &apb1_clk.common.hw }; =20 static const struct clk_parent_data apb_uart_parents[] =3D { { .hw =3D &sys_24M_clk.hw }, @@ -430,6 +433,9 @@ static SUNXI_CCU_M_DATA_WITH_MUX(apb_uart_clk, "apb-uar= t", apb_uart_parents, 0x5 0, 5, /* M */ 24, 3, /* mux */ 0); +static const struct clk_hw *apb_uart_hws[] =3D { + &apb_uart_clk.common.hw +}; =20 static const struct clk_parent_data trace_parents[] =3D { { .hw =3D &sys_24M_clk.hw }, @@ -463,6 +469,8 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(cpu_peri_clk, "cp= u-peri", gic_cpu_peri_par BIT(31), /* gate */ 0); =20 +static SUNXI_CCU_GATE_DATA(bus_its_pcie_clk, "bus-its-pcie", hosc, 0x574, = BIT(1), 0); + static const struct clk_parent_data nsi_parents[] =3D { { .hw =3D &sys_24M_clk.hw }, { .hw =3D &pll_ddr_clk.common.hw }, @@ -477,6 +485,7 @@ static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(nsi_clk, "n= si", nsi_parents, 0x580, 24, 3, /* mux */ BIT(31), /* gate */ 0, CCU_FEATURE_UPDATE_BIT); +static SUNXI_CCU_GATE_DATA(bus_nsi_clk, "bus-nsi", hosc, 0x584, BIT(0), 0); =20 static const struct clk_parent_data mbus_parents[] =3D { { .hw =3D &sys_24M_clk.hw }, @@ -493,9 +502,117 @@ static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(mbus_clk,= "mbus", mbus_parents, 0x58 BIT(31), /* gate */ CLK_IS_CRITICAL, CCU_FEATURE_UPDATE_BIT); +static const struct clk_hw *mbus_hws[] =3D { &mbus_clk.common.hw }; + +static SUNXI_CCU_GATE_HWS(mbus_iommu0_sys_clk, "mbus-iommu0-sys", mbus_hws= , 0x58c, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(apb_iommu0_sys_clk, "apb-iommu0-sys", apb0_hws, = 0x58c, BIT(1), 0); +static SUNXI_CCU_GATE_HWS(ahb_iommu0_sys_clk, "ahb-iommu0-sys", ahb_hws, 0= x58c, BIT(2), 0); + +static SUNXI_CCU_GATE_DATA(bus_msi_lite0_clk, "bus-msi-lite0", hosc, 0x594= , BIT(0), 0); +static SUNXI_CCU_GATE_DATA(bus_msi_lite1_clk, "bus-msi-lite1", hosc, 0x59c= , BIT(0), 0); +static SUNXI_CCU_GATE_DATA(bus_msi_lite2_clk, "bus-msi-lite2", hosc, 0x5a4= , BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(mbus_iommu1_sys_clk, "mbus-iommu1-sys", mbus_hws= , 0x5b4, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(apb_iommu1_sys_clk, "apb_iommu1-sys", apb0_hws, = 0x5b4, BIT(1), 0); +static SUNXI_CCU_GATE_HWS(ahb_iommu1_sys_clk, "ahb_iommu1-sys", ahb_hws, 0= x5b4, BIT(2), 0); + +static SUNXI_CCU_GATE_HWS(ahb_ve_dec_clk, "ahb-ve-dec", ahb_hws, + 0x5c0, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(ahb_ve_enc_clk, "ahb-ve-enc", ahb_hws, + 0x5c0, BIT(1), 0); +static SUNXI_CCU_GATE_HWS(ahb_vid_in_clk, "ahb-vid-in", ahb_hws, + 0x5c0, BIT(2), 0); +static SUNXI_CCU_GATE_HWS(ahb_vid_cout0_clk, "ahb-vid-cout0", ahb_hws, + 0x5c0, BIT(3), 0); +static SUNXI_CCU_GATE_HWS(ahb_vid_cout1_clk, "ahb-vid-cout1", ahb_hws, + 0x5c0, BIT(4), 0); +static SUNXI_CCU_GATE_HWS(ahb_de_clk, "ahb-de", ahb_hws, + 0x5c0, BIT(5), 0); +static SUNXI_CCU_GATE_HWS(ahb_npu_clk, "ahb-npu", ahb_hws, + 0x5c0, BIT(6), 0); +static SUNXI_CCU_GATE_HWS(ahb_gpu0_clk, "ahb-gpu0", ahb_hws, + 0x5c0, BIT(7), 0); +static SUNXI_CCU_GATE_HWS(ahb_serdes_clk, "ahb-serdes", ahb_hws, + 0x5c0, BIT(8), 0); +static SUNXI_CCU_GATE_HWS(ahb_usb_sys_clk, "ahb-usb-sys", ahb_hws, + 0x5c0, BIT(9), 0); +static SUNXI_CCU_GATE_HWS(ahb_msi_lite0_clk, "ahb-msi-lite0", ahb_hws, + 0x5c0, BIT(16), 0); +static SUNXI_CCU_GATE_HWS(ahb_store_clk, "ahb-store", ahb_hws, + 0x5c0, BIT(24), 0); +static SUNXI_CCU_GATE_HWS(ahb_cpus_clk, "ahb-cpus", ahb_hws, + 0x5c0, BIT(28), 0); + +static SUNXI_CCU_GATE_HWS(mbus_iommu0_clk, "mbus-iommu0", mbus_hws, + 0x5e0, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(mbus_iommu1_clk, "mbus-iommu1", mbus_hws, + 0x5e0, BIT(1), 0); +static SUNXI_CCU_GATE_HWS(mbus_desys_clk, "mbus-desys", mbus_hws, + 0x5e0, BIT(11), 0); +static SUNXI_CCU_GATE_HWS(mbus_ve_enc_gate_clk, "mbus-ve-enc-gate", mbus_h= ws, + 0x5e0, BIT(12), 0); +static SUNXI_CCU_GATE_HWS(mbus_ve_dec_gate_clk, "mbus-ve-dec-gate", mbus_h= ws, + 0x5e0, BIT(14), 0); +static SUNXI_CCU_GATE_HWS(mbus_gpu0_clk, "mbus-gpu0", mbus_hws, + 0x5e0, BIT(16), 0); +static SUNXI_CCU_GATE_HWS(mbus_npu_clk, "mbus-npu", mbus_hws, + 0x5e0, BIT(18), 0); +static SUNXI_CCU_GATE_HWS(mbus_vid_in_clk, "mbus-vid-in", mbus_hws, + 0x5e0, BIT(24), 0); +static SUNXI_CCU_GATE_HWS(mbus_serdes_clk, "mbus-serdes", mbus_hws, + 0x5e0, BIT(28), 0); +static SUNXI_CCU_GATE_HWS(mbus_msi_lite0_clk, "mbus-msi-lite0", mbus_hws, + 0x5e0, BIT(29), 0); +static SUNXI_CCU_GATE_HWS(mbus_store_clk, "mbus-store", mbus_hws, + 0x5e0, BIT(30), 0); +static SUNXI_CCU_GATE_HWS(mbus_msi_lite2_clk, "mbus-msi-lite2", mbus_hws, + 0x5e0, BIT(31), 0); + +static SUNXI_CCU_GATE_HWS(mbus_dma0_clk, "mbus-dma0", mbus_hws, + 0x5e4, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(mbus_ve_enc_clk, "mbus-ve-enc", mbus_hws, + 0x5e4, BIT(1), 0); +static SUNXI_CCU_GATE_HWS(mbus_ce_clk, "mbus-ce", mbus_hws, + 0x5e4, BIT(2), 0); +static SUNXI_CCU_GATE_HWS(mbus_dma1_clk, "mbus-dma1", mbus_hws, + 0x5e4, BIT(3), 0); +static SUNXI_CCU_GATE_HWS(mbus_nand_clk, "mbus-nand", mbus_hws, + 0x5e4, BIT(5), 0); +static SUNXI_CCU_GATE_HWS(mbus_csi_clk, "mbus-csi", mbus_hws, + 0x5e4, BIT(8), 0); +static SUNXI_CCU_GATE_HWS(mbus_isp_clk, "mbus-isp", mbus_hws, + 0x5e4, BIT(9), 0); +static SUNXI_CCU_GATE_HWS(mbus_gmac0_clk, "mbus-gmac0", mbus_hws, + 0x5e4, BIT(11), 0); +static SUNXI_CCU_GATE_HWS(mbus_gmac1_clk, "mbus-gmac1", mbus_hws, + 0x5e4, BIT(12), 0); +static SUNXI_CCU_GATE_HWS(mbus_ve_dec_clk, "mbus-ve-dec", mbus_hws, + 0x5e4, BIT(18), 0); + +static SUNXI_CCU_GATE_HWS(bus_dma0_clk, "bus-dma0", ahb_hws, + 0x704, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_dma1_clk, "bus-dma1", ahb_hws, + 0x70c, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_spinlock_clk, "bus-spinlock", ahb_hws, + 0x724, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_msgbox_clk, "bus-msgbox", ahb_hws, + 0x744, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_pwm0_clk, "bus-pwm0", apb0_hws, + 0x784, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_pwm1_clk, "bus-pwm1", apb0_hws, + 0x78c, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_dbg_clk, "bus-dbg", sys_24M_hws, + 0x7a4, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_sysdap_clk, "bus-sysdap", apb1_hws, + 0x88c, BIT(0), 0); =20 /************************************************************************** - * mod clocks * + * mod clocks with gates * *************************************************************************= */ =20 static const struct clk_parent_data timer_parents[] =3D { @@ -565,6 +682,7 @@ static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer9_clk, "tim= er9", timer_parents, 0x82 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_timer_clk, "bus-timer", ahb_hws, 0x850, BIT(= 0), 0); =20 static const struct clk_parent_data avs_parents[] =3D { { .hw =3D &sys_24M_clk.hw }, @@ -589,6 +707,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(de_clk, "de", de_pa= rents, 0xa00, 24, 3, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); +static SUNXI_CCU_GATE_HWS(bus_de_clk, "bus-de", ahb_hws, 0xa04, BIT(0), 0); =20 static const struct clk_hw *di_parents[] =3D { &pll_periph0_600M_clk.hw, @@ -602,6 +721,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(di_clk, "di", di_pa= rents, 0xa20, 24, 3, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); +static SUNXI_CCU_GATE_HWS(bus_di_clk, "bus-di", ahb_hws, 0xa24, BIT(0), 0); =20 static const struct clk_hw *g2d_parents[] =3D { &pll_periph0_400M_clk.hw, @@ -614,6 +734,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(g2d_clk, "g2d", g2d= _parents, 0xa40, 24, 3, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); +static SUNXI_CCU_GATE_HWS(bus_g2d_clk, "bus-g2d", ahb_hws, 0xa44, BIT(0), = 0); =20 static const struct clk_hw *eink_parents[] =3D { &pll_periph0_480M_clk.common.hw, @@ -637,6 +758,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(eink_panel_clk, "ei= nk-panel", eink_panel_par 24, 3, /* mux */ BIT(31), /* gate */ CLK_SET_RATE_PARENT); +static SUNXI_CCU_GATE_HWS(bus_eink_clk, "bus-eink", ahb_hws, 0xa6c, BIT(0)= , 0); =20 static const struct clk_hw *ve_enc_parents[] =3D { &pll_ve0_clk.common.hw, @@ -668,6 +790,9 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_dec_clk, "ve-dec= ", ve_dec_parents, 0xa88, BIT(31), /* gate */ CLK_SET_RATE_PARENT); =20 +static SUNXI_CCU_GATE_HWS(bus_ve_enc_clk, "bus-ve-enc", ahb_hws, 0xa8c, BI= T(0), 0); +static SUNXI_CCU_GATE_HWS(bus_ve_dec_clk, "bus-ve-dec", ahb_hws, 0xa8c, BI= T(2), 0); + static const struct clk_hw *ce_parents[] =3D { &sys_24M_clk.hw, &pll_periph0_400M_clk.hw, @@ -678,6 +803,8 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(ce_clk, "ce", ce_pa= rents, 0xac0, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_ce_clk, "bus-ce", ahb_hws, 0xac4, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_ce_sys_clk, "bus-ce-sys", ahb_hws, 0xac4, BI= T(1), 0); =20 static const struct clk_hw *npu_parents[] =3D { &pll_npu_clk.common.hw, @@ -693,6 +820,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(npu_clk, "npu", npu= _parents, 0xb00, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_DATA(bus_npu_clk, "bus-npu", hosc, 0xb04, BIT(0), 0); =20 /* * GPU_CLK =3D ClockSource * ((16 - M) / 16) @@ -725,6 +853,7 @@ static struct ccu_div gpu_clk =3D { &ccu_div_ops, 0), } }; +static SUNXI_CCU_GATE_HWS(bus_gpu_clk, "bus-gpu", ahb_hws, 0xb24, BIT(0), = 0); =20 static const struct clk_parent_data dram_parents[] =3D { { .hw =3D &pll_ddr_clk.common.hw, }, @@ -740,6 +869,7 @@ static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(dram_clk, "= dram", dram_parents, 0xc0 BIT(31), /* gate */ CLK_IS_CRITICAL, CCU_FEATURE_UPDATE_BIT); +static SUNXI_CCU_GATE_HWS(bus_dram_clk, "bus-dram", ahb_hws, 0xc0c, BIT(0)= , 0); =20 static const struct clk_parent_data nand_mmc_parents[] =3D { { .hw =3D &sys_24M_clk.hw, }, @@ -758,6 +888,7 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(nand1_clk, "nand1= ", nand_mmc_parents, 0xc8 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_nand_clk, "bus-nand", ahb_hws, 0xc8c, BIT(0)= , 0); =20 static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc0_clk, "mmc0", nand_mmc_pa= rents, 0xd00, 0, 5, /* M */ @@ -796,6 +927,11 @@ static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc3_clk,= "mmc3", mmc2_mmc3_parents 2, /* post div */ 0); =20 +static SUNXI_CCU_GATE_HWS(bus_mmc0_clk, "bus-mmc0", ahb_hws, 0xd0c, BIT(0)= , 0); +static SUNXI_CCU_GATE_HWS(bus_mmc1_clk, "bus-mmc1", ahb_hws, 0xd1c, BIT(0)= , 0); +static SUNXI_CCU_GATE_HWS(bus_mmc2_clk, "bus-mmc2", ahb_hws, 0xd2c, BIT(0)= , 0); +static SUNXI_CCU_GATE_HWS(bus_mmc3_clk, "bus-mmc3", ahb_hws, 0xd3c, BIT(0)= , 0); + static const struct clk_hw *ufs_axi_parents[] =3D { &pll_periph0_300M_clk.hw, &pll_periph0_200M_clk.hw, @@ -815,6 +951,29 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ufs_cfg_clk, "uf= s-cfg", ufs_cfg_parents, 0 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_DATA(bus_ufs_clk, "bus-ufs", hosc, 0xd8c, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_uart0_clk, "bus-uart0", apb_uart_hws, 0xe00,= BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_uart1_clk, "bus-uart1", apb_uart_hws, 0xe04,= BIT(1), 0); +static SUNXI_CCU_GATE_HWS(bus_uart2_clk, "bus-uart2", apb_uart_hws, 0xe08,= BIT(2), 0); +static SUNXI_CCU_GATE_HWS(bus_uart3_clk, "bus-uart3", apb_uart_hws, 0xe0c,= BIT(3), 0); +static SUNXI_CCU_GATE_HWS(bus_uart4_clk, "bus-uart4", apb_uart_hws, 0xe10,= BIT(4), 0); +static SUNXI_CCU_GATE_HWS(bus_uart5_clk, "bus-uart5", apb_uart_hws, 0xe14,= BIT(5), 0); +static SUNXI_CCU_GATE_HWS(bus_uart6_clk, "bus-uart6", apb_uart_hws, 0xe18,= BIT(6), 0); + +static SUNXI_CCU_GATE_HWS(bus_i2c0_clk, "bus-i2c0", apb1_hws, 0xe80, BIT(0= ), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c1_clk, "bus-i2c1", apb1_hws, 0xe84, BIT(0= ), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c2_clk, "bus-i2c2", apb1_hws, 0xe88, BIT(0= ), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c3_clk, "bus-i2c3", apb1_hws, 0xe8c, BIT(0= ), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c4_clk, "bus-i2c4", apb1_hws, 0xe90, BIT(0= ), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c5_clk, "bus-i2c5", apb1_hws, 0xe94, BIT(0= ), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c6_clk, "bus-i2c6", apb1_hws, 0xe98, BIT(0= ), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c7_clk, "bus-i2c7", apb1_hws, 0xe9c, BIT(0= ), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c8_clk, "bus-i2c8", apb1_hws, 0xea0, BIT(0= ), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c9_clk, "bus-i2c9", apb1_hws, 0xea4, BIT(0= ), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c10_clk, "bus-i2c10", apb1_hws, 0xea8, BIT= (0), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c11_clk, "bus-i2c11", apb1_hws, 0xeac, BIT= (0), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c12_clk, "bus-i2c12", apb1_hws, 0xeb0, BIT= (0), 0); =20 static const struct clk_parent_data spi_parents[] =3D { { .hw =3D &sys_24M_clk.hw }, @@ -856,6 +1015,11 @@ static SUNXI_CCU_DUALDIV_MUX_GATE(spi4_clk, "spi4", s= pi_parents, 0xf28, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_spi0_clk, "bus-spi0", ahb_hws, 0xf04, BIT(0)= , 0); +static SUNXI_CCU_GATE_HWS(bus_spi1_clk, "bus-spi1", ahb_hws, 0xf0c, BIT(0)= , 0); +static SUNXI_CCU_GATE_HWS(bus_spi2_clk, "bus-spi2", ahb_hws, 0xf14, BIT(0)= , 0); +static SUNXI_CCU_GATE_HWS(bus_spi3_clk, "bus-spi3", ahb_hws, 0xf24, BIT(0)= , 0); +static SUNXI_CCU_GATE_HWS(bus_spi4_clk, "bus-spi4", ahb_hws, 0xf2c, BIT(0)= , 0); =20 static const struct clk_parent_data spif_parents[] =3D { { .hw =3D &sys_24M_clk.hw }, @@ -873,6 +1037,7 @@ static SUNXI_CCU_DUALDIV_MUX_GATE(spif_clk, "spif", sp= if_parents, 0xf18, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_spif_clk, "bus-spif", ahb_hws, 0xf1c, BIT(0)= , 0); =20 static const struct clk_parent_data gpadc_parents[] =3D { { .hw =3D &sys_24M_clk.hw }, @@ -883,6 +1048,9 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(gpadc_clk, "gpad= c", gpadc_parents, 0xfc0, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_gpadc_clk, "bus-gpadc", ahb_hws, 0xfc4, BIT(= 0), 0); + +static SUNXI_CCU_GATE_HWS(bus_ths_clk, "bus-ths", apb0_hws, 0xfe4, BIT(0),= 0); =20 static const struct clk_parent_data irrx_parents[] =3D { { .fw_name =3D "losc"}, @@ -894,6 +1062,7 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(irrx_clk, "irrx"= , irrx_parents, 0x1000, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_irrx_clk, "bus-irrx", apb0_hws, 0x1004, BIT(= 0), 0); =20 static const struct clk_parent_data irtx_parents[] =3D { { .fw_name =3D "losc"}, @@ -905,6 +1074,9 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(irtx_clk, "irtx"= , irtx_parents, 0x1008, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_irtx_clk, "bus-irtx", apb0_hws, 0x100c, BIT(= 0), 0); + +static SUNXI_CCU_GATE_HWS(bus_lradc_clk, "bus-lradc", apb0_hws, 0x1024, BI= T(0), 0); =20 static const struct clk_parent_data sgpio_parents[] =3D { { .fw_name =3D "losc"}, @@ -915,6 +1087,7 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(sgpio_clk, "sgpi= o", sgpio_parents, 0x1060, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_DATA(bus_sgpio_clk, "bus-sgpio", hosc, 0x1064, BIT(0= ), 0); =20 static const struct clk_hw *lpc_parents[] =3D { &pll_video0_3x_clk.common.hw, @@ -927,6 +1100,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(lpc_clk, "lpc", lp= c_parents, 0x1080, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_DATA(bus_lpc_clk, "bus-lpc", hosc, 0x1084, BIT(0), 0= ); =20 static const struct clk_hw *i2spcm_parents[] =3D { &pll_audio0_4x_clk.common.hw, @@ -959,6 +1133,11 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm4_clk, "i2s= pcm4", i2spcm_parents, 0x12 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_DATA(bus_i2spcm0_clk, "bus-i2spcm0", hosc, 0x120c, B= IT(0), 0); +static SUNXI_CCU_GATE_DATA(bus_i2spcm1_clk, "bus-i2spcm1", hosc, 0x121c, B= IT(0), 0); +static SUNXI_CCU_GATE_DATA(bus_i2spcm2_clk, "bus-i2spcm2", hosc, 0x122c, B= IT(0), 0); +static SUNXI_CCU_GATE_DATA(bus_i2spcm3_clk, "bus-i2spcm3", hosc, 0x123c, B= IT(0), 0); +static SUNXI_CCU_GATE_DATA(bus_i2spcm4_clk, "bus-i2spcm4", hosc, 0x124c, B= IT(0), 0); =20 static const struct clk_hw *i2spcm2_asrc_parents[] =3D { &pll_audio0_4x_clk.common.hw, @@ -995,6 +1174,8 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(owa_rx_clk, "owa_r= x", owa_rx_parents, 0x1284 BIT(31), /* gate */ 0); =20 +static SUNXI_CCU_GATE_HWS(bus_owa_clk, "bus-owa", apb1_hws, 0x128c, BIT(0)= , 0); + static const struct clk_hw *dmic_parents[] =3D { &pll_audio0_4x_clk.common.hw, &pll_audio1_div2_clk.common.hw, @@ -1006,6 +1187,8 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(dmic_clk, "dmic",= dmic_parents, 0x12c0, BIT(31), /* gate */ 0); =20 +static SUNXI_CCU_GATE_HWS(bus_dmic_clk, "bus-dmic", apb1_hws, 0x12cc, BIT(= 0), 0); + /* * The first parent is a 48 MHz input clock divided by 4. That 48 MHz cloc= k is * a 2x multiplier from pll-ref synchronized by pll-periph0, and is also u= sed by @@ -1037,6 +1220,9 @@ static struct ccu_mux usb_ohci0_clk =3D { &ccu_mux_ops, 0), }, }; +static SUNXI_CCU_GATE_HWS(bus_ohci0_clk, "bus-ohci0", ahb_hws, 0x1304, BIT= (0), 0); +static SUNXI_CCU_GATE_HWS(bus_ehci0_clk, "bus-ehci0", ahb_hws, 0x1304, BIT= (4), 0); +static SUNXI_CCU_GATE_HWS(bus_otg_clk, "bus-otg", ahb_hws, 0x1304, BIT(8),= 0); =20 static struct ccu_mux usb_ohci1_clk =3D { .enable =3D BIT(31), @@ -1053,6 +1239,8 @@ static struct ccu_mux usb_ohci1_clk =3D { &ccu_mux_ops, 0), }, }; +static SUNXI_CCU_GATE_HWS(bus_ohci1_clk, "bus-ohci1", ahb_hws, 0x130c, BIT= (0), 0); +static SUNXI_CCU_GATE_HWS(bus_ehci1_clk, "bus-ehci1", ahb_hws, 0x130c, BIT= (4), 0); =20 static const struct clk_parent_data usb_ref_parents[] =3D { { .hw =3D &sys_24M_clk.hw }, @@ -1159,6 +1347,8 @@ static SUNXI_CCU_M_HWS_WITH_GATE(gmac1_phy_clk, "gmac= 1-phy", pll_periph0_150M_hw 0, 5, /* M */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_gmac0_clk, "bus-gmac0", ahb_hws, 0x141c, BIT= (0), 0); +static SUNXI_CCU_GATE_HWS(bus_gmac1_clk, "bus-gmac1", ahb_hws, 0x142c, BIT= (0), 0); =20 static const struct clk_hw *tcon_lcd_parents[] =3D { &pll_video0_4x_clk.common.hw, @@ -1181,6 +1371,9 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd2_clk, "t= con-lcd2", tcon_lcd_parents 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_tcon_lcd0_clk, "bus-tcon-lcd0", ahb_hws, 0x1= 504, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_tcon_lcd1_clk, "bus-tcon-lcd1", ahb_hws, 0x1= 50c, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_tcon_lcd2_clk, "bus-tcon-lcd2", ahb_hws, 0x1= 514, BIT(0), 0); =20 static const struct clk_hw *dsi_parents[] =3D { &sys_24M_clk.hw, @@ -1197,6 +1390,8 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(dsi1_clk, "dsi1",= dsi_parents, 0x1588, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_dsi0_clk, "bus-dsi0", ahb_hws, 0x1584, BIT(0= ), 0); +static SUNXI_CCU_GATE_HWS(bus_dsi1_clk, "bus-dsi1", ahb_hws, 0x158c, BIT(0= ), 0); =20 static const struct clk_hw *combphy_parents[] =3D { &pll_video0_4x_clk.common.hw, @@ -1216,6 +1411,9 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(combphy1_clk, "co= mbphy1", combphy_parents, 0 BIT(31), /* gate */ 0); =20 +static SUNXI_CCU_GATE_HWS(bus_tcon_tv0_clk, "bus-tcon-tv0", ahb_hws, 0x160= 4, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_tcon_tv1_clk, "bus-tcon-tv1", ahb_hws, 0x160= c, BIT(0), 0); + static const struct clk_hw *edp_tv_parents[] =3D { &pll_video0_4x_clk.common.hw, &pll_video1_4x_clk.common.hw, @@ -1227,6 +1425,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(edp_tv_clk, "edp-= tv", edp_tv_parents, 0x1640 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_edp_tv_clk, "bus-edp-tv", ahb_hws, 0x164c, B= IT(0), 0); =20 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(hdmi_cec_32k_clk, "hdmi-cec-32k", pl= l_periph0_2x_hws, 0x1680, BIT(30), /* gate */ @@ -1254,6 +1453,7 @@ static SUNXI_CCU_DUALDIV_MUX_GATE(hdmi_tv_clk, "hdmi-= tv", hdmi_tv_parents, 0x168 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_hdmi_tv_clk, "bus-hdmi-tv", ahb_hws, 0x168c,= BIT(0), 0); =20 static const struct clk_parent_data hdmi_sfr_parents[] =3D { { .hw =3D &sys_24M_clk.hw }, @@ -1266,6 +1466,9 @@ static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_sfr_clk, "hd= mi-sfr", hdmi_sfr_parents, =20 static SUNXI_CCU_GATE_HWS(hdmi_esm_clk, "hdmi-esm", pll_periph0_300M_hws, = 0x1694, BIT(31), 0); =20 +static SUNXI_CCU_GATE_HWS(bus_dpss_top0_clk, "bus-dpss-top0", ahb_hws, 0x1= 6c4, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_dpss_top1_clk, "bus-dpss-top1", ahb_hws, 0x1= 6cc, BIT(0), 0); + static const struct clk_parent_data ledc_parents[] =3D { { .hw =3D &sys_24M_clk.hw }, { .hw =3D &pll_periph0_600M_clk.hw }, @@ -1276,6 +1479,9 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ledc_clk, "ledc= ", ledc_parents, 0x1700, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_ledc_clk, "bus-ledc", apb0_hws, 0x1704, BIT(= 0), 0); + +static SUNXI_CCU_GATE_HWS(bus_dsc_clk, "bus-dsc", ahb_hws, 0x1744, BIT(0),= 0); =20 static const struct clk_parent_data csi_master_parents[] =3D { { .hw =3D &sys_24M_clk.hw }, @@ -1317,6 +1523,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_clk, "csi", c= si_parents, 0x1840, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_csi_clk, "bus-csi", ahb_hws, 0x1844, BIT(0),= 0); =20 static const struct clk_hw *isp_parents[] =3D { &pll_video2_4x_clk.common.hw, @@ -1446,8 +1653,62 @@ static struct ccu_common *sun60i_a733_ccu_clks[] =3D= { &trace_clk.common, &gic_clk.common, &cpu_peri_clk.common, + &bus_its_pcie_clk.common, &nsi_clk.common, + &bus_nsi_clk.common, &mbus_clk.common, + &mbus_iommu0_sys_clk.common, + &apb_iommu0_sys_clk.common, + &ahb_iommu0_sys_clk.common, + &bus_msi_lite0_clk.common, + &bus_msi_lite1_clk.common, + &bus_msi_lite2_clk.common, + &mbus_iommu1_sys_clk.common, + &apb_iommu1_sys_clk.common, + &ahb_iommu1_sys_clk.common, + &ahb_ve_dec_clk.common, + &ahb_ve_enc_clk.common, + &ahb_vid_in_clk.common, + &ahb_vid_cout0_clk.common, + &ahb_vid_cout1_clk.common, + &ahb_de_clk.common, + &ahb_npu_clk.common, + &ahb_gpu0_clk.common, + &ahb_serdes_clk.common, + &ahb_usb_sys_clk.common, + &ahb_msi_lite0_clk.common, + &ahb_store_clk.common, + &ahb_cpus_clk.common, + &mbus_iommu0_clk.common, + &mbus_iommu1_clk.common, + &mbus_desys_clk.common, + &mbus_ve_enc_gate_clk.common, + &mbus_ve_dec_gate_clk.common, + &mbus_gpu0_clk.common, + &mbus_npu_clk.common, + &mbus_vid_in_clk.common, + &mbus_serdes_clk.common, + &mbus_msi_lite0_clk.common, + &mbus_store_clk.common, + &mbus_msi_lite2_clk.common, + &mbus_dma0_clk.common, + &mbus_ve_enc_clk.common, + &mbus_ce_clk.common, + &mbus_dma1_clk.common, + &mbus_nand_clk.common, + &mbus_csi_clk.common, + &mbus_isp_clk.common, + &mbus_gmac0_clk.common, + &mbus_gmac1_clk.common, + &mbus_ve_dec_clk.common, + &bus_dma0_clk.common, + &bus_dma1_clk.common, + &bus_spinlock_clk.common, + &bus_msgbox_clk.common, + &bus_pwm0_clk.common, + &bus_pwm1_clk.common, + &bus_dbg_clk.common, + &bus_sysdap_clk.common, &timer0_clk.common, &timer1_clk.common, &timer2_clk.common, @@ -1458,48 +1719,111 @@ static struct ccu_common *sun60i_a733_ccu_clks[] = =3D { &timer7_clk.common, &timer8_clk.common, &timer9_clk.common, + &bus_timer_clk.common, &avs_clk.common, &de_clk.common, + &bus_de_clk.common, &di_clk.common, + &bus_di_clk.common, &g2d_clk.common, + &bus_g2d_clk.common, &eink_clk.common, &eink_panel_clk.common, + &bus_eink_clk.common, &ve_enc_clk.common, &ve_dec_clk.common, + &bus_ve_enc_clk.common, + &bus_ve_dec_clk.common, &ce_clk.common, + &bus_ce_clk.common, + &bus_ce_sys_clk.common, &npu_clk.common, + &bus_npu_clk.common, &gpu_clk.common, + &bus_gpu_clk.common, &dram_clk.common, + &bus_dram_clk.common, &nand0_clk.common, &nand1_clk.common, + &bus_nand_clk.common, &mmc0_clk.common, &mmc1_clk.common, &mmc2_clk.common, &mmc3_clk.common, + &bus_mmc0_clk.common, + &bus_mmc1_clk.common, + &bus_mmc2_clk.common, + &bus_mmc3_clk.common, &ufs_axi_clk.common, &ufs_cfg_clk.common, + &bus_ufs_clk.common, + &bus_uart0_clk.common, + &bus_uart1_clk.common, + &bus_uart2_clk.common, + &bus_uart3_clk.common, + &bus_uart4_clk.common, + &bus_uart5_clk.common, + &bus_uart6_clk.common, + &bus_i2c0_clk.common, + &bus_i2c1_clk.common, + &bus_i2c2_clk.common, + &bus_i2c3_clk.common, + &bus_i2c4_clk.common, + &bus_i2c5_clk.common, + &bus_i2c6_clk.common, + &bus_i2c7_clk.common, + &bus_i2c8_clk.common, + &bus_i2c9_clk.common, + &bus_i2c10_clk.common, + &bus_i2c11_clk.common, + &bus_i2c12_clk.common, &spi0_clk.common, &spi1_clk.common, &spi2_clk.common, &spi3_clk.common, &spi4_clk.common, + &bus_spi0_clk.common, + &bus_spi1_clk.common, + &bus_spi2_clk.common, + &bus_spi3_clk.common, + &bus_spi4_clk.common, &spif_clk.common, + &bus_spif_clk.common, &gpadc_clk.common, + &bus_gpadc_clk.common, + &bus_ths_clk.common, &irrx_clk.common, + &bus_irrx_clk.common, &irtx_clk.common, + &bus_irtx_clk.common, + &bus_lradc_clk.common, &sgpio_clk.common, + &bus_sgpio_clk.common, &lpc_clk.common, + &bus_lpc_clk.common, &i2spcm0_clk.common, &i2spcm1_clk.common, &i2spcm2_clk.common, &i2spcm3_clk.common, &i2spcm4_clk.common, + &bus_i2spcm0_clk.common, + &bus_i2spcm1_clk.common, + &bus_i2spcm2_clk.common, + &bus_i2spcm3_clk.common, + &bus_i2spcm4_clk.common, &i2spcm2_asrc_clk.common, &owa_tx_clk.common, &owa_rx_clk.common, + &bus_owa_clk.common, &dmic_clk.common, + &bus_dmic_clk.common, &usb_ohci0_clk.common, + &bus_otg_clk.common, + &bus_ehci0_clk.common, + &bus_ohci0_clk.common, &usb_ohci1_clk.common, + &bus_ehci1_clk.common, + &bus_ohci1_clk.common, &usb_ref_clk.common, &usb2_u2_ref_clk.common, &usb2_suspend_clk.common, @@ -1512,24 +1836,40 @@ static struct ccu_common *sun60i_a733_ccu_clks[] = =3D { &gmac_ptp_clk.common, &gmac0_phy_clk.common, &gmac1_phy_clk.common, + &bus_gmac0_clk.common, + &bus_gmac1_clk.common, &tcon_lcd0_clk.common, &tcon_lcd1_clk.common, &tcon_lcd2_clk.common, + &bus_tcon_lcd0_clk.common, + &bus_tcon_lcd1_clk.common, + &bus_tcon_lcd2_clk.common, &dsi0_clk.common, &dsi1_clk.common, + &bus_dsi0_clk.common, + &bus_dsi1_clk.common, &combphy0_clk.common, &combphy1_clk.common, + &bus_tcon_tv0_clk.common, + &bus_tcon_tv1_clk.common, &edp_tv_clk.common, + &bus_edp_tv_clk.common, &hdmi_cec_32k_clk.common, &hdmi_cec_clk.common, &hdmi_tv_clk.common, + &bus_hdmi_tv_clk.common, &hdmi_sfr_clk.common, &hdmi_esm_clk.common, + &bus_dpss_top0_clk.common, + &bus_dpss_top1_clk.common, &ledc_clk.common, + &bus_ledc_clk.common, + &bus_dsc_clk.common, &csi_master0_clk.common, &csi_master1_clk.common, &csi_master2_clk.common, &csi_clk.common, + &bus_csi_clk.common, &isp_clk.common, &apb2jtag_clk.common, &fanout_24M_clk.common, @@ -1596,8 +1936,62 @@ static struct clk_hw_onecell_data sun60i_a733_hw_clk= s =3D { [CLK_TRACE] =3D &trace_clk.common.hw, [CLK_GIC] =3D &gic_clk.common.hw, [CLK_CPU_PERI] =3D &cpu_peri_clk.common.hw, + [CLK_BUS_ITS_PCIE] =3D &bus_its_pcie_clk.common.hw, [CLK_NSI] =3D &nsi_clk.common.hw, + [CLK_BUS_NSI] =3D &bus_nsi_clk.common.hw, [CLK_MBUS] =3D &mbus_clk.common.hw, + [CLK_MBUS_IOMMU0_SYS] =3D &mbus_iommu0_sys_clk.common.hw, + [CLK_APB_IOMMU0_SYS] =3D &apb_iommu0_sys_clk.common.hw, + [CLK_AHB_IOMMU0_SYS] =3D &ahb_iommu0_sys_clk.common.hw, + [CLK_BUS_MSI_LITE0] =3D &bus_msi_lite0_clk.common.hw, + [CLK_BUS_MSI_LITE1] =3D &bus_msi_lite1_clk.common.hw, + [CLK_BUS_MSI_LITE2] =3D &bus_msi_lite2_clk.common.hw, + [CLK_MBUS_IOMMU1_SYS] =3D &mbus_iommu1_sys_clk.common.hw, + [CLK_APB_IOMMU1_SYS] =3D &apb_iommu1_sys_clk.common.hw, + [CLK_AHB_IOMMU1_SYS] =3D &ahb_iommu1_sys_clk.common.hw, + [CLK_AHB_VE_DEC] =3D &ahb_ve_dec_clk.common.hw, + [CLK_AHB_VE_ENC] =3D &ahb_ve_enc_clk.common.hw, + [CLK_AHB_VID_IN] =3D &ahb_vid_in_clk.common.hw, + [CLK_AHB_VID_COUT0] =3D &ahb_vid_cout0_clk.common.hw, + [CLK_AHB_VID_COUT1] =3D &ahb_vid_cout1_clk.common.hw, + [CLK_AHB_DE] =3D &ahb_de_clk.common.hw, + [CLK_AHB_NPU] =3D &ahb_npu_clk.common.hw, + [CLK_AHB_GPU0] =3D &ahb_gpu0_clk.common.hw, + [CLK_AHB_SERDES] =3D &ahb_serdes_clk.common.hw, + [CLK_AHB_USB_SYS] =3D &ahb_usb_sys_clk.common.hw, + [CLK_AHB_MSI_LITE0] =3D &ahb_msi_lite0_clk.common.hw, + [CLK_AHB_STORE] =3D &ahb_store_clk.common.hw, + [CLK_AHB_CPUS] =3D &ahb_cpus_clk.common.hw, + [CLK_MBUS_IOMMU0] =3D &mbus_iommu0_clk.common.hw, + [CLK_MBUS_IOMMU1] =3D &mbus_iommu1_clk.common.hw, + [CLK_MBUS_DESYS] =3D &mbus_desys_clk.common.hw, + [CLK_MBUS_VE_ENC_GATE] =3D &mbus_ve_enc_gate_clk.common.hw, + [CLK_MBUS_VE_DEC_GATE] =3D &mbus_ve_dec_gate_clk.common.hw, + [CLK_MBUS_GPU0] =3D &mbus_gpu0_clk.common.hw, + [CLK_MBUS_NPU] =3D &mbus_npu_clk.common.hw, + [CLK_MBUS_VID_IN] =3D &mbus_vid_in_clk.common.hw, + [CLK_MBUS_SERDES] =3D &mbus_serdes_clk.common.hw, + [CLK_MBUS_MSI_LITE0] =3D &mbus_msi_lite0_clk.common.hw, + [CLK_MBUS_STORE] =3D &mbus_store_clk.common.hw, + [CLK_MBUS_MSI_LITE2] =3D &mbus_msi_lite2_clk.common.hw, + [CLK_MBUS_DMA0] =3D &mbus_dma0_clk.common.hw, + [CLK_MBUS_VE_ENC] =3D &mbus_ve_enc_clk.common.hw, + [CLK_MBUS_CE] =3D &mbus_ce_clk.common.hw, + [CLK_MBUS_DMA1] =3D &mbus_dma1_clk.common.hw, + [CLK_MBUS_NAND] =3D &mbus_nand_clk.common.hw, + [CLK_MBUS_CSI] =3D &mbus_csi_clk.common.hw, + [CLK_MBUS_ISP] =3D &mbus_isp_clk.common.hw, + [CLK_MBUS_GMAC0] =3D &mbus_gmac0_clk.common.hw, + [CLK_MBUS_GMAC1] =3D &mbus_gmac1_clk.common.hw, + [CLK_MBUS_VE_DEC] =3D &mbus_ve_dec_clk.common.hw, + [CLK_BUS_DMA0] =3D &bus_dma0_clk.common.hw, + [CLK_BUS_DMA1] =3D &bus_dma1_clk.common.hw, + [CLK_BUS_SPINLOCK] =3D &bus_spinlock_clk.common.hw, + [CLK_BUS_MSGBOX] =3D &bus_msgbox_clk.common.hw, + [CLK_BUS_PWM0] =3D &bus_pwm0_clk.common.hw, + [CLK_BUS_PWM1] =3D &bus_pwm1_clk.common.hw, + [CLK_BUS_DBG] =3D &bus_dbg_clk.common.hw, + [CLK_BUS_SYSDAP] =3D &bus_sysdap_clk.common.hw, [CLK_TIMER0] =3D &timer0_clk.common.hw, [CLK_TIMER1] =3D &timer1_clk.common.hw, [CLK_TIMER2] =3D &timer2_clk.common.hw, @@ -1608,48 +2002,111 @@ static struct clk_hw_onecell_data sun60i_a733_hw_c= lks =3D { [CLK_TIMER7] =3D &timer7_clk.common.hw, [CLK_TIMER8] =3D &timer8_clk.common.hw, [CLK_TIMER9] =3D &timer9_clk.common.hw, + [CLK_BUS_TIMER] =3D &bus_timer_clk.common.hw, [CLK_AVS] =3D &avs_clk.common.hw, [CLK_DE] =3D &de_clk.common.hw, + [CLK_BUS_DE] =3D &bus_de_clk.common.hw, [CLK_DI] =3D &di_clk.common.hw, + [CLK_BUS_DI] =3D &bus_di_clk.common.hw, [CLK_G2D] =3D &g2d_clk.common.hw, + [CLK_BUS_G2D] =3D &bus_g2d_clk.common.hw, [CLK_EINK] =3D &eink_clk.common.hw, [CLK_EINK_PANEL] =3D &eink_panel_clk.common.hw, + [CLK_BUS_EINK] =3D &bus_eink_clk.common.hw, [CLK_VE_ENC] =3D &ve_enc_clk.common.hw, [CLK_VE_DEC] =3D &ve_dec_clk.common.hw, + [CLK_BUS_VE_ENC] =3D &bus_ve_enc_clk.common.hw, + [CLK_BUS_VE_DEC] =3D &bus_ve_dec_clk.common.hw, [CLK_CE] =3D &ce_clk.common.hw, + [CLK_BUS_CE] =3D &bus_ce_clk.common.hw, + [CLK_BUS_CE_SYS] =3D &bus_ce_sys_clk.common.hw, [CLK_NPU] =3D &npu_clk.common.hw, + [CLK_BUS_NPU] =3D &bus_npu_clk.common.hw, [CLK_GPU] =3D &gpu_clk.common.hw, + [CLK_BUS_GPU] =3D &bus_gpu_clk.common.hw, [CLK_DRAM] =3D &dram_clk.common.hw, + [CLK_BUS_DRAM] =3D &bus_dram_clk.common.hw, [CLK_NAND0] =3D &nand0_clk.common.hw, [CLK_NAND1] =3D &nand1_clk.common.hw, + [CLK_BUS_NAND] =3D &bus_nand_clk.common.hw, [CLK_MMC0] =3D &mmc0_clk.common.hw, [CLK_MMC1] =3D &mmc1_clk.common.hw, [CLK_MMC2] =3D &mmc2_clk.common.hw, [CLK_MMC3] =3D &mmc3_clk.common.hw, + [CLK_BUS_MMC0] =3D &bus_mmc0_clk.common.hw, + [CLK_BUS_MMC1] =3D &bus_mmc1_clk.common.hw, + [CLK_BUS_MMC2] =3D &bus_mmc2_clk.common.hw, + [CLK_BUS_MMC3] =3D &bus_mmc3_clk.common.hw, [CLK_UFS_AXI] =3D &ufs_axi_clk.common.hw, [CLK_UFS_CFG] =3D &ufs_cfg_clk.common.hw, + [CLK_BUS_UFS] =3D &bus_ufs_clk.common.hw, + [CLK_BUS_UART0] =3D &bus_uart0_clk.common.hw, + [CLK_BUS_UART1] =3D &bus_uart1_clk.common.hw, + [CLK_BUS_UART2] =3D &bus_uart2_clk.common.hw, + [CLK_BUS_UART3] =3D &bus_uart3_clk.common.hw, + [CLK_BUS_UART4] =3D &bus_uart4_clk.common.hw, + [CLK_BUS_UART5] =3D &bus_uart5_clk.common.hw, + [CLK_BUS_UART6] =3D &bus_uart6_clk.common.hw, + [CLK_BUS_I2C0] =3D &bus_i2c0_clk.common.hw, + [CLK_BUS_I2C1] =3D &bus_i2c1_clk.common.hw, + [CLK_BUS_I2C2] =3D &bus_i2c2_clk.common.hw, + [CLK_BUS_I2C3] =3D &bus_i2c3_clk.common.hw, + [CLK_BUS_I2C4] =3D &bus_i2c4_clk.common.hw, + [CLK_BUS_I2C5] =3D &bus_i2c5_clk.common.hw, + [CLK_BUS_I2C6] =3D &bus_i2c6_clk.common.hw, + [CLK_BUS_I2C7] =3D &bus_i2c7_clk.common.hw, + [CLK_BUS_I2C8] =3D &bus_i2c8_clk.common.hw, + [CLK_BUS_I2C9] =3D &bus_i2c9_clk.common.hw, + [CLK_BUS_I2C10] =3D &bus_i2c10_clk.common.hw, + [CLK_BUS_I2C11] =3D &bus_i2c11_clk.common.hw, + [CLK_BUS_I2C12] =3D &bus_i2c12_clk.common.hw, [CLK_SPI0] =3D &spi0_clk.common.hw, [CLK_SPI1] =3D &spi1_clk.common.hw, [CLK_SPI2] =3D &spi2_clk.common.hw, [CLK_SPI3] =3D &spi3_clk.common.hw, [CLK_SPI4] =3D &spi4_clk.common.hw, + [CLK_BUS_SPI0] =3D &bus_spi0_clk.common.hw, + [CLK_BUS_SPI1] =3D &bus_spi1_clk.common.hw, + [CLK_BUS_SPI2] =3D &bus_spi2_clk.common.hw, + [CLK_BUS_SPI3] =3D &bus_spi3_clk.common.hw, + [CLK_BUS_SPI4] =3D &bus_spi4_clk.common.hw, [CLK_SPIF] =3D &spif_clk.common.hw, + [CLK_BUS_SPIF] =3D &bus_spif_clk.common.hw, [CLK_GPADC] =3D &gpadc_clk.common.hw, + [CLK_BUS_GPADC] =3D &bus_gpadc_clk.common.hw, + [CLK_BUS_THS] =3D &bus_ths_clk.common.hw, [CLK_IRRX] =3D &irrx_clk.common.hw, + [CLK_BUS_IRRX] =3D &bus_irrx_clk.common.hw, [CLK_IRTX] =3D &irtx_clk.common.hw, + [CLK_BUS_IRTX] =3D &bus_irtx_clk.common.hw, + [CLK_BUS_LRADC] =3D &bus_lradc_clk.common.hw, [CLK_SGPIO] =3D &sgpio_clk.common.hw, + [CLK_BUS_SGPIO] =3D &bus_sgpio_clk.common.hw, [CLK_LPC] =3D &lpc_clk.common.hw, + [CLK_BUS_LPC] =3D &bus_lpc_clk.common.hw, [CLK_I2SPCM0] =3D &i2spcm0_clk.common.hw, [CLK_I2SPCM1] =3D &i2spcm1_clk.common.hw, [CLK_I2SPCM2] =3D &i2spcm2_clk.common.hw, [CLK_I2SPCM3] =3D &i2spcm3_clk.common.hw, [CLK_I2SPCM4] =3D &i2spcm4_clk.common.hw, + [CLK_BUS_I2SPCM0] =3D &bus_i2spcm0_clk.common.hw, + [CLK_BUS_I2SPCM1] =3D &bus_i2spcm1_clk.common.hw, + [CLK_BUS_I2SPCM2] =3D &bus_i2spcm2_clk.common.hw, + [CLK_BUS_I2SPCM3] =3D &bus_i2spcm3_clk.common.hw, + [CLK_BUS_I2SPCM4] =3D &bus_i2spcm4_clk.common.hw, [CLK_I2SPCM2_ASRC] =3D &i2spcm2_asrc_clk.common.hw, [CLK_OWA_TX] =3D &owa_tx_clk.common.hw, [CLK_OWA_RX] =3D &owa_rx_clk.common.hw, + [CLK_BUS_OWA] =3D &bus_owa_clk.common.hw, [CLK_DMIC] =3D &dmic_clk.common.hw, + [CLK_BUS_DMIC] =3D &bus_dmic_clk.common.hw, [CLK_USB_OHCI0] =3D &usb_ohci0_clk.common.hw, + [CLK_BUS_OTG] =3D &bus_otg_clk.common.hw, + [CLK_BUS_EHCI0] =3D &bus_ehci0_clk.common.hw, + [CLK_BUS_OHCI0] =3D &bus_ohci0_clk.common.hw, [CLK_USB_OHCI1] =3D &usb_ohci1_clk.common.hw, + [CLK_BUS_EHCI1] =3D &bus_ehci1_clk.common.hw, + [CLK_BUS_OHCI1] =3D &bus_ohci1_clk.common.hw, [CLK_USB_REF] =3D &usb_ref_clk.common.hw, [CLK_USB2_U2_REF] =3D &usb2_u2_ref_clk.common.hw, [CLK_USB2_SUSPEND] =3D &usb2_suspend_clk.common.hw, @@ -1662,24 +2119,40 @@ static struct clk_hw_onecell_data sun60i_a733_hw_cl= ks =3D { [CLK_GMAC_PTP] =3D &gmac_ptp_clk.common.hw, [CLK_GMAC0_PHY] =3D &gmac0_phy_clk.common.hw, [CLK_GMAC1_PHY] =3D &gmac1_phy_clk.common.hw, + [CLK_BUS_GMAC0] =3D &bus_gmac0_clk.common.hw, + [CLK_BUS_GMAC1] =3D &bus_gmac1_clk.common.hw, [CLK_TCON_LCD0] =3D &tcon_lcd0_clk.common.hw, [CLK_TCON_LCD1] =3D &tcon_lcd1_clk.common.hw, [CLK_TCON_LCD2] =3D &tcon_lcd2_clk.common.hw, + [CLK_BUS_TCON_LCD0] =3D &bus_tcon_lcd0_clk.common.hw, + [CLK_BUS_TCON_LCD1] =3D &bus_tcon_lcd1_clk.common.hw, + [CLK_BUS_TCON_LCD2] =3D &bus_tcon_lcd2_clk.common.hw, [CLK_DSI0] =3D &dsi0_clk.common.hw, [CLK_DSI1] =3D &dsi1_clk.common.hw, + [CLK_BUS_DSI0] =3D &bus_dsi0_clk.common.hw, + [CLK_BUS_DSI1] =3D &bus_dsi1_clk.common.hw, [CLK_COMBPHY0] =3D &combphy0_clk.common.hw, [CLK_COMBPHY1] =3D &combphy1_clk.common.hw, + [CLK_BUS_TCON_TV0] =3D &bus_tcon_tv0_clk.common.hw, + [CLK_BUS_TCON_TV1] =3D &bus_tcon_tv1_clk.common.hw, [CLK_EDP_TV] =3D &edp_tv_clk.common.hw, + [CLK_BUS_EDP_TV] =3D &bus_edp_tv_clk.common.hw, [CLK_HDMI_CEC_32K] =3D &hdmi_cec_32k_clk.common.hw, [CLK_HDMI_CEC] =3D &hdmi_cec_clk.common.hw, [CLK_HDMI_TV] =3D &hdmi_tv_clk.common.hw, + [CLK_BUS_HDMI_TV] =3D &bus_hdmi_tv_clk.common.hw, [CLK_HDMI_SFR] =3D &hdmi_sfr_clk.common.hw, [CLK_HDMI_ESM] =3D &hdmi_esm_clk.common.hw, + [CLK_BUS_DPSS_TOP0] =3D &bus_dpss_top0_clk.common.hw, + [CLK_BUS_DPSS_TOP1] =3D &bus_dpss_top1_clk.common.hw, [CLK_LEDC] =3D &ledc_clk.common.hw, + [CLK_BUS_LEDC] =3D &bus_ledc_clk.common.hw, + [CLK_BUS_DSC] =3D &bus_dsc_clk.common.hw, [CLK_CSI_MASTER0] =3D &csi_master0_clk.common.hw, [CLK_CSI_MASTER1] =3D &csi_master1_clk.common.hw, [CLK_CSI_MASTER2] =3D &csi_master2_clk.common.hw, [CLK_CSI] =3D &csi_clk.common.hw, + [CLK_BUS_CSI] =3D &bus_csi_clk.common.hw, [CLK_ISP] =3D &isp_clk.common.hw, [CLK_APB2JTAG] =3D &apb2jtag_clk.common.hw, [CLK_FANOUT_24M] =3D &fanout_24M_clk.common.hw, --=20 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=wIuUi81b5xc87mjMqnKxDHMjtZtsydjHQ7LnQvfD5bQ=; b=VobhP4GmRcIBMykcE33sS17MFYpX3kyfQhRBMnWSg2Cy5S7FhU3B+UrL7+rRxGWx M+bcnB0fcSXeW9pG4JYz70s6/0jS56KkqkCMAEt2DqlVogAeKTG0/D2Ju5Hqflqeiwk odYMEl4thxt+SBq2AByet5ibFJdExXS2Xnowet+g= Received: by mx.zohomail.com with SMTPS id 1773132184269896.811332013007; Tue, 10 Mar 2026 01:43:04 -0700 (PDT) From: Junhui Liu Date: Tue, 10 Mar 2026 16:34:01 +0800 Subject: [PATCH RFC 8/8] clk: sunxi-ng: a733: Add reset lines Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260310-a733-clk-v1-8-36b4e9b24457@pigmoral.tech> References: <20260310-a733-clk-v1-0-36b4e9b24457@pigmoral.tech> In-Reply-To: <20260310-a733-clk-v1-0-36b4e9b24457@pigmoral.tech> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Philipp Zabel , Junhui Liu , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Richard Cochran Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, netdev@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773132092; l=6763; i=junhui.liu@pigmoral.tech; s=20251228; h=from:subject:message-id; bh=DAle9vMGgu5f+fCHI2qe6poOC4rkMuj2uAiM+oK2PRI=; b=2NHSLdhJJsd5MdTeFcEphphv0cxbM3Mgx/RtBJb/2ioNmYIvkK3C3B2O9A3T2vSq4Vk+y+AMB Uz+nbAOXBSzCVZLKCUMaFYZCM7jocmrbiguVXSy4g6EvSL+ynLbS/pu X-Developer-Key: i=junhui.liu@pigmoral.tech; a=ed25519; pk=3vU0qIPJAH8blXmLyqBhKx+nLOjcLwwYhZXelEpw7h4= X-ZohoMailClient: External Add the reset lines for the Allwinner A733 SoC. These reset control bits are integrated into the Bus Gate Reset (BGR) registers, typically sharing the same register address with their corresponding bus clock gates. Integrate them into the main CCU driver using the existing sunxi-ng ccu_reset framework, allowing the CCU to also function as a reset controller for the SoC. Signed-off-by: Junhui Liu --- drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 128 +++++++++++++++++++++++++++++= ++++ 1 file changed, 128 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c b/drivers/clk/sunxi-ng/= ccu-sun60i-a733.c index c0b09f9197d1..7d1ee9235436 100644 --- a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c @@ -17,6 +17,7 @@ #include "../clk.h" =20 #include "ccu_common.h" +#include "ccu_reset.h" =20 #include "ccu_div.h" #include "ccu_gate.h" @@ -2169,11 +2170,138 @@ static struct clk_hw_onecell_data sun60i_a733_hw_c= lks =3D { .num =3D CLK_FANOUT3 + 1, }; =20 +static struct ccu_reset_map sun60i_a733_ccu_resets[] =3D { + [RST_BUS_ITS_PCIE] =3D { 0x574, BIT(16) }, + [RST_BUS_NSI] =3D { 0x580, BIT(30) }, + [RST_BUS_NSI_CFG] =3D { 0x584, BIT(16) }, + [RST_BUS_IOMMU0_SYS] =3D { 0x58c, BIT(16) }, + [RST_BUS_MSI_LITE0_AHB] =3D { 0x594, BIT(16) }, + [RST_BUS_MSI_LITE0_MBUS] =3D { 0x594, BIT(17) }, + [RST_BUS_MSI_LITE1_AHB] =3D { 0x59c, BIT(16) }, + [RST_BUS_MSI_LITE1_MBUS] =3D { 0x59c, BIT(17) }, + [RST_BUS_MSI_LITE2_AHB] =3D { 0x5a4, BIT(16) }, + [RST_BUS_MSI_LITE2_MBUS] =3D { 0x5a4, BIT(17) }, + [RST_BUS_IOMMU1_SYS] =3D { 0x5b4, BIT(16) }, + [RST_BUS_DMA0] =3D { 0x704, BIT(16) }, + [RST_BUS_DMA1] =3D { 0x70c, BIT(16) }, + [RST_BUS_SPINLOCK] =3D { 0x724, BIT(16) }, + [RST_BUS_MSGBOX] =3D { 0x744, BIT(16) }, + [RST_BUS_PWM0] =3D { 0x784, BIT(16) }, + [RST_BUS_PWM1] =3D { 0x78c, BIT(16) }, + [RST_BUS_DBG] =3D { 0x7a4, BIT(16) }, + [RST_BUS_SYSDAP] =3D { 0x7ac, BIT(16) }, + [RST_BUS_TIMER0] =3D { 0x850, BIT(16) }, + [RST_BUS_DE] =3D { 0xa04, BIT(16) }, + [RST_BUS_DI] =3D { 0xa24, BIT(16) }, + [RST_BUS_G2D] =3D { 0xa44, BIT(16) }, + [RST_BUS_EINK] =3D { 0xa6c, BIT(16) }, + [RST_BUS_DE_SYS] =3D { 0xa74, BIT(16) }, + [RST_BUS_VE_ENC] =3D { 0xa8c, BIT(16) }, + [RST_BUS_VE_DEC] =3D { 0xa8c, BIT(18) }, + [RST_BUS_CE] =3D { 0xac4, BIT(16) }, + [RST_BUS_CE_SYS] =3D { 0xac4, BIT(17) }, + [RST_BUS_NPU_CORE] =3D { 0xb04, BIT(16) }, + [RST_BUS_NPU_AXI] =3D { 0xb04, BIT(17) }, + [RST_BUS_NPU_AHB] =3D { 0xb04, BIT(18) }, + [RST_BUS_NPU_SRAM] =3D { 0xb04, BIT(19) }, + [RST_BUS_GPU] =3D { 0xb24, BIT(16) }, + [RST_BUS_DRAM] =3D { 0xc0c, BIT(16) }, + [RST_BUS_NAND] =3D { 0xc8c, BIT(16) }, + [RST_BUS_MMC0] =3D { 0xd0c, BIT(16) }, + [RST_BUS_MMC1] =3D { 0xd1c, BIT(16) }, + [RST_BUS_MMC2] =3D { 0xd2c, BIT(16) }, + [RST_BUS_MMC3] =3D { 0xd3c, BIT(16) }, + [RST_BUS_UFS_AHB] =3D { 0xd8c, BIT(16) }, + [RST_BUS_UFS_AXI] =3D { 0xd8c, BIT(17) }, + [RST_BUS_UFS_PHY] =3D { 0xd8c, BIT(18) }, + [RST_BUS_UFS_CORE] =3D { 0xd8c, BIT(19) }, + [RST_BUS_UART0] =3D { 0xe00, BIT(16) }, + [RST_BUS_UART1] =3D { 0xe04, BIT(16) }, + [RST_BUS_UART2] =3D { 0xe08, BIT(16) }, + [RST_BUS_UART3] =3D { 0xe0c, BIT(16) }, + [RST_BUS_UART4] =3D { 0xe10, BIT(16) }, + [RST_BUS_UART5] =3D { 0xe14, BIT(16) }, + [RST_BUS_UART6] =3D { 0xe18, BIT(16) }, + [RST_BUS_I2C0] =3D { 0xe80, BIT(16) }, + [RST_BUS_I2C1] =3D { 0xe84, BIT(16) }, + [RST_BUS_I2C2] =3D { 0xe88, BIT(16) }, + [RST_BUS_I2C3] =3D { 0xe8c, BIT(16) }, + [RST_BUS_I2C4] =3D { 0xe90, BIT(16) }, + [RST_BUS_I2C5] =3D { 0xe94, BIT(16) }, + [RST_BUS_I2C6] =3D { 0xe98, BIT(16) }, + [RST_BUS_I2C7] =3D { 0xe9c, BIT(16) }, + [RST_BUS_I2C8] =3D { 0xea0, BIT(16) }, + [RST_BUS_I2C9] =3D { 0xea4, BIT(16) }, + [RST_BUS_I2C10] =3D { 0xea8, BIT(16) }, + [RST_BUS_I2C11] =3D { 0xeac, BIT(16) }, + [RST_BUS_I2C12] =3D { 0xeb0, BIT(16) }, + [RST_BUS_SPI0] =3D { 0xf04, BIT(16) }, + [RST_BUS_SPI1] =3D { 0xf0c, BIT(16) }, + [RST_BUS_SPI2] =3D { 0xf14, BIT(16) }, + [RST_BUS_SPIF] =3D { 0xf1c, BIT(16) }, + [RST_BUS_SPI3] =3D { 0xf24, BIT(16) }, + [RST_BUS_SPI4] =3D { 0xf2c, BIT(16) }, + [RST_BUS_GPADC] =3D { 0xfc4, BIT(16) }, + [RST_BUS_THS] =3D { 0xfe4, BIT(16) }, + [RST_BUS_IRRX] =3D { 0x1004, BIT(16) }, + [RST_BUS_IRTX] =3D { 0x100c, BIT(16) }, + [RST_BUS_LRADC] =3D { 0x1024, BIT(16) }, + [RST_BUS_SGPIO] =3D { 0x1064, BIT(16) }, + [RST_BUS_LPC] =3D { 0x1084, BIT(16) }, + [RST_BUS_I2SPCM0] =3D { 0x120c, BIT(16) }, + [RST_BUS_I2SPCM1] =3D { 0x121c, BIT(16) }, + [RST_BUS_I2SPCM2] =3D { 0x122c, BIT(16) }, + [RST_BUS_I2SPCM3] =3D { 0x123c, BIT(16) }, + [RST_BUS_I2SPCM4] =3D { 0x124c, BIT(16) }, + [RST_BUS_OWA] =3D { 0x128c, BIT(16) }, + [RST_BUS_DMIC] =3D { 0x12cc, BIT(16) }, + [RST_USB_PHY0] =3D { 0x1300, BIT(30) }, + [RST_BUS_OHCI0] =3D { 0x1304, BIT(16) }, + [RST_BUS_EHCI0] =3D { 0x1304, BIT(20) }, + [RST_BUS_OTG] =3D { 0x1304, BIT(24) }, + [RST_USB_PHY1] =3D { 0x1308, BIT(30) }, + [RST_BUS_OHCI1] =3D { 0x130c, BIT(16) }, + [RST_BUS_EHCI1] =3D { 0x130c, BIT(20) }, + [RST_BUS_USB2] =3D { 0x135c, BIT(16) }, + [RST_BUS_PCIE] =3D { 0x138c, BIT(17) }, + [RST_BUS_PCIE_PWRUP] =3D { 0x138c, BIT(16) }, + [RST_BUS_SERDES] =3D { 0x13c4, BIT(16) }, + [RST_BUS_GMAC0] =3D { 0x141c, BIT(16) }, + [RST_BUS_GMAC0_AXI] =3D { 0x141c, BIT(17) }, + [RST_BUS_GMAC1] =3D { 0x142c, BIT(16) }, + [RST_BUS_GMAC1_AXI] =3D { 0x142c, BIT(17) }, + [RST_BUS_TCON_LCD0] =3D { 0x1504, BIT(16) }, + [RST_BUS_TCON_LCD1] =3D { 0x150c, BIT(16) }, + [RST_BUS_TCON_LCD2] =3D { 0x1514, BIT(16) }, + [RST_BUS_LVDS0] =3D { 0x1544, BIT(16) }, + [RST_BUS_LVDS1] =3D { 0x154c, BIT(16) }, + [RST_BUS_DSI0] =3D { 0x1584, BIT(16) }, + [RST_BUS_DSI1] =3D { 0x158c, BIT(16) }, + [RST_BUS_TCON_TV0] =3D { 0x1604, BIT(16) }, + [RST_BUS_TCON_TV1] =3D { 0x160c, BIT(16) }, + [RST_BUS_EDP] =3D { 0x164c, BIT(16) }, + [RST_BUS_HDMI_MAIN] =3D { 0x168c, BIT(16) }, + [RST_BUS_HDMI_SUB] =3D { 0x168c, BIT(17) }, + [RST_BUS_HDMI_HDCP] =3D { 0x168c, BIT(18) }, + [RST_BUS_DPSS_TOP0] =3D { 0x16c4, BIT(16) }, + [RST_BUS_DPSS_TOP1] =3D { 0x16cc, BIT(16) }, + [RST_BUS_VIDEO_OUT0] =3D { 0x16e4, BIT(16) }, + [RST_BUS_VIDEO_OUT1] =3D { 0x16ec, BIT(16) }, + [RST_BUS_LEDC] =3D { 0x1704, BIT(16) }, + [RST_BUS_DSC] =3D { 0x1744, BIT(16) }, + [RST_BUS_CSI] =3D { 0x1844, BIT(16) }, + [RST_BUS_VIDEO_IN] =3D { 0x1884, BIT(16) }, + [RST_BUS_APB2JTAG] =3D { 0x1c04, BIT(16) }, +}; + static const struct sunxi_ccu_desc sun60i_a733_ccu_desc =3D { .ccu_clks =3D sun60i_a733_ccu_clks, .num_ccu_clks =3D ARRAY_SIZE(sun60i_a733_ccu_clks), =20 .hw_clks =3D &sun60i_a733_hw_clks, + + .resets =3D sun60i_a733_ccu_resets, + .num_resets =3D ARRAY_SIZE(sun60i_a733_ccu_resets), }; =20 static const u32 pll_regs[] =3D { --=20 2.52.0