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charset="utf-8" From: Nick Hawkins Add support for the eMMC controller integrated in the HPE GSC (ARM64 Cortex-A53) BMC SoC under the new 'hpe,gsc-dwcmshc' compatible string. The HPE GSC eMMC controller is based on the DesignWare Cores MSHC IP but requires several platform-specific adjustments: Clock mux (dwcmshc_hpe_set_clock): The GSC SoC wires SDHCI_CLOCK_CONTROL.freq_sel directly to a clock mux rather than a divider. Forcing freq_sel =3D 1 when the requested clock is 200 MHz (HS200) selects the correct high-speed clock source. Using the generic sdhci_set_clock() would otherwise leave the mux on the wrong source after tuning. Auto-tuning / vendor config (dwcmshc_hpe_vendor_specific): Disables the command-conflict check (DWCMSHC_HOST_CTRL3 BIT(0)) and programs ATCTRL =3D 0x021f0005: BIT(0) auto-tuning circuit enable BIT(2) centre-phase auto-tuning BIT(16) tune-clock-stop enable BITS[18:17] pre-change delay =3D 3 BITS[20:19] post-change delay =3D 3 BIT(25) sample-window threshold enable This combination is required for reliable HS200 signal integrity on the GSC PCB trace topology. Reset (dwcmshc_hpe_reset): Calls sdhci_reset(), re-applies the vendor config above, and then sets DWCMSHC_CARD_IS_EMMC unconditionally. The GSC controller clears this bit on every reset; leaving it clear causes card-detect mis-identification on an eMMC-only slot. UHS signaling (dwcmshc_hpe_set_uhs_signaling): Mirrors upstream dwcmshc_set_uhs_signaling() but always sets CARD_IS_EMMC regardless of timing mode, for the same reason. Init (dwcmshc_hpe_gsc_init): Obtains the SoC register block via the 'hpe,gxp-sysreg' syscon phandle and sets SCGSyncDis (BIT(18)) in MSHCCS (offset 0x110) to allow the HS200 RX delay lines to settle while the card clock is stopped during auto-tuning. Enables SDHCI v4 mode. Quirks: SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN: base clock not advertised in capabilities; must be obtained from the DTS 'clocks' property. SDHCI_QUIRK2_PRESET_VALUE_BROKEN: preset-value registers are not populated in the GSC ROM. All HPE-specific code is isolated to the new hpe_gsc_init / hpe_ops / hpe_gsc_pdata symbols. No existing platform (Rockchip, T-Head, sg2042, etc.) is affected. Signed-off-by: Nick Hawkins --- drivers/mmc/host/sdhci-of-dwcmshc.c | 173 ++++++++++++++++++++++++++++ 1 file changed, 173 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-o= f-dwcmshc.c index 2b75a36c096b..78f5480f4662 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -1245,6 +1245,156 @@ static int sg2042_init(struct device *dev, struct s= dhci_host *host, ARRAY_SIZE(clk_ids), clk_ids); } =20 +/* + * HPE GSC-specific vendor configuration: disable command conflict check + * and program Auto-Tuning Control register. + * + * ATCTRL value 0x021f0005 field breakdown: + * BIT(0) - Auto-tuning circuit enabled + * BIT(2) - Center-phase auto-tuning + * BIT(16) - Tune clock stop enable + * BITS[18:17] - Pre-change delay =3D 3 + * BITS[20:19] - Post-change delay =3D 3 + * BIT(25) - Sample window threshold enable + */ +static void dwcmshc_hpe_vendor_specific(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct dwcmshc_priv *dwc_priv =3D sdhci_pltfm_priv(pltfm_host); + u8 extra; + + extra =3D sdhci_readb(host, dwc_priv->vendor_specific_area1 + DWCMSHC_HOS= T_CTRL3); + extra &=3D ~BIT(0); + sdhci_writeb(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_= CTRL3); + sdhci_writel(host, 0x021f0005, dwc_priv->vendor_specific_area1 + DWCMSHC_= EMMC_ATCTRL); +} + +static void dwcmshc_hpe_reset(struct sdhci_host *host, u8 mask) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct dwcmshc_priv *dwc_priv =3D sdhci_pltfm_priv(pltfm_host); + u16 ctrl; + + dwcmshc_reset(host, mask); + + dwcmshc_hpe_vendor_specific(host); + + /* HPE GSC eMMC always needs CARD_IS_EMMC set after reset */ + ctrl =3D sdhci_readw(host, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC= _CONTROL); + ctrl |=3D DWCMSHC_CARD_IS_EMMC; + sdhci_writew(host, ctrl, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_C= ONTROL); +} + +static void dwcmshc_hpe_set_uhs_signaling(struct sdhci_host *host, + unsigned int timing) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct dwcmshc_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + u16 ctrl, ctrl_2; + + ctrl_2 =3D sdhci_readw(host, SDHCI_HOST_CONTROL2); + ctrl_2 &=3D ~SDHCI_CTRL_UHS_MASK; + + /* HPE GSC: always set CARD_IS_EMMC for all timing modes */ + ctrl =3D sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CON= TROL); + ctrl |=3D DWCMSHC_CARD_IS_EMMC; + sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTR= OL); + + if ((timing =3D=3D MMC_TIMING_MMC_HS200) || + (timing =3D=3D MMC_TIMING_UHS_SDR104)) + ctrl_2 |=3D SDHCI_CTRL_UHS_SDR104; + else if (timing =3D=3D MMC_TIMING_UHS_SDR12) + ctrl_2 |=3D SDHCI_CTRL_UHS_SDR12; + else if ((timing =3D=3D MMC_TIMING_UHS_SDR25) || + (timing =3D=3D MMC_TIMING_MMC_HS)) + ctrl_2 |=3D SDHCI_CTRL_UHS_SDR25; + else if (timing =3D=3D MMC_TIMING_UHS_SDR50) + ctrl_2 |=3D SDHCI_CTRL_UHS_SDR50; + else if ((timing =3D=3D MMC_TIMING_UHS_DDR50) || + (timing =3D=3D MMC_TIMING_MMC_DDR52)) + ctrl_2 |=3D SDHCI_CTRL_UHS_DDR50; + else if (timing =3D=3D MMC_TIMING_MMC_HS400) + ctrl_2 |=3D DWCMSHC_CTRL_HS400; + + if (priv->flags & FLAG_IO_FIXED_1V8) + ctrl_2 |=3D SDHCI_CTRL_VDD_180; + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); +} + +/* + * HPE GSC eMMC controller clock setup. + * + * The GSC SoC wires the freq_sel field of SDHCI_CLOCK_CONTROL directly to= a + * clock mux rather than a divider. Force freq_sel =3D 1 when running at + * 200 MHz (HS200) so the mux selects the correct clock source. + */ +static void dwcmshc_hpe_set_clock(struct sdhci_host *host, unsigned int cl= ock) +{ + u16 clk; + + host->mmc->actual_clock =3D 0; + + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + + if (clock =3D=3D 0) + return; + + clk =3D sdhci_calc_clk(host, clock, &host->mmc->actual_clock); + + if (host->mmc->actual_clock =3D=3D 200000000) + clk |=3D (1 << SDHCI_DIVIDER_SHIFT); + + sdhci_enable_clk(host, clk); +} + +/* + * HPE GSC eMMC controller init. + * + * The GSC SoC requires configuring MSHCCS. Bit 18 (SCGSyncDis) disables = clock + * synchronisation for phase-select values going to the HS200 RX delay lin= es, + * allowing the card clock to be stopped while the delay selection settles= and + * the phase shift is applied. This must be used together with the ATCTRL + * settings programmed in dwcmshc_hpe_vendor_specific(): + * AT_CTRL_R.TUNE_CLK_STOP_EN =3D 0x1 + * AT_CTRL_R.POST_CHANGE_DLY =3D 0x3 + * AT_CTRL_R.PRE_CHANGE_DLY =3D 0x3 + * + * The DTS node provides a syscon phandle ('hpe,gxp-sysreg') to access + * this register at offset 0x110 within the SoC control block. + */ +#define HPE_GSC_MSHCCS_OFFSET 0x110 +#define HPE_GSC_MSHCCS_SCGSYNCDIS BIT(18) + +static int dwcmshc_hpe_gsc_init(struct device *dev, struct sdhci_host *hos= t, + struct dwcmshc_priv *dwc_priv) +{ + struct regmap *soc_ctrl; + int ret; + + /* Disable cmd conflict check and configure auto-tuning */ + dwcmshc_hpe_vendor_specific(host); + + /* Look up the GXP sysreg syscon for MSHCCS access */ + soc_ctrl =3D syscon_regmap_lookup_by_phandle(dev->of_node, "hpe,gxp-sysre= g"); + if (IS_ERR(soc_ctrl)) { + dev_err(dev, "failed to get hpe,gxp-sysreg syscon\n"); + return PTR_ERR(soc_ctrl); + } + + /* Set SCGSyncDis (bit 18) to disable sync on HS200 RX delay lines */ + ret =3D regmap_update_bits(soc_ctrl, HPE_GSC_MSHCCS_OFFSET, + HPE_GSC_MSHCCS_SCGSYNCDIS, + HPE_GSC_MSHCCS_SCGSYNCDIS); + if (ret) { + dev_err(dev, "failed to set SCGSyncDis in MSHCCS\n"); + return ret; + } + + sdhci_enable_v4_mode(host); + + return 0; +} + static void sdhci_eic7700_set_clock(struct sdhci_host *host, unsigned int = clock) { struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); @@ -1834,6 +1984,25 @@ static const struct dwcmshc_pltfm_data sdhci_dwcmshc= _eic7700_pdata =3D { .init =3D eic7700_init, }; =20 +static const struct sdhci_ops sdhci_dwcmshc_hpe_ops =3D { + .set_clock =3D dwcmshc_hpe_set_clock, + .set_bus_width =3D sdhci_set_bus_width, + .set_uhs_signaling =3D dwcmshc_hpe_set_uhs_signaling, + .get_max_clock =3D dwcmshc_get_max_clock, + .reset =3D dwcmshc_hpe_reset, + .adma_write_desc =3D dwcmshc_adma_write_desc, + .irq =3D dwcmshc_cqe_irq_handler, +}; + +static const struct dwcmshc_pltfm_data sdhci_dwcmshc_hpe_gsc_pdata =3D { + .pdata =3D { + .ops =3D &sdhci_dwcmshc_hpe_ops, + .quirks =3D SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, + .quirks2 =3D SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + }, + .init =3D dwcmshc_hpe_gsc_init, +}; + static const struct cqhci_host_ops dwcmshc_cqhci_ops =3D { .enable =3D dwcmshc_sdhci_cqe_enable, .disable =3D sdhci_cqe_disable, @@ -1942,6 +2111,10 @@ static const struct of_device_id sdhci_dwcmshc_dt_id= s[] =3D { .compatible =3D "eswin,eic7700-dwcmshc", .data =3D &sdhci_dwcmshc_eic7700_pdata, }, + { + .compatible =3D "hpe,gsc-dwcmshc", + .data =3D &sdhci_dwcmshc_hpe_gsc_pdata, + }, {}, }; MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids); --=20 2.34.1