From nobody Thu Apr 9 12:04:50 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A700C3C1986; Mon, 9 Mar 2026 13:18:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773062340; cv=none; b=WMpvt/TmGzjQykk3OlHoz5PY5w5gqptP3v33UXCg9mI3D3lxVVQrMdhOkbahaXe2DxLGklVwRKzZkz+N7sKby0z6RHDK7LZGLXNuEom4ygLIVrrZBTA8iZ62hL0Z+3J9P/CGKOQhJZY2buRE8lWJ4w6lHdwWxilX12foHbV7Dy8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773062340; c=relaxed/simple; bh=A3LAyJAcz1JA/oFHkCKe5GHN1cunPWBUHb79U1CN1BQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rjc8pZG+LUIaQIn7d3UwspqKEYjffH/6/a3K2P4YJummnJWPGUJdzdaWehU9k/8cD/1N+HnwNtGsCJKdhDFfnSQx9hbqpk5O6htzp+WyQOUluIaA3GzLo/ke4krI5DPJ8NuNFPkQVhPpd7oy5XR2iJR+SW0R2GlXGaSkBJ0TR+E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=Lg/8abVd; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="Lg/8abVd" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 2B413286902; Mon, 9 Mar 2026 14:18:48 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1773062332; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=9FAPg5WayODloJsgbjuayn1s1S4kixRcPa+/l/L2pOs=; b=Lg/8abVdELA3PKS0vOscIdXqNgBqIe4Pe74e94TWFan9onq1ZzdoALU6iSG/lsuc90XTnW PiXzWQd1sg1zBRHBU5TLtm5udutMCxAint36g4N1Lp9EQDbeV40BHqC2TemsTC6pNwPE2Z c671H9b9IiYlYBR4lxBp45dmVkgwe0eJbzUyEjjOM3pJzViOKRdo/x4v/qpWh87UPP+vq8 OeXXpnWep34pf+McP7uP3K7erGBT24eH4/Ukxpb3UgwjER4p634ucAWVb9K69O4l9N1dcP dYYC6OFa1i0t6/5myeZxy7OPwrd2pavU8hOe36LX0l7URO7gA6SK+Kwgy8EB0w== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: naseefkm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, cjd@cjdns.fr, tsbogend@alpha.franken.de, ryder.lee@mediatek.com, jianjun.wang@mediatek.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, bhelgaas@google.com, vkoul@kernel.org, neil.armstrong@linaro.org, p.zabel@pengutronix.de, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, nbd@nbd.name, ansuelsmth@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 3/8] dt-bindings: phy: Document PCIe PHY in EcoNet EN751221 and EN7528 Date: Mon, 9 Mar 2026 13:18:13 +0000 Message-Id: <20260309131818.74467-4-cjd@cjdns.fr> In-Reply-To: <20260309131818.74467-1-cjd@cjdns.fr> References: <20260309131818.74467-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" EN751221 and EN7528 SoCs have two PCIe slots, and each one has a PHY which behaves slightly differently because one slot is Gen1/Gen2 while the other is Gen1 only. Signed-off-by: Caleb James DeLisle Reviewed-by: Krzysztof Kozlowski --- .../phy/econet,en751221-pcie-phy.yaml | 50 +++++++++++++++++++ MAINTAINERS | 6 +++ 2 files changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/econet,en751221-p= cie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy= .yaml b/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml new file mode 100644 index 000000000000..987d396c1c64 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/econet,en751221-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EcoNet PCI-Express PHY for EcoNet EN751221 and EN7528 + +maintainers: + - Caleb James DeLisle + +description: + The PCIe PHY supports physical layer functionality for PCIe Gen1 and + Gen1/Gen2 ports. On these SoCs, port 0 is a Gen1-only port while + port 1 is Gen1/Gen2 capable. + +properties: + compatible: + enum: + - econet,en751221-pcie-gen1 + - econet,en751221-pcie-gen2 + - econet,en7528-pcie-gen1 + - econet,en7528-pcie-gen2 + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + + pcie-phy@1faf2000 { + compatible =3D "econet,en7528-pcie-gen1"; + reg =3D <0x1faf2000 0x1000>; + #phy-cells =3D <0>; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 3781d55db5bb..bc925fa08baa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9122,6 +9122,12 @@ F: drivers/irqchip/irq-econet-en751221.c F: include/dt-bindings/clock/econet,en751221-scu.h F: include/dt-bindings/reset/econet,en751221-scu.h =20 +ECONET PCIE PHY DRIVER +M: Caleb James DeLisle +L: linux-mips@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml + ECRYPT FILE SYSTEM M: Tyler Hicks L: ecryptfs@vger.kernel.org --=20 2.39.5