From nobody Thu Apr 9 10:32:02 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F6013C2774; Mon, 9 Mar 2026 13:18:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773062334; cv=none; b=upyCwTckBnBIzUVv900R7VurHwyCG98VzL1I+dqS63eOmXmnhtduy0Fo9gJGcWVJzLiflsulA7YSw8kpigWay1xsGuV2beX/C+/cVYMTmaWWVcvM/IAALYl+mGgOyvpHy1nmbsY2eAgdhC5kAonMP50S9qMKU3k+6Pq/55iU47A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773062334; c=relaxed/simple; bh=q/q/Hr9u/FQi3GAawSY26iu1G6qQMuvjFv4Se2zHqEU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZP4NhKAH2rP9f9bqFuXjOTde6xUcU7/G3s63WhIKDiQAICWfjc3LKmPBoQ+WocQfulFFo+6z4HOEL9DKBP0qLa0Bzqx0jq6TE/ej7KZa2m7UetSOrvKERWl6IkUcklmtCnT2nLuveJ3vjgFNMECTG+hG0Yc672jiIrRDyWPPYBM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=arpzSAP+; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="arpzSAP+" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 1E69E28680B; Mon, 9 Mar 2026 14:18:40 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1773062323; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=0kKSPlWgiC0oMPA6n4uvU5Sf5SxbvpnQg9oy7p1Ayeo=; b=arpzSAP+g0pElGs95Ot3BhOqKoSnrYBZs+76Rlx4+vAfybkoxr7rxG7roWlwXOd+iMHPMi OA23z5d7vNvC6UDiO5n5xRBg9Ie8JUwLOGDZdK05Arha4VqTqIggHITYS7j8BDqeRp9VO2 p9p3/kcKYXSn6I4N4h7qx0sK2J+F1MSFNo0lXMVBOKafEz4S6f0x0+fIpMY6a4UzBM+Ltj HBNChVddBLZBcDBQYpArmnQ2wmpTN3gXoNjnRokfHxz5PtFNhXYtyPvexOw5Gj+oq6zmGk eQlvPenO6C0d/Te75pTGn2k7cSlbw16StN+cFqxveWE3rCcXb/RAOfNa5UvZ2Q== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: naseefkm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, cjd@cjdns.fr, tsbogend@alpha.franken.de, ryder.lee@mediatek.com, jianjun.wang@mediatek.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, bhelgaas@google.com, vkoul@kernel.org, neil.armstrong@linaro.org, p.zabel@pengutronix.de, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, nbd@nbd.name, ansuelsmth@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/8] dt-bindings: clock, reset: Add econet EN751221 Date: Mon, 9 Mar 2026 13:18:11 +0000 Message-Id: <20260309131818.74467-2-cjd@cjdns.fr> In-Reply-To: <20260309131818.74467-1-cjd@cjdns.fr> References: <20260309131818.74467-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Add clock and reset bindings for EN751221 as well as a "chip-scu" which is an additional regmap that is used by the clock driver as well as others. This split of the SCU across two register areas is the same as the Airoha AN758x family. Signed-off-by: Caleb James DeLisle --- .../bindings/clock/airoha,en7523-scu.yaml | 7 ++- .../devicetree/bindings/mfd/syscon.yaml | 2 + MAINTAINERS | 2 + .../dt-bindings/clock/econet,en751221-scu.h | 13 +++++ .../dt-bindings/reset/econet,en751221-scu.h | 49 +++++++++++++++++++ 5 files changed, 72 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/clock/econet,en751221-scu.h create mode 100644 include/dt-bindings/reset/econet,en751221-scu.h diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml= b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml index a8471367175b..91abe7716fce 100644 --- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml @@ -32,6 +32,7 @@ properties: - enum: - airoha,en7523-scu - airoha,en7581-scu + - econet,en751221-scu =20 reg: items: @@ -67,7 +68,10 @@ allOf: - if: properties: compatible: - const: airoha,en7581-scu + items: + - enum: + - airoha,en7581-scu + - econet,en751221-scu then: properties: reg: @@ -98,3 +102,4 @@ examples: #reset-cells =3D <1>; }; }; + diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index e57add2bacd3..e22867088063 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -61,6 +61,7 @@ select: - cirrus,ep7209-syscon2 - cirrus,ep7209-syscon3 - cnxt,cx92755-uc + - econet,en751221-chip-scu - freecom,fsg-cs2-system-controller - fsl,imx93-aonmix-ns-syscfg - fsl,imx93-wakeupmix-syscfg @@ -173,6 +174,7 @@ properties: - cirrus,ep7209-syscon2 - cirrus,ep7209-syscon3 - cnxt,cx92755-uc + - econet,en751221-chip-scu - freecom,fsg-cs2-system-controller - fsl,imx93-aonmix-ns-syscfg - fsl,imx93-wakeupmix-syscfg diff --git a/MAINTAINERS b/MAINTAINERS index 14899f1de77e..3781d55db5bb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9119,6 +9119,8 @@ F: arch/mips/boot/dts/econet/ F: arch/mips/econet/ F: drivers/clocksource/timer-econet-en751221.c F: drivers/irqchip/irq-econet-en751221.c +F: include/dt-bindings/clock/econet,en751221-scu.h +F: include/dt-bindings/reset/econet,en751221-scu.h =20 ECRYPT FILE SYSTEM M: Tyler Hicks diff --git a/include/dt-bindings/clock/econet,en751221-scu.h b/include/dt-b= indings/clock/econet,en751221-scu.h new file mode 100644 index 000000000000..44a5b197cb06 --- /dev/null +++ b/include/dt-bindings/clock/econet,en751221-scu.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_ +#define _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_ + +#define EN751221_CLK_PCIE 0 +#define EN751221_CLK_SPI 1 +#define EN751221_CLK_BUS 2 +#define EN751221_CLK_CPU 3 +#define EN751221_CLK_HPT 4 +#define EN751221_CLK_GSW 5 + +#endif /* _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_ */ diff --git a/include/dt-bindings/reset/econet,en751221-scu.h b/include/dt-b= indings/reset/econet,en751221-scu.h new file mode 100644 index 000000000000..bad499d4d50a --- /dev/null +++ b/include/dt-bindings/reset/econet,en751221-scu.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_ +#define __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_ + +#define EN751221_XPON_PHY_RST 0 +#define EN751221_PCM1_ZSI_ISI_RST 1 +#define EN751221_FE_QDMA1_RST 2 +#define EN751221_FE_QDMA2_RST 3 +#define EN751221_FE_UNZIP_RST 4 +#define EN751221_PCM2_RST 5 +#define EN751221_PTM_MAC_RST 6 +#define EN751221_CRYPTO_RST 7 +#define EN751221_SAR_RST 8 +#define EN751221_TIMER_RST 9 +#define EN751221_INTC_RST 10 +#define EN751221_BONDING_RST 11 +#define EN751221_PCM1_RST 12 +#define EN751221_UART_RST 13 +#define EN751221_GPIO_RST 14 +#define EN751221_GDMA_RST 15 +#define EN751221_I2C_MASTER_RST 16 +#define EN751221_PCM2_ZSI_ISI_RST 17 +#define EN751221_SFC_RST 18 +#define EN751221_UART2_RST 19 +#define EN751221_GDMP_RST 20 +#define EN751221_FE_RST 21 +#define EN751221_USB_HOST_P0_RST 22 +#define EN751221_GSW_RST 23 +#define EN751221_SFC2_PCM_RST 24 +#define EN751221_PCIE0_RST 25 +#define EN751221_PCIE1_RST 26 +#define EN751221_CPU_TIMER_RST 27 +#define EN751221_PCIE_HB_RST 28 +#define EN751221_SIMIF_RST 29 +#define EN751221_XPON_MAC_RST 30 +#define EN751221_GFAST_RST 31 +#define EN751221_CPU_TIMER2_RST 32 +#define EN751221_UART3_RST 33 +#define EN751221_UART4_RST 34 +#define EN751221_UART5_RST 35 +#define EN751221_I2C2_RST 36 +#define EN751221_XSI_MAC_RST 37 +#define EN751221_XSI_PHY_RST 38 +#define EN751221_DMT_RST 39 +#define EN751221_USB_PHY_P0_RST 40 +#define EN751221_USB_PHY_P1_RST 41 + +#endif /* __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_ */ --=20 2.39.5 From nobody Thu Apr 9 10:32:02 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B44D3B52E0; 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arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="oEHHlD3O" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 4879F285E2D; Mon, 9 Mar 2026 14:18:44 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1773062327; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=Gj0pfLvp62iMiCvC3tR5W8gm+VmvJN9CDG1MgpK5FCE=; b=oEHHlD3OXybb6BBdNmEn7rHh/cvcimbnrW+6bctw5AC409FQkVExAn8koGSXNiFKrKutGv vcZFCWNEBn0SmYKaBTZKK88XF/tkvOZABLMQTJpu/oNLsaTk8XJmvpigHPjSpl3CpRyYVQ 89c6Wi8yHmoaLP+EEbtxg8CW7jQNmR2pO7eVw1Adl+jeNHG3AQnSSGP7goAEessa02eZ+v 2wNQP1Mxp7hTdLmBtB3xAjEgseAYC8ilLviiRzMd2KNCZ9KO3M1Mm6sgz/ShxAXrZQurZJ SfM8NWzzNTTslpNlyUM8q1iuSYngX6fUDr6A6JUo3CYlqjyv8tGlzVPb5I4MbQ== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: naseefkm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, cjd@cjdns.fr, tsbogend@alpha.franken.de, ryder.lee@mediatek.com, jianjun.wang@mediatek.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, bhelgaas@google.com, vkoul@kernel.org, neil.armstrong@linaro.org, p.zabel@pengutronix.de, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, nbd@nbd.name, ansuelsmth@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 2/8] clk: airoha: Add econet EN751221 clock/reset support to en7523-scu Date: Mon, 9 Mar 2026 13:18:12 +0000 Message-Id: <20260309131818.74467-3-cjd@cjdns.fr> In-Reply-To: <20260309131818.74467-1-cjd@cjdns.fr> References: <20260309131818.74467-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" EcoNet EN751221 clock/reset driver is significantly similar to the EN7523 / EN7581, however the EN751221 does not have a neat batch of clock divider registers so there are fewer known clocks, and the frequency of each clock is derived differently. This clock driver will probably work correctly on EN751627, EN7528, and EN7580. Signed-off-by: Caleb James DeLisle --- drivers/clk/Kconfig | 6 +- drivers/clk/clk-en7523.c | 238 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 236 insertions(+), 8 deletions(-) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 3d803b4cf5c1..47df6073a72b 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -218,13 +218,13 @@ config COMMON_CLK_CS2000_CP If you say yes here you get support for the CS2000 clock multiplier. =20 config COMMON_CLK_EN7523 - bool "Clock driver for Airoha EN7523 SoC system clocks" + bool "Clock driver for Airoha/EcoNet SoC system clocks" depends on OF - depends on ARCH_AIROHA || COMPILE_TEST + depends on ARCH_AIROHA || ECONET || COMPILE_TEST default ARCH_AIROHA help This driver provides the fixed clocks and gates present on Airoha - ARM silicon. + and EcoNet silicon. =20 config COMMON_CLK_EP93XX tristate "Clock driver for Cirrus Logic ep93xx SoC" diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 08cc8e5acf43..f7bd7034cf7f 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only =20 +#include #include #include #include @@ -11,6 +12,8 @@ #include #include #include +#include +#include =20 #define RST_NR_PER_BANK 32 =20 @@ -33,15 +36,49 @@ #define REG_RESET_CONTROL_PCIEHB BIT(29) #define REG_RESET_CONTROL_PCIE1 BIT(27) #define REG_RESET_CONTROL_PCIE2 BIT(26) +#define REG_HIR 0x064 +#define REG_HIR_MASK GENMASK(31, 16) /* EN7581 */ #define REG_NP_SCU_PCIC 0x88 #define REG_NP_SCU_SSTR 0x9c #define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13) #define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11) #define REG_CRYPTO_CLKSRC2 0x20c +/* EN751221 */ +#define EN751221_REG_SPI_DIV 0x0cc +#define EN751221_REG_SPI_DIV_MASK GENMASK(31, 8) +#define EN751221_SPI_BASE 500000000 +#define EN751221_SPI_BASE_EN7526C 400000000 +#define EN751221_REG_BUS 0x284 +#define EN751221_REG_BUS_MASK GENMASK(21, 12) +#define EN751221_REG_SSR3 0x094 +#define EN751221_REG_SSR3_GSW_MASK GENMASK(9, 8) =20 #define REG_RST_CTRL2 0x830 #define REG_RST_CTRL1 0x834 +#define EN751221_REG_RST_DMT 0x84 +#define EN751221_REG_RST_USB 0xec + +#define EN751221_MAX_CLKS 6 + +enum en_hir { + HIR_UNKNOWN =3D -1, + HIR_TC3169 =3D 0, + HIR_TC3182 =3D 1, + HIR_RT65168 =3D 2, + HIR_RT63165 =3D 3, + HIR_RT63365 =3D 4, + HIR_MT751020 =3D 5, + HIR_MT7505 =3D 6, + HIR_EN751221 =3D 7, + HIR_EN7526C =3D 8, + HIR_EN751627 =3D 9, + HIR_EN7580 =3D 10, + HIR_EN7528 =3D 11, + HIR_EN7523 =3D 12, + HIR_EN7581 =3D 13, + HIR_MAX =3D 14, +}; =20 struct en_clk_desc { int id; @@ -93,6 +130,8 @@ static const u32 bus7581_base[] =3D { 600000000, 5400000= 00 }; static const u32 npu7581_base[] =3D { 800000000, 750000000, 720000000, 600= 000000 }; static const u32 crypto_base[] =3D { 540000000, 480000000 }; static const u32 emmc7581_base[] =3D { 200000000, 150000000 }; +/* EN751221 */ +static const u32 gsw751221_base[] =3D { 500000000, 250000000, 400000000, 2= 00000000 }; =20 static const struct en_clk_desc en7523_base_clks[] =3D { { @@ -300,6 +339,13 @@ static const u16 en7581_rst_ofs[] =3D { REG_RST_CTRL1, }; =20 +static const u16 en751221_rst_ofs[] =3D { + REG_RST_CTRL2, + REG_RST_CTRL1, + EN751221_REG_RST_DMT, + EN751221_REG_RST_USB, +}; + static const u16 en7523_rst_map[] =3D { /* RST_CTRL2 */ [EN7523_XPON_PHY_RST] =3D 0, @@ -405,8 +451,61 @@ static const u16 en7581_rst_map[] =3D { [EN7581_XPON_MAC_RST] =3D RST_NR_PER_BANK + 31, }; =20 +static const u16 en751221_rst_map[] =3D { + /* RST_CTRL2 */ + [EN751221_XPON_PHY_RST] =3D 0, + [EN751221_GFAST_RST] =3D 1, + [EN751221_CPU_TIMER2_RST] =3D 2, + [EN751221_UART3_RST] =3D 3, + [EN751221_UART4_RST] =3D 4, + [EN751221_UART5_RST] =3D 5, + [EN751221_I2C2_RST] =3D 6, + [EN751221_XSI_MAC_RST] =3D 7, + [EN751221_XSI_PHY_RST] =3D 8, + + /* RST_CTRL1 */ + [EN751221_PCM1_ZSI_ISI_RST] =3D RST_NR_PER_BANK + 0, + [EN751221_FE_QDMA1_RST] =3D RST_NR_PER_BANK + 1, + [EN751221_FE_QDMA2_RST] =3D RST_NR_PER_BANK + 2, + [EN751221_FE_UNZIP_RST] =3D RST_NR_PER_BANK + 3, + [EN751221_PCM2_RST] =3D RST_NR_PER_BANK + 4, + [EN751221_PTM_MAC_RST] =3D RST_NR_PER_BANK + 5, + [EN751221_CRYPTO_RST] =3D RST_NR_PER_BANK + 6, + [EN751221_SAR_RST] =3D RST_NR_PER_BANK + 7, + [EN751221_TIMER_RST] =3D RST_NR_PER_BANK + 8, + [EN751221_INTC_RST] =3D RST_NR_PER_BANK + 9, + [EN751221_BONDING_RST] =3D RST_NR_PER_BANK + 10, + [EN751221_PCM1_RST] =3D RST_NR_PER_BANK + 11, + [EN751221_UART_RST] =3D RST_NR_PER_BANK + 12, + [EN751221_GPIO_RST] =3D RST_NR_PER_BANK + 13, + [EN751221_GDMA_RST] =3D RST_NR_PER_BANK + 14, + [EN751221_I2C_MASTER_RST] =3D RST_NR_PER_BANK + 16, + [EN751221_PCM2_ZSI_ISI_RST] =3D RST_NR_PER_BANK + 17, + [EN751221_SFC_RST] =3D RST_NR_PER_BANK + 18, + [EN751221_UART2_RST] =3D RST_NR_PER_BANK + 19, + [EN751221_GDMP_RST] =3D RST_NR_PER_BANK + 20, + [EN751221_FE_RST] =3D RST_NR_PER_BANK + 21, + [EN751221_USB_HOST_P0_RST] =3D RST_NR_PER_BANK + 22, + [EN751221_GSW_RST] =3D RST_NR_PER_BANK + 23, + [EN751221_SFC2_PCM_RST] =3D RST_NR_PER_BANK + 25, + [EN751221_PCIE0_RST] =3D RST_NR_PER_BANK + 26, + [EN751221_PCIE1_RST] =3D RST_NR_PER_BANK + 27, + [EN751221_CPU_TIMER_RST] =3D RST_NR_PER_BANK + 28, + [EN751221_PCIE_HB_RST] =3D RST_NR_PER_BANK + 29, + [EN751221_SIMIF_RST] =3D RST_NR_PER_BANK + 30, + [EN751221_XPON_MAC_RST] =3D RST_NR_PER_BANK + 31, + + /* RST_DMT */ + [EN751221_DMT_RST] =3D 2 * RST_NR_PER_BANK + 0, + + /* RST_USB */ + [EN751221_USB_PHY_P0_RST] =3D 3 * RST_NR_PER_BANK + 6, + [EN751221_USB_PHY_P1_RST] =3D 3 * RST_NR_PER_BANK + 7, +}; + static int en7581_reset_register(struct device *dev, void __iomem *base, - const u16 *rst_map, int nr_resets); + const u16 *rst_map, int nr_resets, + const u16 *rst_reg_ofs); =20 static u32 en7523_get_base_rate(const struct en_clk_desc *desc, u32 val) { @@ -604,7 +703,8 @@ static int en7523_clk_hw_init(struct platform_device *p= dev, en7523_register_clocks(&pdev->dev, clk_data, base, np_base); =20 return en7581_reset_register(&pdev->dev, np_base, en7523_rst_map, - ARRAY_SIZE(en7523_rst_map)); + ARRAY_SIZE(en7523_rst_map), + en7581_rst_ofs); } =20 static void en7581_register_clocks(struct device *dev, struct clk_hw_onece= ll_data *clk_data, @@ -705,7 +805,8 @@ static const struct reset_control_ops en7581_reset_ops = =3D { }; =20 static int en7581_reset_register(struct device *dev, void __iomem *base, - const u16 *rst_map, int nr_resets) + const u16 *rst_map, int nr_resets, + const u16 *rst_reg_ofs) { struct en_rst_data *rst_data; =20 @@ -713,7 +814,7 @@ static int en7581_reset_register(struct device *dev, vo= id __iomem *base, if (!rst_data) return -ENOMEM; =20 - rst_data->bank_ofs =3D en7581_rst_ofs; + rst_data->bank_ofs =3D rst_reg_ofs; rst_data->idx_map =3D rst_map; rst_data->base =3D base; =20 @@ -752,7 +853,123 @@ static int en7581_clk_hw_init(struct platform_device = *pdev, writel(val | 3, base + REG_NP_SCU_PCIC); =20 return en7581_reset_register(&pdev->dev, base, en7581_rst_map, - ARRAY_SIZE(en7581_rst_map)); + ARRAY_SIZE(en7581_rst_map), + en7581_rst_ofs); +} + +static enum en_hir get_hw_id(void __iomem *np_base) +{ + u32 val =3D FIELD_GET(REG_HIR_MASK, readl(np_base + REG_HIR)); + + if (val < HIR_MAX) + return (enum en_hir) val; + + return HIR_UNKNOWN; +} + +static void en751221_try_register_clk(struct device *dev, int key, + struct clk_hw_onecell_data *clk_data, + const char *name, u32 rate) +{ + struct clk_hw *hw; + + hw =3D clk_hw_register_fixed_rate(dev, name, NULL, 0, rate); + if (IS_ERR(hw) || key >=3D EN751221_MAX_CLKS) + pr_err("Failed to register clk %s: %pe\n", name, hw); + else + clk_data->hws[key] =3D hw; +} + +static void en751221_register_clocks(struct device *dev, + struct clk_hw_onecell_data *clk_data, + struct regmap *map, void __iomem *np_base) +{ + enum en_hir hid =3D get_hw_id(np_base); + struct clk_hw *hw; + u32 rate; + u32 div; + int err; + + /* PCI */ + hw =3D en7523_register_pcie_clk(dev, np_base); + clk_data->hws[EN751221_CLK_PCIE] =3D hw; + + /* SPI */ + rate =3D EN751221_SPI_BASE; + if (hid =3D=3D HIR_EN7526C) + rate =3D EN751221_SPI_BASE_EN7526C; + + err =3D regmap_read(map, EN751221_REG_SPI_DIV, &div); + if (err) { + pr_err("Failed reading fixed clk div %s: %d\n", + "spi", err); + } else { + div =3D FIELD_GET(EN751221_REG_SPI_DIV_MASK, div) * 2; + if (!div) + div =3D 40; + + en751221_try_register_clk(dev, EN751221_CLK_SPI, clk_data, + "spi", rate / div); + } + + /* BUS */ + rate =3D FIELD_GET(EN751221_REG_BUS_MASK, + readl(np_base + EN751221_REG_BUS)); + rate *=3D 1000000; + en751221_try_register_clk(dev, EN751221_CLK_BUS, clk_data, "bus", + rate); + + /* CPU */ + en751221_try_register_clk(dev, EN751221_CLK_CPU, clk_data, "cpu", + rate * 4); + + /* HPT */ + switch (hid) { + case HIR_EN751221: + case HIR_EN751627: + case HIR_EN7526C: + case HIR_EN7580: + case HIR_EN7528: + rate =3D 200000000; + break; + case HIR_MT7505: + rate =3D 100000000; + break; + case HIR_MT751020: + rate =3D 800000000 / 3; + break; + default: + rate =3D 250000000; + } + en751221_try_register_clk(dev, EN751221_CLK_HPT, clk_data, "hpt", + rate); + + /* GSW */ + rate =3D FIELD_GET(EN751221_REG_SSR3_GSW_MASK, + readl(np_base + EN751221_REG_SSR3)); + en751221_try_register_clk(dev, EN751221_CLK_GSW, clk_data, "gsw", + gsw751221_base[rate]); +} + +static int en751221_clk_hw_init(struct platform_device *pdev, + struct clk_hw_onecell_data *clk_data) +{ + struct regmap *map; + void __iomem *base; + + map =3D syscon_regmap_lookup_by_compatible("econet,en751221-chip-scu"); + if (IS_ERR(map)) + return PTR_ERR(map); + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + en751221_register_clocks(&pdev->dev, clk_data, map, base); + + return en7581_reset_register(&pdev->dev, base, en751221_rst_map, + ARRAY_SIZE(en751221_rst_map), + en751221_rst_ofs); } =20 static int en7523_clk_probe(struct platform_device *pdev) @@ -799,9 +1016,20 @@ static const struct en_clk_soc_data en7581_data =3D { .hw_init =3D en7581_clk_hw_init, }; =20 +static const struct en_clk_soc_data en751221_data =3D { + .num_clocks =3D EN751221_MAX_CLKS, + .pcie_ops =3D { + .is_enabled =3D en7523_pci_is_enabled, + .prepare =3D en7523_pci_prepare, + .unprepare =3D en7523_pci_unprepare, + }, + .hw_init =3D en751221_clk_hw_init, +}; + static const struct of_device_id of_match_clk_en7523[] =3D { { .compatible =3D "airoha,en7523-scu", .data =3D &en7523_data }, { .compatible =3D "airoha,en7581-scu", .data =3D &en7581_data }, + { .compatible =3D "econet,en751221-scu", .data =3D &en751221_data }, { /* sentinel */ } }; =20 --=20 2.39.5 From nobody Thu Apr 9 10:32:02 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A700C3C1986; Mon, 9 Mar 2026 13:18:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; 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spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="Lg/8abVd" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 2B413286902; Mon, 9 Mar 2026 14:18:48 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1773062332; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=9FAPg5WayODloJsgbjuayn1s1S4kixRcPa+/l/L2pOs=; b=Lg/8abVdELA3PKS0vOscIdXqNgBqIe4Pe74e94TWFan9onq1ZzdoALU6iSG/lsuc90XTnW PiXzWQd1sg1zBRHBU5TLtm5udutMCxAint36g4N1Lp9EQDbeV40BHqC2TemsTC6pNwPE2Z c671H9b9IiYlYBR4lxBp45dmVkgwe0eJbzUyEjjOM3pJzViOKRdo/x4v/qpWh87UPP+vq8 OeXXpnWep34pf+McP7uP3K7erGBT24eH4/Ukxpb3UgwjER4p634ucAWVb9K69O4l9N1dcP dYYC6OFa1i0t6/5myeZxy7OPwrd2pavU8hOe36LX0l7URO7gA6SK+Kwgy8EB0w== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: naseefkm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, cjd@cjdns.fr, tsbogend@alpha.franken.de, ryder.lee@mediatek.com, jianjun.wang@mediatek.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, bhelgaas@google.com, vkoul@kernel.org, neil.armstrong@linaro.org, p.zabel@pengutronix.de, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, nbd@nbd.name, ansuelsmth@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 3/8] dt-bindings: phy: Document PCIe PHY in EcoNet EN751221 and EN7528 Date: Mon, 9 Mar 2026 13:18:13 +0000 Message-Id: <20260309131818.74467-4-cjd@cjdns.fr> In-Reply-To: <20260309131818.74467-1-cjd@cjdns.fr> References: <20260309131818.74467-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" EN751221 and EN7528 SoCs have two PCIe slots, and each one has a PHY which behaves slightly differently because one slot is Gen1/Gen2 while the other is Gen1 only. Signed-off-by: Caleb James DeLisle Reviewed-by: Krzysztof Kozlowski --- .../phy/econet,en751221-pcie-phy.yaml | 50 +++++++++++++++++++ MAINTAINERS | 6 +++ 2 files changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/econet,en751221-p= cie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy= .yaml b/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml new file mode 100644 index 000000000000..987d396c1c64 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/econet,en751221-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EcoNet PCI-Express PHY for EcoNet EN751221 and EN7528 + +maintainers: + - Caleb James DeLisle + +description: + The PCIe PHY supports physical layer functionality for PCIe Gen1 and + Gen1/Gen2 ports. On these SoCs, port 0 is a Gen1-only port while + port 1 is Gen1/Gen2 capable. + +properties: + compatible: + enum: + - econet,en751221-pcie-gen1 + - econet,en751221-pcie-gen2 + - econet,en7528-pcie-gen1 + - econet,en7528-pcie-gen2 + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells =3D <1>; + #size-cells =3D <1>; + + pcie-phy@1faf2000 { + compatible =3D "econet,en7528-pcie-gen1"; + reg =3D <0x1faf2000 0x1000>; + #phy-cells =3D <0>; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 3781d55db5bb..bc925fa08baa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9122,6 +9122,12 @@ F: drivers/irqchip/irq-econet-en751221.c F: include/dt-bindings/clock/econet,en751221-scu.h F: include/dt-bindings/reset/econet,en751221-scu.h =20 +ECONET PCIE PHY DRIVER +M: Caleb James DeLisle +L: linux-mips@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml + ECRYPT FILE SYSTEM M: Tyler Hicks L: ecryptfs@vger.kernel.org --=20 2.39.5 From nobody Thu Apr 9 10:32:02 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED5B23BD63D; Mon, 9 Mar 2026 13:18:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773062340; cv=none; b=FOad2VegMTzsaFUJQhVPyIlnPRuWC3llBXuC0NAJmeAKWo3H0mex/gLApyGdtqAUxUTee8S6h24P6OMMTxMdyq45kEHy0wcR1e9nGw2qPVnNecOoyYFDrhQ20ibbLpuPvRBxFH26YLjlYnfXlItrKh28T0SluIp8dk9Xrs9pYdw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773062340; c=relaxed/simple; bh=gyMk7nvx9IgZUGQh97vkC0j+GVRi8Q+Ceg4Wx47cXjM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=M6j9GYxi5eI/KEBjVCXfqr0jSawjGrgNBOUmHfbNQTj7XqUQqv5N2mQkxa+6Vkm7oaVdTroQxOChZWQJRXW0n6/PB0Mo1vyfKvjmbZ59FB73dv2qKXHGnRZVVhx8F7xbH8t5bBXOXg+DeXmKxmHWUJmbP4WcukLZkhnxaOwzs/Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=pass smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=hXMzu1BM; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="hXMzu1BM" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id AA5B4286985; Mon, 9 Mar 2026 14:18:52 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1773062336; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=kQWdgH3x2vdZ3Qquixcoy7M8nIfPldbaMc0m6t5PCmk=; b=hXMzu1BMB8G9qNV/3jKACz9Cg7ErGd6P+Cp0RoC6Y+GevATuWka3EQzwL+FYskxx+Kyt8o MMy4aP3LbxvD0Wlbk1sfq2T+1gHyBetZxbh1Shit4FTsq3GoR8Pvlv5K7WSyjbiBL6ZQ0A uVdG1s/9AnqM7CHXUW5T79XU8twUMTkEt0mkaOfKxaqd2dG2k0Uw8bnLJpNmk1LvJRQToF TgGNEa0BoZWmjiVAHxm/y0mRGJkBSQV4sFVbR5EYBDBtOqktofLlGD+1/drmwIqJzEdBVu EnI6mKo51CCaNa8YLQzyYzTBa0lDxL7EPy8CSpwURPcguObcrDMcMWuIzX1KVw== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: naseefkm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, cjd@cjdns.fr, tsbogend@alpha.franken.de, ryder.lee@mediatek.com, jianjun.wang@mediatek.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, bhelgaas@google.com, vkoul@kernel.org, neil.armstrong@linaro.org, p.zabel@pengutronix.de, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, nbd@nbd.name, ansuelsmth@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 4/8] phy: econet: Add PCIe PHY driver for EcoNet EN751221 and EN7528 SoCs. Date: Mon, 9 Mar 2026 13:18:14 +0000 Message-Id: <20260309131818.74467-5-cjd@cjdns.fr> In-Reply-To: <20260309131818.74467-1-cjd@cjdns.fr> References: <20260309131818.74467-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Introduce support for EcoNet PCIe PHY controllers found in EN751221 and EN7528 SoCs, these SoCs are not identical but are similar, each having one Gen1 port, and one Gen1/Gen2 port. Co-developed-by: Ahmed Naseef Signed-off-by: Ahmed Naseef [cjd@cjdns.fr: add EN751221 support and refactor for clarity] Signed-off-by: Caleb James DeLisle --- MAINTAINERS | 1 + drivers/phy/Kconfig | 12 +++ drivers/phy/Makefile | 1 + drivers/phy/phy-econet-pcie.c | 180 ++++++++++++++++++++++++++++++++++ 4 files changed, 194 insertions(+) create mode 100644 drivers/phy/phy-econet-pcie.c diff --git a/MAINTAINERS b/MAINTAINERS index bc925fa08baa..e61a349864fc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9127,6 +9127,7 @@ M: Caleb James DeLisle L: linux-mips@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml +F: drivers/phy/phy-econet-pcie.c =20 ECRYPT FILE SYSTEM M: Tyler Hicks diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 02467dfd4fb0..60efc37f6eb0 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -123,6 +123,18 @@ config PHY_AIROHA_PCIE This driver create the basic PHY instance and provides initialize callback for PCIe GEN3 port. =20 +config PHY_ECONET_PCIE + tristate "EcoNet PCIe-PHY Driver" + depends on ECONET || COMPILE_TEST + depends on OF + select GENERIC_PHY + select REGMAP_MMIO + help + Say Y here to add support for EcoNet PCIe PHY driver. + This driver create the basic PHY instance and provides initialize + callback for PCIe GEN1 and GEN2 ports. This PHY is found on + EcoNet SoCs including EN751221 and EN7528. + config PHY_NXP_PTN3222 tristate "NXP PTN3222 1-port eUSB2 to USB2 redriver" depends on I2C diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index a648c2e02a83..a77f182ee8f3 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PHY_PISTACHIO_USB) +=3D phy-pistachio-usb.o obj-$(CONFIG_PHY_SNPS_EUSB2) +=3D phy-snps-eusb2.o obj-$(CONFIG_USB_LGM_PHY) +=3D phy-lgm-usb.o obj-$(CONFIG_PHY_AIROHA_PCIE) +=3D phy-airoha-pcie.o +obj-$(CONFIG_PHY_ECONET_PCIE) +=3D phy-econet-pcie.o obj-$(CONFIG_PHY_NXP_PTN3222) +=3D phy-nxp-ptn3222.o obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE) +=3D phy-spacemit-k1-pcie.o obj-$(CONFIG_GENERIC_PHY) +=3D allwinner/ \ diff --git a/drivers/phy/phy-econet-pcie.c b/drivers/phy/phy-econet-pcie.c new file mode 100644 index 000000000000..d2c6e0c1f331 --- /dev/null +++ b/drivers/phy/phy-econet-pcie.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Author: Caleb James DeLisle + * Ahmed Naseef + */ + +#include +#include +#include +#include +#include +#include + +/* Rx detection timing for EN751221: 16*8 clock cycles */ +#define EN751221_RXDET_VAL 16 + +/* Rx detection timing when in power mode 3 */ +#define EN75_RXDET_P3_REG 0xa28 +#define EN75_RXDET_P3_MASK GENMASK(17, 9) + +/* Rx detection timing when in power mode 2 */ +#define EN75_RXDET_P2_REG 0xa2c +#define EN75_RXDET_P2_MASK GENMASK(8, 0) + +/* Rx impedance */ +#define EN75_RX_IMPEDANCE_REG 0xb2c +#define EN75_RX_IMPEDANCE_MASK GENMASK(13, 12) +enum en75_rx_impedance { + EN75_RX_IMPEDANCE_100_OHM =3D 0, + EN75_RX_IMPEDANCE_95_OHM =3D 1, + EN75_RX_IMPEDANCE_90_OHM =3D 2, +}; + +/* PLL Invert clock */ +#define EN75_PLL_PH_INV_REG 0x4a0 +#define EN75_PLL_PH_INV_MASK BIT(5) + +struct en75_phy_op { + u32 reg; + u32 mask; + u32 val; +}; + +struct en7528_pcie_phy { + struct regmap *regmap; + const struct en75_phy_op *data; +}; + +/* Port 0 PHY: set LCDDS_CLK_PH_INV for PLL operation */ +static const struct en75_phy_op en7528_phy_gen1[] =3D { + { + .reg =3D EN75_PLL_PH_INV_REG, + .mask =3D EN75_PLL_PH_INV_MASK, + .val =3D 1, + }, + { /* sentinel */ } +}; + +/* EN7528 Port 1 PHY: Rx impedance tuning, target R -5 Ohm */ +static const struct en75_phy_op en7528_phy_gen2[] =3D { + { + .reg =3D EN75_RX_IMPEDANCE_REG, + .mask =3D EN75_RX_IMPEDANCE_MASK, + .val =3D EN75_RX_IMPEDANCE_95_OHM, + }, + { /* sentinel */ } +}; + +/* EN751221 Port 1 PHY, set RX detect to 16*8 clock cycles */ +static const struct en75_phy_op en751221_phy_gen2[] =3D { + { + .reg =3D EN75_RXDET_P3_REG, + .mask =3D EN75_RXDET_P3_MASK, + .val =3D EN751221_RXDET_VAL, + }, + { + .reg =3D EN75_RXDET_P2_REG, + .mask =3D EN75_RXDET_P2_MASK, + .val =3D EN751221_RXDET_VAL, + }, + { /* sentinel */ } +}; + +static int en75_pcie_phy_init(struct phy *phy) +{ + struct en7528_pcie_phy *ephy =3D phy_get_drvdata(phy); + const struct en75_phy_op *data =3D ephy->data; + int i, ret; + u32 val; + + for (i =3D 0; data[i].mask || data[i].val; i++) { + if (i) + usleep_range(1000, 2000); + + val =3D field_prep(data[i].mask, data[i].val); + + ret =3D regmap_update_bits(ephy->regmap, data[i].reg, + data[i].mask, val); + if (ret) + return ret; + } + + return 0; +} + +static const struct phy_ops en75_pcie_phy_ops =3D { + .init =3D en75_pcie_phy_init, + .owner =3D THIS_MODULE, +}; + +static int en75_pcie_phy_probe(struct platform_device *pdev) +{ + struct regmap_config regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + }; + struct device *dev =3D &pdev->dev; + const struct en75_phy_op *data; + struct phy_provider *provider; + struct en7528_pcie_phy *ephy; + void __iomem *base; + struct phy *phy; + int i; + + data =3D of_device_get_match_data(dev); + if (!data) + return -EINVAL; + + ephy =3D devm_kzalloc(dev, sizeof(*ephy), GFP_KERNEL); + if (!ephy) + return -ENOMEM; + + ephy->data =3D data; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + /* Set max_register to highest used register */ + for (i =3D 0; data[i].mask || data[i].val; i++) + if (data[i].reg > regmap_config.max_register) + regmap_config.max_register =3D data[i].reg; + + ephy->regmap =3D devm_regmap_init_mmio(dev, base, ®map_config); + if (IS_ERR(ephy->regmap)) + return PTR_ERR(ephy->regmap); + + phy =3D devm_phy_create(dev, dev->of_node, &en75_pcie_phy_ops); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + phy_set_drvdata(phy, ephy); + + provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(provider); +} + +static const struct of_device_id en75_pcie_phy_ids[] =3D { + { .compatible =3D "econet,en7528-pcie-gen1", .data =3D en7528_phy_gen1 }, + { .compatible =3D "econet,en7528-pcie-gen2", .data =3D en7528_phy_gen2 }, + { .compatible =3D "econet,en751221-pcie-gen1", .data =3D en7528_phy_gen1 = }, + { .compatible =3D "econet,en751221-pcie-gen2", .data =3D en751221_phy_gen= 2 }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, en75_pcie_phy_ids); + +static struct platform_driver en75_pcie_phy_driver =3D { + .probe =3D en75_pcie_phy_probe, + .driver =3D { + .name =3D "econet-pcie-phy", + .of_match_table =3D en75_pcie_phy_ids, + }, +}; +module_platform_driver(en75_pcie_phy_driver); + +MODULE_AUTHOR("Caleb James DeLisle "); +MODULE_DESCRIPTION("EcoNet PCIe PHY driver"); +MODULE_LICENSE("GPL"); --=20 2.39.5 From nobody Thu Apr 9 10:32:02 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EA8D3BD63D; Mon, 9 Mar 2026 13:19:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773062345; cv=none; b=WJBDvb7KnSN3HoJPy3aI6dfDec5LQyKQg2R2Xol1X9458kxmw+2R+V3E76AsPynQUw088MaUgi+dv4REFidU80zOCceqnzK2AK/Bw1o1sGv+ByFMgz1m9b99Y1O1hXHM1VV4wkkR3Z+1xnWAfMaFoVbknXzWSYXHJql5uGTFei0= ARC-Message-Signature: i=1; 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Mon, 9 Mar 2026 14:18:56 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1773062341; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=OiRQgm2fH3aML6cl3pDo1ClODmIrMf+JKaRfp7jk63k=; b=ehIaKPCbQpJv7N/K2R3jc1AxUGhEwUdKkelwgQ8B9PibujelZs9PyDJFlFpM/30aGlT0KN jJP1w2hHUMKQSChlRCMoBJMwJbK8SkyaB8wKoYjtJ3J4h0hzhTTDZMh6rR36FgCX/j8j0M kpAeBi7jvCfaVZTbSe8dDLeRWyarb/3wmFMUJK/vqA8njbScl492GZRJhpGbgWwEy3QTU1 QyjWENdyQWNo/98DPrJ7lOuk4bIqTwOcAUawzll5XtnfxzFs3stbm3ZFQmToRYvzXjvZHs rw4gaorrqfp852WQfiaUGdBmN+SnXl+4xIUpf14mfYBoxSz269oRp+QeLzXsEw== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: naseefkm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, cjd@cjdns.fr, tsbogend@alpha.franken.de, ryder.lee@mediatek.com, jianjun.wang@mediatek.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, bhelgaas@google.com, vkoul@kernel.org, neil.armstrong@linaro.org, p.zabel@pengutronix.de, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, nbd@nbd.name, ansuelsmth@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 5/8] dt-bindings: PCI: mediatek: Add support for EcoNet EN7528 Date: Mon, 9 Mar 2026 13:18:15 +0000 Message-Id: <20260309131818.74467-6-cjd@cjdns.fr> In-Reply-To: <20260309131818.74467-1-cjd@cjdns.fr> References: <20260309131818.74467-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Introduce EcoNet EN7528 SoC compatible in MediaTek PCIe controller binding. EcoNet PCIe controller has the same configuration model as Mediatek v2 but is initiallized more similarly to an MT7621 PCIe. Signed-off-by: Caleb James DeLisle --- Documentation/devicetree/bindings/pci/mediatek-pcie.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml b/Doc= umentation/devicetree/bindings/pci/mediatek-pcie.yaml index 0b8c78ec4f91..57cbfbff7a31 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml @@ -14,6 +14,7 @@ properties: oneOf: - enum: - airoha,an7583-pcie + - econet,en7528-pcie - mediatek,mt2712-pcie - mediatek,mt7622-pcie - mediatek,mt7629-pcie --=20 2.39.5 From nobody Thu Apr 9 10:32:02 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B88003B52E0; Mon, 9 Mar 2026 13:19:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773062351; cv=none; b=O2mMRR8T6+CijaSuBzABFf6W4MVUps85cjfEpIvXOgtWcKqdYrUNdOycQy6+wWwsdkSJgEeKmTL7jBOR9RAiZnUxbgltmxrpVWAQsUNHHblC2nFPm+3+MDkwPnwVUBRiMgpbUwuxzbh5B7isf8g6eGs2JA5yRRbt2LQ6UTYmxis= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773062351; c=relaxed/simple; bh=FD4BI1Gb3m19FPn08PLkbT5uw/0VcS7n03LI5QfIoP0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=PdJDaHiC+t1MNEe2vxL6bJQLaOac6tNkT5grU09zToTaOvbaZlt1yrT+YWkGjRlrhn8omBsZDO/oU2ehC7Ysw1Yoz8O7TVxvlNxIhz7NE4Sol0B1mxtvbB3Q1fRMe/8Q7pnWpnnC4fLLiYLCH5zO6qQ35zhlhxSJ2X2yDr2PepI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=pnmFChtk; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="pnmFChtk" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 6223F2861EC; Mon, 9 Mar 2026 14:19:02 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1773062347; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=HuHaP85Of4AqfnaoFvV68qQ7iaLR88P52Epoh/9OC4Q=; b=pnmFChtkt4LokGmhRv0fEs4jfOzaJdDa2ru6kXEp+sneiFOF4Ws0oBzuByRVTQwQJgrMXQ ORafaY0xuamaCWq7QVYYls6YQOOep5AohUsAq+NqjFBZVIrJgXwqvVu5yPsS5S38CpQL6X f7wqmn0+tJp205nmuDP/NULmv3UA/uHZcakJWusPIWULqR/g8w6sDInGUC2L6EJ/9DVxFa gOURfm+JsmUT5wpJVgEp13q999xpGIvbOrcPiYjcRDiRDaKXO6E/qlddHhwArOhxJaw6Hg 0/oP+nZ9PQOWbFxJnb/vxKNHFmItTPjhwHGlY5VKpuL86g9I+4DcjMH7wPa92g== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: naseefkm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, cjd@cjdns.fr, tsbogend@alpha.franken.de, ryder.lee@mediatek.com, jianjun.wang@mediatek.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, bhelgaas@google.com, vkoul@kernel.org, neil.armstrong@linaro.org, p.zabel@pengutronix.de, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, nbd@nbd.name, ansuelsmth@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 6/8] PCI: mediatek: Add support for EcoNet EN7528 SoC Date: Mon, 9 Mar 2026 13:18:16 +0000 Message-Id: <20260309131818.74467-7-cjd@cjdns.fr> In-Reply-To: <20260309131818.74467-1-cjd@cjdns.fr> References: <20260309131818.74467-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Add support for the PCIe present on the EcoNet EN7528 (and EN751221) SoCs. These SoCs have a mix of Gen1 and Gen2 capable ports, but the Gen2 ports require re-training after startup. Co-developed-by: Ahmed Naseef Signed-off-by: Ahmed Naseef Signed-off-by: Caleb James DeLisle --- drivers/pci/controller/Kconfig | 2 +- drivers/pci/controller/pcie-mediatek.c | 118 +++++++++++++++++++++++++ 2 files changed, 119 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 5aaed8ac6e44..f6a5fcacb38d 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -209,7 +209,7 @@ config PCI_MVEBU =20 config PCIE_MEDIATEK tristate "MediaTek PCIe controller" - depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST + depends on ARCH_AIROHA || ARCH_MEDIATEK || ECONET || COMPILE_TEST depends on OF depends on PCI_MSI select IRQ_MSI_LIB diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controlle= r/pcie-mediatek.c index 5defa5cc4c2b..84064061652a 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -77,6 +78,7 @@ =20 #define PCIE_CONF_VEND_ID 0x100 #define PCIE_CONF_DEVICE_ID 0x102 +#define PCIE_CONF_REV_CLASS 0x104 #define PCIE_CONF_CLASS_ID 0x106 =20 #define PCIE_INT_MASK 0x420 @@ -89,6 +91,11 @@ #define MSI_MASK BIT(23) #define MTK_MSI_IRQS_NUM 32 =20 +#define EN7528_HOST_MODE 0x00804201 +#define EN7528_LINKUP_REG 0x50 +#define EN7528_RC0_LINKUP BIT(1) +#define EN7528_RC1_LINKUP BIT(2) + #define PCIE_AHB_TRANS_BASE0_L 0x438 #define PCIE_AHB_TRANS_BASE0_H 0x43c #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0)) @@ -753,6 +760,86 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_po= rt *port) return 0; } =20 +static int mtk_pcie_startup_port_en7528(struct mtk_pcie_port *port) +{ + struct mtk_pcie *pcie =3D port->pcie; + struct pci_host_bridge *host =3D pci_host_bridge_from_priv(pcie); + struct resource *mem =3D NULL; + struct resource_entry *entry; + u32 val, link_mask; + int err; + + entry =3D resource_list_first_type(&host->windows, IORESOURCE_MEM); + if (entry) + mem =3D entry->res; + if (!mem) + return -EINVAL; + + if (!pcie->cfg) { + dev_err(pcie->dev, "EN7528: pciecfg syscon not available\n"); + return -EINVAL; + } + + /* Assert all reset signals */ + writel(0, port->base + PCIE_RST_CTRL); + + /* + * Enable PCIe link down reset, if link status changed from link up to + * link down, this will reset MAC control registers and configuration + * space. + */ + writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); + + /* + * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and + * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# + * should be delayed 100ms (TPVPERL) for the power and clock to become + * stable. + */ + msleep(100); + + /* De-assert PHY, PE, PIPE, MAC and configuration reset */ + val =3D readl(port->base + PCIE_RST_CTRL); + val |=3D PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | + PCIE_MAC_SRSTB | PCIE_CRSTB; + writel(val, port->base + PCIE_RST_CTRL); + + writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, + port->base + PCIE_CONF_REV_CLASS); + writel(EN7528_HOST_MODE, port->base); + + link_mask =3D (port->slot =3D=3D 0) ? EN7528_RC0_LINKUP : EN7528_RC1_LINK= UP; + + /* 100ms timeout value should be enough for Gen1/2 training */ + err =3D regmap_read_poll_timeout(pcie->cfg, EN7528_LINKUP_REG, val, + !!(val & link_mask), 20, + 100 * USEC_PER_MSEC); + if (err) { + dev_err(pcie->dev, "EN7528: port%d link timeout\n", port->slot); + return -ETIMEDOUT; + } + + /* Set INTx mask */ + val =3D readl(port->base + PCIE_INT_MASK); + val &=3D ~INTX_MASK; + writel(val, port->base + PCIE_INT_MASK); + + if (IS_ENABLED(CONFIG_PCI_MSI)) + mtk_pcie_enable_msi(port); + + /* Set AHB to PCIe translation windows */ + val =3D lower_32_bits(mem->start) | + AHB2PCIE_SIZE(fls(resource_size(mem))); + writel(val, port->base + PCIE_AHB_TRANS_BASE0_L); + + val =3D upper_32_bits(mem->start); + writel(val, port->base + PCIE_AHB_TRANS_BASE0_H); + + writel(WIN_ENABLE, port->base + PCIE_AXI_WINDOW0); + + return 0; +} + static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { @@ -1149,6 +1236,30 @@ static int mtk_pcie_probe(struct platform_device *pd= ev) if (err) goto put_resources; =20 + /* Retrain Gen1 links to reach Gen2 where supported */ + if (pcie->soc->startup =3D=3D mtk_pcie_startup_port_en7528) { + struct pci_bus *bus =3D host->bus; + struct pci_dev *rc =3D NULL; + + while ((rc =3D pci_get_class(PCI_CLASS_BRIDGE_PCI << 8, rc))) { + int ret =3D -EOPNOTSUPP; + + if (rc->bus !=3D bus) + continue; + + #if IS_BUILTIN(CONFIG_PCIE_MEDIATEK) + ret =3D pcie_retrain_link(rc, true); + #endif + + if (!ret) + dev_info(dev, "port%d link retrained\n", + PCI_SLOT(rc->devfn)); + else + dev_info(dev, "port%d failed to retrain %pe\n", + PCI_SLOT(rc->devfn), ERR_PTR(ret)); + } + } + return 0; =20 put_resources: @@ -1264,8 +1375,15 @@ static const struct mtk_pcie_soc mtk_pcie_soc_mt7629= =3D { .quirks =3D MTK_PCIE_FIX_CLASS_ID | MTK_PCIE_FIX_DEVICE_ID, }; =20 +static const struct mtk_pcie_soc mtk_pcie_soc_en7528 =3D { + .ops =3D &mtk_pcie_ops_v2, + .startup =3D mtk_pcie_startup_port_en7528, + .setup_irq =3D mtk_pcie_setup_irq, +}; + static const struct of_device_id mtk_pcie_ids[] =3D { { .compatible =3D "airoha,an7583-pcie", .data =3D &mtk_pcie_soc_an7583 }, + { .compatible =3D "econet,en7528-pcie", .data =3D &mtk_pcie_soc_en7528 }, { .compatible =3D "mediatek,mt2701-pcie", .data =3D &mtk_pcie_soc_v1 }, { .compatible =3D "mediatek,mt7623-pcie", .data =3D &mtk_pcie_soc_v1 }, { .compatible =3D "mediatek,mt2712-pcie", .data =3D &mtk_pcie_soc_mt2712 = }, --=20 2.39.5 From nobody Thu Apr 9 10:32:02 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 758E93C2798; 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arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="HF2R0jnb" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 635EE286C09; Mon, 9 Mar 2026 14:19:07 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1773062352; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=Hun8qRSx+c81aOcVRS1X8gTZpBZdlow4lndHrL4U0TU=; b=HF2R0jnbjMCjt6F6GTSzu2+49yojrI0X6Zrj5TWhd7IOb7azquDI4KpmVCYjJidlE+fbs9 PlpRcqiMdtQUVp+kMkK4BvYZosqeBkjNAoMLP5VELJQmxVapM0t89pvSYy06I1l/FamsnC clUM+0seM+v5TkHAJA9fV9V4ADPusFG8FbabslvGnds/kwas6t4Hw2rS3y52LplGYgGY/Q qubTLRLk9VbsgyxT0iBC2XmcYjp55wKJfGaUVMAAgJPS5YgwFIS8HAKOQKlQku+bRkqoxu HtKitXkSJm6j+DE2yywDkY6lp/5+cnOjKM6Ci8PzkjR6v48sX7uKIHcESV/t7Q== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: naseefkm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, cjd@cjdns.fr, tsbogend@alpha.franken.de, ryder.lee@mediatek.com, jianjun.wang@mediatek.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, bhelgaas@google.com, vkoul@kernel.org, neil.armstrong@linaro.org, p.zabel@pengutronix.de, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, nbd@nbd.name, ansuelsmth@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Bjorn Helgaas Subject: [PATCH v2 7/8] PCI: Skip bridge window reads when window is not supported Date: Mon, 9 Mar 2026 13:18:17 +0000 Message-Id: <20260309131818.74467-8-cjd@cjdns.fr> In-Reply-To: <20260309131818.74467-1-cjd@cjdns.fr> References: <20260309131818.74467-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" pci_read_bridge_io() and pci_read_bridge_mmio_pref() read bridge window registers unconditionally. If the registers are hardwired to zero (not implemented), both base and limit will be 0. Since (0 <=3D 0) is true, a bogus window [mem 0x00000000-0x000fffff] or [io 0x0000-0x0fff] gets created. pci_read_bridge_windows() already detects unsupported windows by testing register writability and sets io_window/pref_window flags accordingly. Check these flags at the start of pci_read_bridge_io() and pci_read_bridge_mmio_pref() to skip reading registers when the window is not supported. Suggested-by: Bjorn Helgaas Link: https://lore.kernel.org/all/20260113210259.GA715789@bhelgaas/ Signed-off-by: Ahmed Naseef Signed-off-by: Caleb James DeLisle --- drivers/pci/probe.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index bccc7a4bdd79..4eacb741b4ec 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -395,6 +395,9 @@ static void pci_read_bridge_io(struct pci_dev *dev, str= uct resource *res, unsigned long io_mask, io_granularity, base, limit; struct pci_bus_region region; =20 + if (!dev->io_window) + return; + io_mask =3D PCI_IO_RANGE_MASK; io_granularity =3D 0x1000; if (dev->io_window_1k) { @@ -465,6 +468,9 @@ static void pci_read_bridge_mmio_pref(struct pci_dev *d= ev, struct resource *res, pci_bus_addr_t base, limit; struct pci_bus_region region; =20 + if (!dev->pref_window) + return; + pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); base64 =3D (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; --=20 2.39.5 From nobody Thu Apr 9 10:32:02 2026 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CCE83C1988; Mon, 9 Mar 2026 13:19:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.135.140.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773062362; cv=none; b=IciLSJRzP5sM9w9G7UDVZHA1zBilmuAlhVgSrCxDJjZQ08T8oBIDROKIIa1IpWYLCjCVdp5IAvzvPToiyopyVrrSDUhRO1ZitmTwJ6IrCZ1M4XJDCrPOvPMZwSp+c6ZS7XNwmellxcz+etYBIoBZiEqnuzkIjq0nYZTNGI7FLQI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773062362; c=relaxed/simple; bh=OuVg1o1oE6Dk4NJfoc56g7qoOxUkOmdON33ACGlQ9fU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=IwGtn+KCXsIr/Blj7U2RW5OoIZvykj2dnYERs9Qwyu6vUDXcWx14KfUJKKCzx/CZ5Lhj6SmbI/axr2GvnJylCPpM/RQlCmgQMEGV+tAOqMXVlmwIaGUqn1eS6vUy8JFeNQcKf1aMlbGoW+gMPzibozlpAebCh79XhPe62onkgqo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b=j9ecNe94; arc=none smtp.client-ip=5.135.140.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cjdns.fr header.i=@cjdns.fr header.b="j9ecNe94" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 173DE286152; Mon, 9 Mar 2026 14:19:13 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1773062357; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=AsslNjPsniHPFq7y9ACqeRGOIicsFNpWA+I3qRFhHu8=; b=j9ecNe94U9Em4IEwzKUh0fU8VAQGLclzvHLaHHqfT106fFGiQDskAYkhTzaE1I6qjgyzGB fzHSl3OV+SjCc2QfXwjyk3yMQLg7T39ghqRKxskqHiybQKxgOfaq5qCLdF/Ewkkym92M4i D9RG+xHxpH0Rcbc7ezS0pZE4VKZJpacQjXW291iNDzVEpnLXuikzBcl2FFHwLxgwYFWxMF RphLbS4y7iN4bji5qazjWyDImLHqnPZ1tXdm1UYNaVs6l13v8UoCR5wmGIbMJWqPjr5MfE SDf5XydOSUjXeliTSKntn/ovIe2m9Wdk7LS6oGl7bpbcJ8nEHlAZkjr2ABmwDw== From: Caleb James DeLisle To: linux-mips@vger.kernel.org Cc: naseefkm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, cjd@cjdns.fr, tsbogend@alpha.franken.de, ryder.lee@mediatek.com, jianjun.wang@mediatek.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, bhelgaas@google.com, vkoul@kernel.org, neil.armstrong@linaro.org, p.zabel@pengutronix.de, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, nbd@nbd.name, ansuelsmth@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 8/8] mips: dts: Add PCIe to EcoNet EN751221 Date: Mon, 9 Mar 2026 13:18:18 +0000 Message-Id: <20260309131818.74467-9-cjd@cjdns.fr> In-Reply-To: <20260309131818.74467-1-cjd@cjdns.fr> References: <20260309131818.74467-1-cjd@cjdns.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" Add PCIe based on EN7528 PCIe driver, also add two MT76 wifi devices to SmartFiber XP8421-B. Signed-off-by: Caleb James DeLisle --- arch/mips/boot/dts/econet/en751221.dtsi | 114 ++++++++++++++++++ .../econet/en751221_smartfiber_xp8421-b.dts | 21 ++++ arch/mips/econet/Kconfig | 2 + 3 files changed, 137 insertions(+) diff --git a/arch/mips/boot/dts/econet/en751221.dtsi b/arch/mips/boot/dts/e= conet/en751221.dtsi index 2abeef5b744a..72cb65654c34 100644 --- a/arch/mips/boot/dts/econet/en751221.dtsi +++ b/arch/mips/boot/dts/econet/en751221.dtsi @@ -1,6 +1,8 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /dts-v1/; =20 +#include + / { compatible =3D "econet,en751221"; #address-cells =3D <1>; @@ -30,6 +32,30 @@ cpuintc: interrupt-controller { #interrupt-cells =3D <1>; }; =20 + chip_scu: syscon@1fa20000 { + compatible =3D "econet,en751221-chip-scu", "syscon"; + reg =3D <0x1fa20000 0x388>; + }; + + pcie_phy1: pcie-phy@1fac0000 { + compatible =3D "econet,en751221-pcie-gen2"; + reg =3D <0x1fac0000 0x1000>; + #phy-cells =3D <0>; + }; + + pcie_phy0: pcie-phy@1faf2000 { + compatible =3D "econet,en751221-pcie-gen1"; + reg =3D <0x1faf2000 0x1000>; + #phy-cells =3D <0>; + }; + + scuclk: clock-controller@1fb00000 { + compatible =3D "econet,en751221-scu"; + reg =3D <0x1fb00000 0x970>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + intc: interrupt-controller@1fb40000 { compatible =3D "econet,en751221-intc"; reg =3D <0x1fb40000 0x100>; @@ -41,6 +67,94 @@ intc: interrupt-controller@1fb40000 { econet,shadow-interrupts =3D <7 2>, <8 3>, <13 12>, <30 29>; }; =20 + pciecfg: pciecfg@1fb80000 { + compatible =3D "mediatek,generic-pciecfg", "syscon"; + reg =3D <0x1fb80000 0x1000>; + }; + + pcie0: pcie@1fb81000 { + compatible =3D "econet,en7528-pcie"; + device_type =3D "pci"; + reg =3D <0x1fb81000 0x1000>; + reg-names =3D "port0"; + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + interrupt-parent =3D <&intc>; + interrupts =3D <23>; + interrupt-names =3D "pcie_irq"; + clocks =3D <&scuclk EN751221_CLK_PCIE>; + clock-names =3D "sys_ck0"; + phys =3D <&pcie_phy0>; + phy-names =3D "pcie-phy0"; + bus-range =3D <0x00 0xff>; + ranges =3D <0x01000000 0 0x00000000 0x1f600000 0 0x00008000>, + <0x82000000 0 0x20000000 0x20000000 0 0x08000000>; + status =3D "disabled"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + + slot0: pcie@0,0 { + reg =3D <0x0000 0 0 0 0>; + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie1: pcie@1fb83000 { + compatible =3D "econet,en7528-pcie"; + device_type =3D "pci"; + reg =3D <0x1fb83000 0x1000>; + reg-names =3D "port1"; + linux,pci-domain =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + interrupt-parent =3D <&intc>; + interrupts =3D <24>; + interrupt-names =3D "pcie_irq"; + clocks =3D <&scuclk EN751221_CLK_PCIE>; + clock-names =3D "sys_ck1"; + phys =3D <&pcie_phy1>; + phy-names =3D "pcie-phy1"; + bus-range =3D <0x00 0xff>; + ranges =3D <0x81000000 0 0x00000000 0x1f608000 0 0x00008000>, + <0x82000000 0 0x28000000 0x28000000 0 0x08000000>; + status =3D "disabled"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + + slot1: pcie@1,0 { + reg =3D <0x0800 0 0 0 0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + uart: serial@1fbf0000 { compatible =3D "ns16550"; reg =3D <0x1fbf0000 0x30>; diff --git a/arch/mips/boot/dts/econet/en751221_smartfiber_xp8421-b.dts b/a= rch/mips/boot/dts/econet/en751221_smartfiber_xp8421-b.dts index 8223c5bce67f..c633bf73add6 100644 --- a/arch/mips/boot/dts/econet/en751221_smartfiber_xp8421-b.dts +++ b/arch/mips/boot/dts/econet/en751221_smartfiber_xp8421-b.dts @@ -17,3 +17,24 @@ chosen { linux,usable-memory-range =3D <0x00020000 0x1bfe0000>; }; }; + +&pcie0 { + status =3D "okay"; +}; +&slot0 { + wifi@0,0 { + /* MT7612E */ + compatible =3D "mediatek,mt76"; + reg =3D <0x0000 0 0 0 0>; + }; +}; +&pcie1 { + status =3D "okay"; +}; +&slot1 { + wifi@0,0 { + /* MT7592 */ + compatible =3D "mediatek,mt76"; + reg =3D <0x0000 0 0 0 0>; + }; +}; diff --git a/arch/mips/econet/Kconfig b/arch/mips/econet/Kconfig index fd69884cc9a8..b37b9d25d5a4 100644 --- a/arch/mips/econet/Kconfig +++ b/arch/mips/econet/Kconfig @@ -13,7 +13,9 @@ choice bool "EN751221 family" select COMMON_CLK select ECONET_EN751221_INTC + select HAVE_PCI select IRQ_MIPS_CPU + select PCI_DRIVERS_GENERIC select SMP select SMP_UP select SYS_SUPPORTS_SMP --=20 2.39.5