From nobody Thu Apr 2 12:35:33 2026 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BBC63ACA5E; Mon, 9 Mar 2026 12:05:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773057933; cv=none; b=V+i7Finu2ZeDf2PbWsmDSUBfDADutfR6qx0dfn2WxBx2T7WxoV+K7CeUa/pE5kfJA/K12Tv0ebg3qrYbYBg4LCk0o1CI2KrFDU0qsnZKOMAr8wOjEkLCHhxDB4NmV/uHUDpFVDh/sN+WzN0jbYHXzVv5t2Xu9Rr596o1AsVFcE0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773057933; c=relaxed/simple; bh=yy4EqIVDDj+an7aMIZ0jbyCSJDgvKGKiZ5herPmzJw8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uyfhxFa+7MkHVEupNenLBx5MwiJVbJ33aPJp2BEILhyMU0mteMCocUubTl6Xz0/MjSABEmpEZBRoUtc8BW6gt4cPGAJ0y42ZJodO0HZwoRuF2RhXzRA8NoeQEI399x4vY1nmlaIlZ3QwCT1J+CXNMkb0LuQghrqIs92Dq6JzZC0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=tCshxbpn; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="tCshxbpn" X-UUID: 3e85a8fc1bb011f1a39cd589f645bc18-20260309 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=jpfPzB9CGeEzDJ3hnSG8fv+pZKTEiqaxkUJRxUt0HJY=; b=tCshxbpnpFbuKrN3VeBk7WGyZN6LdqpsRXAoUBow47O9ZzvSQNXJkkIeSH7BRlvA9jW2vptfvHI4xXHPXWR6Hqo2ongC+9ohvBGAF/mT9ilp9ukI4N/UaUvtE2OSgfwoq7L8MWGZCJphjgEyWOG0JrGwy2WljlyVMJyiaki92RM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.11,REQID:a3e5da77-30cf-41a3-9e47-936de98460b5,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:89c9d04,CLOUDID:16de085c-a957-4259-bcca-d3af718d7034,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:-1,COL:0,OSI :0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 3e85a8fc1bb011f1a39cd589f645bc18-20260309 Received: from mtkmbs09n1.mediatek.inc [(172.21.101.35)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1677610078; Mon, 09 Mar 2026 20:05:20 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Mon, 9 Mar 2026 20:05:18 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Mon, 9 Mar 2026 20:05:18 +0800 From: irving.ch.lin To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Richard Cochran , Bartosz Golaszewski , Chen-Yu Tsai , Miles Chen CC: , , , , , , , Qiqi Wang , , , , Subject: [PATCH v6 09/18] clk: mediatek: Add MT8189 dbgao clock support Date: Mon, 9 Mar 2026 20:04:51 +0800 Message-ID: <20260309120512.3624804-10-irving-ch.lin@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20260309120512.3624804-1-irving-ch.lin@mediatek.com> References: <20260309120512.3624804-1-irving-ch.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Irving-CH Lin Add support for the MT8189 dbgao clock controller, which provides clock gate control for debug-system. Signed-off-by: Irving-CH Lin --- drivers/clk/mediatek/Kconfig | 10 +++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-dbgao.c | 94 +++++++++++++++++++++++++ 3 files changed, 105 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8189-dbgao.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 0665255a29fd..89f68cb56bb3 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -850,6 +850,16 @@ config COMMON_CLK_MT8189_CAM that relies on this SoC and you want to control its clocks, say Y or M to include this driver in your kernel build. =20 +config COMMON_CLK_MT8189_DBGAO + tristate "Clock driver for MediaTek MT8189 debug ao" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this to support the clock management for the debug function + on MediaTek MT8189 SoCs. This includes enabling and disabling + vcore debug system clocks. If you want to control its clocks, say Y or M + to include this driver in your kernel build. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 95a8f4ae05ee..eabe2cab4b8d 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -127,6 +127,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189) +=3D clk-mt8189-apmixed= sys.o clk-mt8189-topckgen.o clk-mt8189-vlpckgen.o clk-mt8189-vlpcfg.o obj-$(CONFIG_COMMON_CLK_MT8189_BUS) +=3D clk-mt8189-bus.o obj-$(CONFIG_COMMON_CLK_MT8189_CAM) +=3D clk-mt8189-cam.o +obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) +=3D clk-mt8189-dbgao.o obj-$(CONFIG_COMMON_CLK_MT8192) +=3D clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) +=3D clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) +=3D clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-dbgao.c b/drivers/clk/mediatek= /clk-mt8189-dbgao.c new file mode 100644 index 000000000000..543321ae5e65 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-dbgao.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs dbgao_cg_regs =3D { + .set_ofs =3D 0x70, + .clr_ofs =3D 0x70, + .sta_ofs =3D 0x70, +}; + +#define GATE_DBGAO(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &dbgao_cg_regs, _shift, &mtk_clk_gate_ops_n= o_setclr_inv) + +static const struct mtk_gate dbgao_clks[] =3D { + GATE_DBGAO(CLK_DBGAO_ATB_EN, "dbgao_atb_en", "atb_sel", 0), +}; + +static const struct mtk_clk_desc dbgao_mcd =3D { + .clks =3D dbgao_clks, + .num_clks =3D ARRAY_SIZE(dbgao_clks), +}; + +static const struct mtk_gate_regs dem0_cg_regs =3D { + .set_ofs =3D 0x2c, + .clr_ofs =3D 0x2c, + .sta_ofs =3D 0x2c, +}; + +static const struct mtk_gate_regs dem1_cg_regs =3D { + .set_ofs =3D 0x30, + .clr_ofs =3D 0x30, + .sta_ofs =3D 0x30, +}; + +static const struct mtk_gate_regs dem2_cg_regs =3D { + .set_ofs =3D 0x70, + .clr_ofs =3D 0x70, + .sta_ofs =3D 0x70, +}; + +#define GATE_DEM0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &dem0_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr_inv) + +#define GATE_DEM1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &dem1_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr_inv) + +#define GATE_DEM2(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &dem2_cg_regs, _shift, &mtk_clk_gate_ops_no= _setclr_inv) + +static const struct mtk_gate dem_clks[] =3D { + /* DEM0 */ + GATE_DEM0(CLK_DEM_BUSCLK_EN, "dem_busclk_en", "axi_sel", 0), + /* DEM1 */ + GATE_DEM1(CLK_DEM_SYSCLK_EN, "dem_sysclk_en", "axi_sel", 0), + /* DEM2 */ + GATE_DEM2(CLK_DEM_ATB_EN, "dem_atb_en", "atb_sel", 0), +}; + +static const struct mtk_clk_desc dem_mcd =3D { + .clks =3D dem_clks, + .num_clks =3D ARRAY_SIZE(dem_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_dbgao[] =3D { + { .compatible =3D "mediatek,mt8189-dbg-ao", .data =3D &dbgao_mcd }, + { .compatible =3D "mediatek,mt8189-dem", .data =3D &dem_mcd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_dbgao); + +static struct platform_driver clk_mt8189_dbgao_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8189-dbgao", + .of_match_table =3D of_match_clk_mt8189_dbgao, + }, +}; + +module_platform_driver(clk_mt8189_dbgao_drv); +MODULE_DESCRIPTION("MediaTek MT8189 dbgao system clocks driver"); +MODULE_LICENSE("GPL"); --=20 2.45.2