From nobody Thu Apr 9 12:58:42 2026 Received: from mta-64-227.siemens.flowmailer.net (mta-64-227.siemens.flowmailer.net [185.136.64.227]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCD503803C1 for ; Mon, 9 Mar 2026 10:09:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.64.227 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773050951; cv=none; b=ZUkaw99am0vLHG6qqqOidwc7XllUNn3+udfwjFg1treNGFZjKGtUW3lGIel5oXZMM8y5TxEjlnT3C2FlS2y0XG00hYJ5FuzH+fxZAI7QfOKcQqzPk6Da7tYQnGSsYIFY1cJm8F+ouWZVki/Bm9DZ4AOQ1ucYqDPuzJSocLGXDQQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773050951; c=relaxed/simple; bh=Eagp5Ejb5uSVhOilX6Bp+PTFyYqeR/ZTFOzn3ekyRUA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HUOCBovBGGsyiV5HLRDrb4dgcMzRHqmafF3tX3q6BrdB00i42w5W1KLc+qtRY1SpH9qfKsFPAkSydA00M102zM55gV+lQf6tE6fqo/olKCDNbMwmSRl75U4pPdCByP153PFFejZ0KRgqgtj4OShBRPMdejX7LhzxUpjEAxYIIQc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com; dkim=pass (2048-bit key) header.d=siemens.com header.i=alexander.sverdlin@siemens.com header.b=Hne3b6DA; arc=none smtp.client-ip=185.136.64.227 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=siemens.com header.i=alexander.sverdlin@siemens.com header.b="Hne3b6DA" Received: by mta-64-227.siemens.flowmailer.net with ESMTPSA id 2026030910085929eed5eccc000207b8 for ; Mon, 09 Mar 2026 11:08:59 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=alexander.sverdlin@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=RZC0oGY8rRbgVELeb0RF2I7S6lvyMsAod6S1xdxvL7A=; b=Hne3b6DAZ3NK7o4qoULldXDLZAioGXj00TLOCqWII02dWiqBeW9ksPi0pSmxSD2Y8cqUUM jEFdseMXYtuDX00HoVtHOUsEOLNoAxjIIETNjcPPRuvBOXCdeFdtEZ6Ls9uGwwZDOrOOeAst 4l0I2FqgW2J/Xc4EMQvPyopa+8IWLLnLvgkvsn8pwOplo666b9/cDTdBD9zrZ07k0lVa9AFE Kk02DYKSt9W8zWRLgFbp7GcSjg4nOpLRPQ3oJx79is4Dal2nOibKA0bdoBKcVVEtVb/t5QOn 7nqOIqncK0YiodNYDcST5ujYKsOYfZhVCJd8E5Ke2V8E00diV4FE2Clw==; From: "A. Sverdlin" To: linux-arm-kernel@lists.infradead.org Cc: Alexander Sverdlin , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Santosh Shilimkar , Andrew Davis , Jayesh Choudhary , Siddharth Vadapalli , Abraham I , Roger Quadros , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] soc: ti: k3-socinfo: Provide reset reason information Date: Mon, 9 Mar 2026 11:07:55 +0100 Message-ID: <20260309100800.1134701-4-alexander.sverdlin@siemens.com> In-Reply-To: <20260309100800.1134701-1-alexander.sverdlin@siemens.com> References: <20260309100800.1134701-1-alexander.sverdlin@siemens.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-456497:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Alexander Sverdlin Add reset_reason attribute decoging the RST_SRC register present in AM64x and later SoCs of K3 family. Textual representation of the bits was taken from the AM62x Processors Technical Reference Manual, except the POR, which is not signalled explicitly by the reset module. Signed-off-by: Alexander Sverdlin --- drivers/soc/ti/k3-socinfo.c | 88 +++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/drivers/soc/ti/k3-socinfo.c b/drivers/soc/ti/k3-socinfo.c index 676041879eca3..3736c982fd0c8 100644 --- a/drivers/soc/ti/k3-socinfo.c +++ b/drivers/soc/ti/k3-socinfo.c @@ -45,6 +45,8 @@ #define JTAG_ID_PARTNO_J722S 0xBBA0 #define JTAG_ID_PARTNO_AM62LX 0xBBA7 =20 +#define CTRL_MMR_RST_SRC 8 + static const struct k3_soc_id { unsigned int id; const char *family_name; @@ -123,6 +125,90 @@ static const struct regmap_config k3_chipinfo_regmap_c= fg =3D { .reg_stride =3D 4, }; =20 +static u32 k3_reset_source; +static const char *const k3_reset_sources[] =3D { + [0] =3D "Reset Caused by MCU Reset Pin", + [1] =3D "Power On Reset", /* Reserved in HW */ + [2] =3D "Main Reset Pin", + [4] =3D "Thermal Reset", + [8] =3D "Debug Subsystem Initiated Reset", + [12] =3D "SMS Cold Reset", + [13] =3D "SMS Warm Reset", + [16] =3D "Software Warm Reset", + [20] =3D "Software Main Warm Reset From MCU CTRL MMR", + [21] =3D "Software Main Warm Reset from MAIN CTRL MMR", + [22] =3D "Watchdog Initiated Reset", + [24] =3D "Software Main Power On Reset From MCU CTRL MMR", + [25] =3D "Software Main Power On Reset From MAIN CTRL MMR", + [30] =3D "Reset Caused by Main ESM Error", + [31] =3D "Reset Caused by MCU ESM Error", +}; + +static ssize_t reset_reason_show(struct device *dev, struct device_attribu= te *attr, char *buf) +{ + int ret, i; + int total =3D 0; + + for (i =3D ARRAY_SIZE(k3_reset_sources); i >=3D 0; i--) { + if (!k3_reset_sources[i] || !(k3_reset_source & BIT(i))) + continue; + + ret =3D sprintf(buf + total, "%s\n", k3_reset_sources[i]); + if (ret < 0) + return ret; + total +=3D ret; + /* Note that several reset sources may be active simultaneously */ + } + + return total; +} + +static DEVICE_ATTR_RO(reset_reason); + +static struct attribute *k3_soc_attrs[] =3D { + &dev_attr_reset_reason.attr, + NULL +}; + +ATTRIBUTE_GROUPS(k3_soc); + +static const struct of_device_id k3_rst_id_table[] =3D { + { + .compatible =3D "ti,am64-rst", + }, + {} +}; + +static void k3_reset_reason_read(struct soc_device_attribute *soc_dev_attr) +{ + struct device_node *node =3D of_find_matching_node(NULL, k3_rst_id_table); + struct regmap *regmap; + + /* AM65x/J721E do not have similar registers */ + if (!node) + return; + + regmap =3D device_node_to_regmap(node); + of_node_put(node); + if (IS_ERR(regmap)) { + pr_err("Cannot obtain %s regmap\n", k3_rst_id_table[0].compatible); + return; + } + + regmap_read(regmap, CTRL_MMR_RST_SRC, &k3_reset_source); + /* + * The register is only being cleared on POR, so we have to clear reset + * source of the current boot manually + */ + regmap_write(regmap, CTRL_MMR_RST_SRC, k3_reset_source); + + /* Simplify the code a bit and use HW-reserved bit for POR indication */ + if (!k3_reset_source) + k3_reset_source |=3D BIT(1); + + soc_dev_attr->custom_attr_group =3D k3_soc_groups[0]; +} + static int k3_chipinfo_probe(struct platform_device *pdev) { struct device_node *node =3D pdev->dev.of_node; @@ -183,6 +269,8 @@ static int k3_chipinfo_probe(struct platform_device *pd= ev) of_property_read_string(node, "model", &soc_dev_attr->machine); of_node_put(node); =20 + k3_reset_reason_read(soc_dev_attr); + soc_dev =3D soc_device_register(soc_dev_attr); if (IS_ERR(soc_dev)) { ret =3D PTR_ERR(soc_dev); --=20 2.52.0