From nobody Thu Apr 9 13:26:17 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5242134F270 for ; Mon, 9 Mar 2026 06:10:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773036603; cv=none; b=QMtVyrbN7MJLxC7jOHUKTUxsNEVlBIqmXDhZ+kga97DmTrKxBGboHIr9aU1bU5tsg807pyAiwjbrbEiJYUCgHxwLX7j0Fu+oOVbUfXNLAdUzW5yWDFMHYJGwYQZ3lz1tsrCYg+19E7Qxmj2NSN9sIAcQVgjqQoYHhQuJs4YW8Ys= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773036603; c=relaxed/simple; bh=DYREPAnsXoAIO6r1Fw6EsIIRjTHVUtTguaZ0vRiAhtk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=u8XbTu3KiamJCiuwXsTxcLJbW/W6aYQ8IkoK85Vkt5gHgQDeNR9UWwGs/kVJ39lee/6JCFYzXysLh861PmpM1iE1CAVtZ59nufVZRoDX+5Hrn0Q1SZEMiN0u1JL6rH7/sJrt+6EQ4S5yJQNUyDNljBv/81t/D+T6PDtYFTqZX50= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RyHrFyDN; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RyHrFyDN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1773036602; x=1804572602; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DYREPAnsXoAIO6r1Fw6EsIIRjTHVUtTguaZ0vRiAhtk=; b=RyHrFyDNC98EFgVMtfmW4B72yeiykNKFrKfa+xUi7KgyaqYejzxRi03C BUlH7ohWEI5U1r5FIFaJuJkOhpX+bJy/0zJZKM7sMOd/ND1EwwgiT5dqW Al1GKXb35SROifY2jx4fxdYh6+AIcTOgnMQxNR0xAiY+vaXo/rg4MTzQe Pre7fTxfK6TGzvdncIXQAneBfSZwY/P0mJONQ4hWxBeS+LqQkr95YJbcS g4waNvA1hItTDYm3sdKbitchOCQwPvqBBPc3z8Rg3ZNNAgWjVFtLO7Bbj 5ur15v0TqMQc3VqlWivuO5DRccAJEuvFQd7WiEEvX/i/MwRyknUnT5Xbd g==; X-CSE-ConnectionGUID: Pg9dlwqGTpSziijMA8PQJg== X-CSE-MsgGUID: VL/DbWiUQmWa4sMyS0+JXA== X-IronPort-AV: E=McAfee;i="6800,10657,11723"; a="73248306" X-IronPort-AV: E=Sophos;i="6.23,109,1770624000"; d="scan'208";a="73248306" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2026 23:10:00 -0700 X-CSE-ConnectionGUID: I7OP9EknQNKMwMswO7kOvA== X-CSE-MsgGUID: VXVbF9BVSRuQjTfqra2T4g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,109,1770624000"; d="scan'208";a="245669179" Received: from allen-box.sh.intel.com ([10.239.159.52]) by fmviesa001.fm.intel.com with ESMTP; 08 Mar 2026 23:09:57 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Kevin Tian , Jason Gunthorpe Cc: Dmytro Maluka , Samiullah Khawaja , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH 7/8] iommu/vt-d: Use intel_pasid_write() for pass-through setup Date: Mon, 9 Mar 2026 14:06:47 +0800 Message-ID: <20260309060648.276762-8-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260309060648.276762-1-baolu.lu@linux.intel.com> References: <20260309060648.276762-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refactor intel_pasid_setup_pass_through() to utilize the intel_pasid_write() helper. Move the pass-through setup implementation to the entry_sync library, where the target PASID entry is constructed locally and committed via the centralized intel_pasid_write() wrapper. Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.c | 12 +----------- drivers/iommu/intel/pasid.c | 26 ++++---------------------- 2 files changed, 5 insertions(+), 33 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index b98020ac9de2..f1f9fafd3984 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1248,16 +1248,6 @@ static void domain_context_clear_one(struct device_d= omain_info *info, u8 bus, u8 __iommu_flush_cache(iommu, context, sizeof(*context)); } =20 -static int domain_setup_passthrough(struct intel_iommu *iommu, - struct device *dev, ioasid_t pasid, - struct iommu_domain *old) -{ - if (old) - intel_pasid_tear_down_entry(iommu, dev, pasid, false); - - return intel_pasid_setup_pass_through(iommu, dev, pasid); -} - static int domain_setup_first_level(struct intel_iommu *iommu, struct dmar_domain *domain, struct device *dev, @@ -3848,7 +3838,7 @@ static int identity_domain_set_dev_pasid(struct iommu= _domain *domain, if (ret) return ret; =20 - ret =3D domain_setup_passthrough(iommu, dev, pasid, old); + ret =3D intel_pasid_setup_pass_through(iommu, dev, pasid); if (ret) { iopf_for_domain_replace(old, domain, dev); return ret; diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index 3084afb3d4a1..cb55ff422d7d 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -704,9 +704,6 @@ int intel_pasid_setup_dirty_tracking(struct intel_iommu= *iommu, static void pasid_pte_config_pass_through(struct intel_iommu *iommu, struct pasid_entry *pte, u16 did) { - lockdep_assert_held(&iommu->lock); - - pasid_clear_entry(pte); pasid_set_domain_id(pte, did); pasid_set_address_width(pte, iommu->agaw); pasid_set_translation_type(pte, PASID_ENTRY_PGTT_PT); @@ -718,27 +715,12 @@ static void pasid_pte_config_pass_through(struct inte= l_iommu *iommu, int intel_pasid_setup_pass_through(struct intel_iommu *iommu, struct device *dev, u32 pasid) { - u16 did =3D FLPT_DEFAULT_DID; - struct pasid_entry *pte; + struct pasid_entry new_pte =3D {0}; =20 - spin_lock(&iommu->lock); - pte =3D intel_pasid_get_entry(dev, pasid); - if (!pte) { - spin_unlock(&iommu->lock); - return -ENODEV; - } + iommu_group_mutex_assert(dev); + pasid_pte_config_pass_through(iommu, &new_pte, FLPT_DEFAULT_DID); =20 - if (pasid_pte_is_present(pte)) { - spin_unlock(&iommu->lock); - return -EBUSY; - } - - pasid_pte_config_pass_through(iommu, pte, did); - spin_unlock(&iommu->lock); - - pasid_flush_caches(iommu, pte, pasid, did); - - return 0; + return intel_pasid_write(iommu, dev, pasid, (u128 *)&new_pte); } =20 /* --=20 2.43.0