From nobody Thu Apr 9 13:26:18 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89BA534F270 for ; Mon, 9 Mar 2026 06:09:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773036598; cv=none; b=tbPOtMmpsasq2BdoObWZM2ACUpPHb6JyDny+yaJfErx3f/y5T09ebHCgKABjsPYzlPmVyoJQQX+RBuTgwn1Ti9TATwYuWwMiCY+eCTsL6BFa36WnvXugXYbrZ8AE79DypZuqSk+UwUfFLblukwZCwLnu2wgzl6tXWNl35Cvq7A0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773036598; c=relaxed/simple; bh=15cuIjNmzRhJGbEOchA9KN71cU83CCr7Ainh+JmETF4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jHt++w3gTGMrzITGVa0oE8bgMkApPL2QPWvHyof9kt/k3AD/vFvfOj0wCFOR7NQJzFBSRs5LcS9kaELkUvKbuAs5G3nXQtKFq97gIxhNKhSJa1QPXLpetpqiMtd186Cy3XgbrE6k7IhG39b5Uu/XOsVfIzYZbPYr9it2Z6nhP6o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=dcSQMCGQ; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="dcSQMCGQ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1773036598; x=1804572598; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=15cuIjNmzRhJGbEOchA9KN71cU83CCr7Ainh+JmETF4=; b=dcSQMCGQRSi73y4a7d1Z7N15AMOq0eevE3qfFgJjiexncwDCV+8iWcjm 3tg7vJVZy4FPWO8a9+mBmAKM4bYec2xqYqVfIqoDv9xcUH0j/gj4/t0Rd J1wwbn3zhzVwbjBfjNoRP0bP2Cj2dSOJ8TSTHE8wft3FuEvOY8J1E05UG kDVr1wWQDPb9QJUmt2PB0W4XVncnDWHUIUMjg+Ys/xnHMb7OxbbCBHDvE egI4I7wjTOYlDqTUVcQbX3gGbtDedWalxAUnpV0ltRmOSicqmF48pUcwK G+ZXwI150pnVngHv00W1tqv/9tnqp4CKCp7MAl2BR0EvasOTWKFXN3JU2 g==; X-CSE-ConnectionGUID: NKQxFtieTGi41Lc8iXSTuQ== X-CSE-MsgGUID: xYqUQWNDTVuIACf/8ohlwQ== X-IronPort-AV: E=McAfee;i="6800,10657,11723"; a="73248295" X-IronPort-AV: E=Sophos;i="6.23,109,1770624000"; d="scan'208";a="73248295" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2026 23:09:57 -0700 X-CSE-ConnectionGUID: QjNyrwwFTI2k3U1exs2qbQ== X-CSE-MsgGUID: WhLy3t6GSqK+lBkjuDwqJg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,109,1770624000"; d="scan'208";a="245669174" Received: from allen-box.sh.intel.com ([10.239.159.52]) by fmviesa001.fm.intel.com with ESMTP; 08 Mar 2026 23:09:55 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Kevin Tian , Jason Gunthorpe Cc: Dmytro Maluka , Samiullah Khawaja , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH 6/8] iommu/vt-d: Use intel_pasid_write() for second-stage setup Date: Mon, 9 Mar 2026 14:06:46 +0800 Message-ID: <20260309060648.276762-7-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260309060648.276762-1-baolu.lu@linux.intel.com> References: <20260309060648.276762-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refactor intel_pasid_setup_second_level() to utilize the intel_pasid_write() helper. Similar to the first-stage setup, moves the second stage setup logic to the entry_sync library by constructing the target PASID entry in a local buffer and committing it via intel_pasid_write(). Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.c | 19 ++++--------------- drivers/iommu/intel/pasid.c | 26 ++++---------------------- 2 files changed, 8 insertions(+), 37 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index db5e8dad50dc..b98020ac9de2 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -1248,17 +1248,6 @@ static void domain_context_clear_one(struct device_d= omain_info *info, u8 bus, u8 __iommu_flush_cache(iommu, context, sizeof(*context)); } =20 -static int domain_setup_second_level(struct intel_iommu *iommu, - struct dmar_domain *domain, - struct device *dev, ioasid_t pasid, - struct iommu_domain *old) -{ - if (old) - intel_pasid_tear_down_entry(iommu, dev, pasid, false); - - return intel_pasid_setup_second_level(iommu, domain, dev, pasid); -} - static int domain_setup_passthrough(struct intel_iommu *iommu, struct device *dev, ioasid_t pasid, struct iommu_domain *old) @@ -1323,8 +1312,8 @@ static int dmar_domain_attach_device(struct dmar_doma= in *domain, ret =3D domain_setup_first_level(iommu, domain, dev, IOMMU_NO_PASID, NULL); else if (intel_domain_is_ss_paging(domain)) - ret =3D domain_setup_second_level(iommu, domain, dev, - IOMMU_NO_PASID, NULL); + ret =3D intel_pasid_setup_second_level(iommu, domain, + dev, IOMMU_NO_PASID); else if (WARN_ON(true)) ret =3D -EINVAL; =20 @@ -3634,8 +3623,8 @@ static int intel_iommu_set_dev_pasid(struct iommu_dom= ain *domain, ret =3D domain_setup_first_level(iommu, dmar_domain, dev, pasid, old); else if (intel_domain_is_ss_paging(dmar_domain)) - ret =3D domain_setup_second_level(iommu, dmar_domain, - dev, pasid, old); + ret =3D intel_pasid_setup_second_level(iommu, dmar_domain, + dev, pasid); else if (WARN_ON(true)) ret =3D -EINVAL; =20 diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index 8ea1ac8cbf5e..3084afb3d4a1 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -590,10 +590,7 @@ static void pasid_pte_config_second_level(struct intel= _iommu *iommu, { struct pt_iommu_vtdss_hw_info pt_info; =20 - lockdep_assert_held(&iommu->lock); - pt_iommu_vtdss_hw_info(&domain->sspt, &pt_info); - pasid_clear_entry(pte); pasid_set_domain_id(pte, did); pasid_set_slptr(pte, pt_info.ssptptr); pasid_set_address_width(pte, pt_info.aw); @@ -611,9 +608,10 @@ int intel_pasid_setup_second_level(struct intel_iommu = *iommu, struct dmar_domain *domain, struct device *dev, u32 pasid) { - struct pasid_entry *pte; + struct pasid_entry new_pte =3D {0}; u16 did; =20 + iommu_group_mutex_assert(dev); =20 /* * If hardware advertises no support for second level @@ -626,25 +624,9 @@ int intel_pasid_setup_second_level(struct intel_iommu = *iommu, } =20 did =3D domain_id_iommu(domain, iommu); + pasid_pte_config_second_level(iommu, &new_pte, domain, did); =20 - spin_lock(&iommu->lock); - pte =3D intel_pasid_get_entry(dev, pasid); - if (!pte) { - spin_unlock(&iommu->lock); - return -ENODEV; - } - - if (pasid_pte_is_present(pte)) { - spin_unlock(&iommu->lock); - return -EBUSY; - } - - pasid_pte_config_second_level(iommu, pte, domain, did); - spin_unlock(&iommu->lock); - - pasid_flush_caches(iommu, pte, pasid, did); - - return 0; + return intel_pasid_write(iommu, dev, pasid, (u128 *)&new_pte); } =20 /* --=20 2.43.0