From nobody Thu Apr 9 13:26:19 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C2E934EF0E for ; Mon, 9 Mar 2026 06:09:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773036591; cv=none; b=VHpmARoobJAKnKgiXU6zeD3e2CWu7UTrY5kbjupeGDCIb0ysd+h7nA+mFqjt1goL6a5t3pVe/BWjUotemmmrW9W+L3qLSS4RuLD88qcIiVTbswf+81irV/1liAwPU0stCYU9Fonmt1GS0svIQ+FCj0eJZKNZmqYf87EnPP6P7Nc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773036591; c=relaxed/simple; bh=hh2uOktjahAxQZlSnY1/zk5puptgnvDXUVoF/w/9cGo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=X1eWnrEh1nQ19uAvgpnFqJ6NgLO3UQflelqEFHi4RBMbK38LG072ia5QOMP8XkGbVCMV/c7wD2IdWAmeOe/1uMscIhnFa1621M5ubUflY1ZRna1Zkt3FnjC0sS9ZxbCLCYrc//EcYWyAg3Phd89fVAPgxsniW2egI8GUMrFcbW0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=HIqeyBGz; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="HIqeyBGz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1773036591; x=1804572591; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hh2uOktjahAxQZlSnY1/zk5puptgnvDXUVoF/w/9cGo=; b=HIqeyBGzAXusQaSsIErv9iPYrl+3f0BsEvwHA/P4k0KwQ7keB0e+82I7 Uxe3wI5AqndAbF0GsRf6ByHLBfbGBAo3jRKiFQJd+z7h+mir6PPDL280Z puIjWFsiFEY+i4bmeQ8tQuST6R9KKvyy6TeOQClmKf7mX4wKNiGUg1jOf zjfzC1MX0PwwIOo687Le1LHpgoWlnkgUHIZA4mqC7s4gbXXuX6WpOMTXL v6gfn/ev081HBEPkVS9DHPj3R7fKtURtuFkTnVXSd9G95FNfXhaPn1yfA 22VOJijvfvvxWSNELGpuAVAzUeVFzu4+2B2adrGuLSZWk+GRrE04qdvDJ Q==; X-CSE-ConnectionGUID: SQU6DcipSSSWOPynhSMVCw== X-CSE-MsgGUID: NflHz0vZTPOW5jNar3SPnQ== X-IronPort-AV: E=McAfee;i="6800,10657,11723"; a="73248266" X-IronPort-AV: E=Sophos;i="6.23,109,1770624000"; d="scan'208";a="73248266" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Mar 2026 23:09:50 -0700 X-CSE-ConnectionGUID: zHm29YHkQK6tmG9AN4sSNg== X-CSE-MsgGUID: I+ZcCJjiS7WqFoB8xwLwTA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,109,1770624000"; d="scan'208";a="245669165" Received: from allen-box.sh.intel.com ([10.239.159.52]) by fmviesa001.fm.intel.com with ESMTP; 08 Mar 2026 23:09:48 -0700 From: Lu Baolu To: Joerg Roedel , Will Deacon , Robin Murphy , Kevin Tian , Jason Gunthorpe Cc: Dmytro Maluka , Samiullah Khawaja , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Lu Baolu Subject: [PATCH 3/8] iommu/vt-d: Require CMPXCHG16B for PASID support Date: Mon, 9 Mar 2026 14:06:43 +0800 Message-ID: <20260309060648.276762-4-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260309060648.276762-1-baolu.lu@linux.intel.com> References: <20260309060648.276762-1-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Intel IOMMU driver is moving toward using the generic entry_sync library for PASID table entry updates. This library requires 128-bit atomic write operations (cmpxchg128) to update 512-bit PASID entries in atomic quanta, ensuring the hardware never observes a torn entry. On x86_64, 128-bit atomicity is provided by the CMPXCHG16B instruction. Update the driver to: 1. Limit INTEL_IOMMU to X86_64, as 128-bit atomic operations are not available on 32-bit x86. 2. Gate pasid_supported() on the presence of X86_FEATURE_CX16. 3. Provide a boot-time warning if a PASID-capable IOMMU is detected on a CPU lacking the required instruction. Signed-off-by: Lu Baolu --- drivers/iommu/intel/Kconfig | 2 +- drivers/iommu/intel/iommu.h | 3 ++- drivers/iommu/intel/iommu.c | 4 ++++ 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/intel/Kconfig b/drivers/iommu/intel/Kconfig index 7fa31b9d4ef4..fee7fea9dfcb 100644 --- a/drivers/iommu/intel/Kconfig +++ b/drivers/iommu/intel/Kconfig @@ -11,7 +11,7 @@ config DMAR_DEBUG =20 config INTEL_IOMMU bool "Support for Intel IOMMU using DMA Remapping Devices" - depends on PCI_MSI && ACPI && X86 + depends on PCI_MSI && ACPI && X86_64 select IOMMU_API select GENERIC_PT select IOMMU_PT diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index 599913fb65d5..54b58d01d0cb 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -535,7 +535,8 @@ enum { =20 #define sm_supported(iommu) (intel_iommu_sm && ecap_smts((iommu)->ecap)) #define pasid_supported(iommu) (sm_supported(iommu) && \ - ecap_pasid((iommu)->ecap)) + ecap_pasid((iommu)->ecap) && \ + boot_cpu_has(X86_FEATURE_CX16)) #define ssads_supported(iommu) (sm_supported(iommu) && \ ecap_slads((iommu)->ecap) && \ ecap_smpwc(iommu->ecap)) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index ef7613b177b9..5369526e89d0 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -2647,6 +2647,10 @@ int __init intel_iommu_init(void) pr_info_once("IOMMU batching disallowed due to virtualization\n"); iommu_set_dma_strict(); } + + if (ecap_pasid(iommu->ecap) && !boot_cpu_has(X86_FEATURE_CX16)) + pr_info_once("PASID disabled due to lack of CMPXCHG16B support.\n"); + iommu_device_sysfs_add(&iommu->iommu, NULL, intel_iommu_groups, "%s", iommu->name); --=20 2.43.0