From nobody Thu Apr 2 03:24:59 2026 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 120BA392C4D for ; Mon, 9 Mar 2026 10:46:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773053177; cv=none; b=PYJKqZwE6GWt2qmP0Aiu9kqnPwEYLMDsqsCoU5g6JTcl/dcmp0oyQZyoA6NOGQY9mn85AXfVFfI9JpWw0K5xvzm4phkELw1FS2TJThBfhup6gC4xRBm07eZgDL9KDKNf7HaUIV4l27i9JAF4l0yyyjji6V38d+nbwxD5ihvDwLU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773053177; c=relaxed/simple; bh=eUAqIxEHyaYABwI+Jee8cvytUjiOhaL5zu6R0o6tHUI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TD4GjdncB6Zg/uMSx0FCpyuPuI6M/GW/3fZcIYfw9W6z+K8rGztK1/YZDVRUuvs+u/wHw1d3NUB0WPb1szQYcXRpln1RxtIO2k0bXbCLd6RB/Fam7tb8yF/lEC6zYRXAjd6vmP2/ACHlzrl7oLZcYlOKjf1pkAfNPtnyBrq6BeQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=ohtIjhKZ; arc=none smtp.client-ip=209.85.221.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="ohtIjhKZ" Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-439c5b40f60so4509432f8f.0 for ; Mon, 09 Mar 2026 03:46:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1773053173; x=1773657973; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=qfhSqbpupN4IJx0kwDfVRiWpYBljSt7jU/bnXNCnZpc=; b=ohtIjhKZGxRjsT7WlV6SfNEY4Ti1sAcDgYXqVUe4dGPm/hPtXgJlqs0S6uj0Yva9Ti e2z5Phpkv3eO7mSOVCP79gcAlILBmWq/AAF7auX/uOh+Yqp95sYPYIF6zCfoYDqCEJDI Qbkias4kVi+1LV7M5dGHEyZ/GfwwUEY6J91FkUzLvYpFEknLMZL7FgYmqKJ6jzG+kwTG qTatqp04GTPIS4y5xeb4ghYlUH6WMpk8rB8fQfmwr/p1sOpwoAYla/PgnY6uKb/o9NJz uDHlqJD8utsj/0cgq2T+tqf9bzd9HktfMyXX7wgMBks6NQI14VqGT1DAXdUXDHPB5zoy 3TrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773053173; x=1773657973; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=qfhSqbpupN4IJx0kwDfVRiWpYBljSt7jU/bnXNCnZpc=; b=F+7PQFsOyFMPm3FWxokl1m1MJZyPmyB8ZJb+L/z4l49ooA28SVsWVVcTEhyz/RYbID OEvdeFGTISFww6YHvB18l0KyVoiDdvil/ZVnnU2xeF11Tiosja0JgpSG3IXm+BOrRuLW G2HwfRZr5MuJ98Z0rw/rSvAcUdJjlMKigohxxujZh/SVsjM7OQ8cpt3J50xo6vIyjfUd m6S/Tx/zSYAaZP0quTEN87LqJnVO9TnpGoVkBFsIEyBhHz58s+z0Mx4gGugG8FMAWa+J AGqd8dMItNR0G9QDJ7ouf8TfsFVyDIWrTuHEH+ID+G/zxqW4TLBsBRGgY3SxfA3yzgRu tvuQ== X-Forwarded-Encrypted: i=1; AJvYcCVD3beA7ULxp+iylLDJRbl0J9lheH3HFpI9TyvWd7JwQc5hYjqxVq+zH+mIFVKV5rt5YeQig1TWtGe7DZQ=@vger.kernel.org X-Gm-Message-State: AOJu0Yz8HDas/iMmkuRrddjGZCJDtbMyW5xME5AfXfCA2vScXqTpWO++ i/X5xhbaPf/EWV5u6KNK15cP9wr4g/RpxN2bqmJ/R2D16XN0IIPEckjPLjgkoEfdqEo= X-Gm-Gg: ATEYQzxs9GOyyTWYhjlBIBL5zjeZY9as1g10DbvVuJaBU3gMOA9i4TFCK40wZsxX3bM Ez1DLI/22Dsm77FlypDcYJEZ64McE5kJxs+QfjC+yZ5ZIUdLxtdO9RV9DuDCEHkZ1Waw8J9gKAL mJBRyq7cNoRTjq3TWrZJH1VMFA7gYXD3g/M9otDF0w/aJExNP37krQGLufGU3Ka78bpSjOEizal PG7WWLkRTjvyTRZeKTLPbxBDDyiShLgkiZJIrc34nKTNweRIXeOKaPWcIpM+4X2/zb/63XsGzpx gMMr7s7vZbKLyerjdWaj2WR8iaS2JkRH/FtR3gdGgyEdCFcd4qfUuZ1FCr/34DN6EbApd1ha8x5 KkgfzoyEQr3meM6EypSaw+bOksvcbCq9femhkdppJ35i9mypDaayUz9b2SvdrUUcrjVtaBWH/KW TM5RSXWxEdjFV2tby2/zSC X-Received: by 2002:a05:6000:2003:b0:439:a72e:bb1f with SMTP id ffacd0b85a97d-439da683f72mr17751338f8f.50.1773053173240; Mon, 09 Mar 2026 03:46:13 -0700 (PDT) Received: from localhost ([2001:4090:a244:8139:5278:cf5a:3494:5e80]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439dad8da01sm27057106f8f.1.2026.03.09.03.46.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Mar 2026 03:46:12 -0700 (PDT) From: "Markus Schneider-Pargmann (TI.com)" Date: Mon, 09 Mar 2026 11:45:48 +0100 Subject: [PATCH v4 3/3] clocksource/drivers/timer-ti-dm: Add clockevent support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260309-topic-ti-dm-clkevt-v6-16-v4-3-bb8d2a04c45e@baylibre.com> References: <20260309-topic-ti-dm-clkevt-v6-16-v4-0-bb8d2a04c45e@baylibre.com> In-Reply-To: <20260309-topic-ti-dm-clkevt-v6-16-v4-0-bb8d2a04c45e@baylibre.com> To: Daniel Lezcano , Thomas Gleixner Cc: Vishal Mahaveer , Kevin Hilman , Dhruva Gole , Sebin Francis , Kendall Willis , Akashdeep Kaur , linux-kernel@vger.kernel.org, "Markus Schneider-Pargmann (TI.com)" X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6712; i=msp@baylibre.com; h=from:subject:message-id; bh=eUAqIxEHyaYABwI+Jee8cvytUjiOhaL5zu6R0o6tHUI=; b=owGbwMvMwCXWejAsc4KoVzDjabUkhsx1S179OuZ5bcUx8y1p1n8k7R+f2zzDM2nl6a6buzS1p p+6ncx0qKOUhUGMi0FWTJGlMzE07b/8zmPJi5ZthpnDygQyhIGLUwAmUryc4Q+HTEv5uf5HT7+t T20wP/F2I6vriQWdDT93Moc8+XtPcPZXhv+JRRc3Vz3ddDdpfdy3EC+bv1fd166IkWnbG7CrtZT 7y2dmAA== X-Developer-Key: i=msp@baylibre.com; a=openpgp; fpr=BADD88DB889FDC3E8A3D5FE612FA6A01E0A45B41 Add support for using the TI Dual-Mode Timer for clockevents. The second always on device with the "ti,timer-alwon" property is selected to be used for clockevents. The first one is used as clocksource. This allows clockevents to be setup independently of the CPU. Signed-off-by: Markus Schneider-Pargmann (TI.com) --- drivers/clocksource/timer-ti-dm.c | 138 ++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 133 insertions(+), 5 deletions(-) diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-= ti-dm.c index 75f38394e2598d76c41dd2b250c0c42f9f48bbe0..cefed71ac243e86e951405e5080= 1239e35abe290 100644 --- a/drivers/clocksource/timer-ti-dm.c +++ b/drivers/clocksource/timer-ti-dm.c @@ -21,8 +21,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -157,7 +159,14 @@ struct dmtimer_clocksource { unsigned int loadval; }; =20 +struct omap_dm_timer_clockevent { + struct clock_event_device dev; + struct dmtimer *timer; + u32 period; +}; + static resource_size_t omap_dm_timer_clocksource_base; +static resource_size_t omap_dm_timer_clockevent_base; static void __iomem *omap_dm_timer_sched_clock_counter; =20 enum { @@ -1201,6 +1210,9 @@ static void omap_dm_timer_find_alwon(void) { struct device_node *np; =20 + if (omap_dm_timer_clocksource_base && omap_dm_timer_clockevent_base) + return; + for_each_matching_node(np, omap_timer_match) { struct resource res; =20 @@ -1213,13 +1225,22 @@ static void omap_dm_timer_find_alwon(void) if (of_address_to_resource(np, 0, &res)) continue; =20 - omap_dm_timer_clocksource_base =3D res.start; + if (!omap_dm_timer_clocksource_base) { + omap_dm_timer_clocksource_base =3D res.start; + continue; + } =20 - of_node_put(np); - return; + if (res.start !=3D omap_dm_timer_clocksource_base) { + omap_dm_timer_clockevent_base =3D res.start; + + of_node_put(np); + return; + } } =20 - omap_dm_timer_clocksource_base =3D RESOURCE_SIZE_MAX; + if (!omap_dm_timer_clocksource_base) + omap_dm_timer_clocksource_base =3D RESOURCE_SIZE_MAX; + omap_dm_timer_clockevent_base =3D RESOURCE_SIZE_MAX; } =20 static struct dmtimer_clocksource *omap_dm_timer_to_clocksource(struct clo= cksource *cs) @@ -1308,6 +1329,105 @@ static int omap_dm_timer_setup_clocksource(struct d= mtimer *timer) return 0; } =20 +static struct omap_dm_timer_clockevent *to_dm_timer_clockevent(struct cloc= k_event_device *evt) +{ + return container_of(evt, struct omap_dm_timer_clockevent, dev); +} + +static int omap_dm_timer_evt_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + struct omap_dm_timer_clockevent *clkevt =3D to_dm_timer_clockevent(evt); + struct dmtimer *timer =3D clkevt->timer; + + dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, 0xffffffff - cycles); + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, OMAP_TIMER_CTRL_ST); + + return 0; +} + +static int omap_dm_timer_evt_shutdown(struct clock_event_device *evt) +{ + struct omap_dm_timer_clockevent *clkevt =3D to_dm_timer_clockevent(evt); + struct dmtimer *timer =3D clkevt->timer; + + __omap_dm_timer_stop(timer); + + return 0; +} + +static int omap_dm_timer_evt_set_periodic(struct clock_event_device *evt) +{ + struct omap_dm_timer_clockevent *clkevt =3D to_dm_timer_clockevent(evt); + struct dmtimer *timer =3D clkevt->timer; + + omap_dm_timer_evt_shutdown(evt); + + omap_dm_timer_set_load(&timer->cookie, clkevt->period); + dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, clkevt->period); + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, + OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST); + + return 0; +} + +static irqreturn_t omap_dm_timer_evt_interrupt(int irq, void *dev_id) +{ + struct omap_dm_timer_clockevent *clkevt =3D dev_id; + struct dmtimer *timer =3D clkevt->timer; + + __omap_dm_timer_write_status(timer, OMAP_TIMER_INT_OVERFLOW); + + clkevt->dev.event_handler(&clkevt->dev); + + return IRQ_HANDLED; +} + +static int omap_dm_timer_setup_clockevent(struct dmtimer *timer) +{ + struct device *dev =3D &timer->pdev->dev; + struct omap_dm_timer_clockevent *clkevt; + int ret; + + clkevt =3D devm_kzalloc(dev, sizeof(*clkevt), GFP_KERNEL); + if (!clkevt) + return -ENOMEM; + + timer->reserved =3D 1; + clkevt->timer =3D timer; + + clkevt->dev.name =3D "omap_dm_timer"; + clkevt->dev.features =3D CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + clkevt->dev.rating =3D 300; + clkevt->dev.set_next_event =3D omap_dm_timer_evt_set_next_event; + clkevt->dev.set_state_shutdown =3D omap_dm_timer_evt_shutdown; + clkevt->dev.set_state_periodic =3D omap_dm_timer_evt_set_periodic; + clkevt->dev.set_state_oneshot =3D omap_dm_timer_evt_shutdown; + clkevt->dev.set_state_oneshot_stopped =3D omap_dm_timer_evt_shutdown; + clkevt->dev.tick_resume =3D omap_dm_timer_evt_shutdown; + clkevt->dev.cpumask =3D cpu_possible_mask; + clkevt->period =3D 0xffffffff - DIV_ROUND_CLOSEST(timer->fclk_rate, HZ); + + __omap_dm_timer_init_regs(timer); + __omap_dm_timer_stop(timer); + __omap_dm_timer_enable_posted(timer); + + ret =3D devm_request_irq(dev, timer->irq, omap_dm_timer_evt_interrupt, + IRQF_TIMER, "omap_dm_timer_clockevent", clkevt); + if (ret) { + dev_err(dev, "Failed to request interrupt: %d\n", ret); + return ret; + } + + __omap_dm_timer_int_enable(timer, OMAP_TIMER_INT_OVERFLOW); + + clockevents_config_and_register(&clkevt->dev, timer->fclk_rate, + 3, + 0xffffffff); + + return 0; +} + /** * omap_dm_timer_probe - probe function called for every registered device * @pdev: pointer to current timer platform device @@ -1324,7 +1444,7 @@ static int omap_dm_timer_probe(struct platform_device= *pdev) struct resource *res; int ret; =20 - if (!omap_dm_timer_clocksource_base) + if (!omap_dm_timer_clocksource_base || !omap_dm_timer_clockevent_base) omap_dm_timer_find_alwon(); =20 pdata =3D of_device_get_match_data(dev); @@ -1401,6 +1521,14 @@ static int omap_dm_timer_probe(struct platform_devic= e *pdev) =20 res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); =20 + if (omap_dm_timer_clockevent_base && res && + res->start =3D=3D omap_dm_timer_clockevent_base && + !IS_ERR_OR_NULL(timer->fclk)) { + ret =3D omap_dm_timer_setup_clockevent(timer); + if (ret) + return ret; + } + if (omap_dm_timer_clocksource_base && res && res->start =3D=3D omap_dm_timer_clocksource_base && !IS_ERR_OR_NULL(timer->fclk)) { --=20 2.53.0