From nobody Thu Apr 2 01:49:43 2026 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83F5B392C30 for ; Mon, 9 Mar 2026 10:46:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773053174; cv=none; b=GrUFWtvNnz2oXPSRbYRRTte89xVjFPD1yn8egbJfF27vUo4KU7EFWnBoUGWjwRj6cuC4lpq1tHi1uYx0eGurLMcs1hJ0vTGuJ+8DDzHaOT/+C4bGE5dW9srvguV/NrYkozGaARBdYvsjHsm1UibNfmzK9Ck1YoDY+FfaEasTWcs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773053174; c=relaxed/simple; bh=xDwa+yju+uELeFTZoiFSjSD7nBxKqIsZaotiZf1OjRA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=B4jHgZVIsSD4oPawjwgRofoJAwcAo8YARN040wg4mi39dtu+6TWpnJqA09727gMP/3rOriWTi533wKQnwV5UXTTURuvmcxylrXCgcagBpj8jPhvSWCn5dQV4Sxtuf3h9kpUTMzqzg/hbqU8tL7fY5Qer3A9Wn/CEJbv7qKtA7gw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=pPTxT1ev; arc=none smtp.client-ip=209.85.221.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="pPTxT1ev" Received: by mail-wr1-f45.google.com with SMTP id ffacd0b85a97d-439cb5af25bso1836941f8f.1 for ; Mon, 09 Mar 2026 03:46:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1773053171; x=1773657971; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=SGuSBsjeWyqsWDniaIhFJ9XSwVQus93E477T0cX6W3U=; b=pPTxT1ev8Kb2X891hoK1plJohzW3dST0Lmabh9BxkjyAZmhks6cSWvMUVLiXyfW5+P hiLlw4pvcuFA9NerAOYLzdGeLNLNaJLRmyhJzAeC1fuIkxjC7KYpNJ7OxSSPox8XlnDs OlqGUq4wFeoDatclK1fRiEosn0MzyoffMTYfhS2w0m7hddj/I+CZkovhee1cQr6QMjNp 5+azoa/wzgmLPC/2n58WtbK4ZJ0B33hnP7TtMA5COytWteTgpVrcJVkPjLthGr+u9O5r JLRtjTUi12MBDo0edOcrCcGQlRA82KgcIA00vYzcgIVWKuCSV9DxKVKsNrzIWirQgIJc zgyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773053171; x=1773657971; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=SGuSBsjeWyqsWDniaIhFJ9XSwVQus93E477T0cX6W3U=; b=YwqdD0mvgEj7qy8tck6CGvGkHCELqbWrYQEQ95wJUatMVMlhWUFQEc8TrgZfVsJdgl Jf9Q0uWiP9EAc7WIzUBnirotsMclFSdQ3cWxfMyMXwHeQD/FP9PyvT6viBbZidplyEsP lpCBCpipEdMYMitWQGVspWsRaBpofOYOCHkNvR7q1cSh/QqYxGmuJ5Io6kH1g9p3pAI3 hR0Dijj0YM5/Z6zXuqkgdduYOMn9jj11y5D+xAoZv1oJe8N4OuvOsVRefphgtM4T5bk+ JXtUwD88Z4EVBRsiROVpeM/DOEBb0fGT1nUHFmpJKk6nYZJpTFtx+LVDAfiQQ6CoCWba e4HQ== X-Forwarded-Encrypted: i=1; AJvYcCV46m8no6F+Y6VWDtLTTbmQF1mjgVAF5yZaoC3086XgIYfuEwjLHQF1KxbOTaDqw201+0i2SBd1u/e8nuE=@vger.kernel.org X-Gm-Message-State: AOJu0YwqeEZ0msILwmjIFIt9DyN8lJlCsWXa1/hUF/2+vbyQlPNXifpI x1JImph4+okYe+lxP/nmVnJifL69gpm1mICWsbkoRuj6jl+YNYYscpuV306Ml2VBWfo= X-Gm-Gg: ATEYQzyMLEA9SU4vKFeL49eki4GEui1hzi7BsqOHUghFYQj26hex9w+LyGc+XYivTHW j9IK3HPNjzU25aubWzjbwdgMJMG09qyGiMXcmaq5YrrY6io/SrOPr0BQjvWUC8LonpnqXOMkBRF Nut/k+EFVki6oYMVxmD5AzgOCpE6d1kmD4a9TFh/Hl9KskAiOzD5y3grCb8BtST52aJoM6CGKMz pj/dUg/X14xK7q+ehNiycONeCaa09f+4aKB4WkGFeSYEjO0tCE/w1cSkqvQBFqj7p0ylul4oN9F pd77fzU+TEURHXKAN0nGU6wDRNp2OxFHZ2A1PhaKS0t+wSsHZ01EgcYGCaAnmRi88q+4LgZMp/r ioAxpjleJmhauRpgTyO4jpQSB8qTcvboOvM+pTTNWvrU7Hw005I0d+jdjTNWLQkixH/Em39BlDC zQG+/Oujsnx+gwWUXUNZ6b X-Received: by 2002:a5d:64c9:0:b0:439:b440:b8b5 with SMTP id ffacd0b85a97d-439da86f760mr18128099f8f.43.1773053170389; Mon, 09 Mar 2026 03:46:10 -0700 (PDT) Received: from localhost ([2001:4090:a244:8139:5278:cf5a:3494:5e80]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439dad97be5sm26650328f8f.11.2026.03.09.03.46.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Mar 2026 03:46:10 -0700 (PDT) From: "Markus Schneider-Pargmann (TI.com)" Date: Mon, 09 Mar 2026 11:45:46 +0100 Subject: [PATCH v4 1/3] clocksource/drivers/timer-ti-dm: Fix property name in comment Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260309-topic-ti-dm-clkevt-v6-16-v4-1-bb8d2a04c45e@baylibre.com> References: <20260309-topic-ti-dm-clkevt-v6-16-v4-0-bb8d2a04c45e@baylibre.com> In-Reply-To: <20260309-topic-ti-dm-clkevt-v6-16-v4-0-bb8d2a04c45e@baylibre.com> To: Daniel Lezcano , Thomas Gleixner Cc: Vishal Mahaveer , Kevin Hilman , Dhruva Gole , Sebin Francis , Kendall Willis , Akashdeep Kaur , linux-kernel@vger.kernel.org, "Markus Schneider-Pargmann (TI.com)" X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1234; i=msp@baylibre.com; h=from:subject:message-id; bh=xDwa+yju+uELeFTZoiFSjSD7nBxKqIsZaotiZf1OjRA=; b=owGbwMvMwCXWejAsc4KoVzDjabUkhsx1Sx4+n2wftJi7WaitkWHzU2HPCf2vjKd+0GHvNPP5N LF4P+e3jlIWBjEuBlkxRZbOxNC0//I7jyUvWrYZZg4rE8gQBi5OAZjIlneMDKfVw3NcFcyT6ydd O6UkL775jcb2Iq+liw6d4bS4t+x2/TdGhvXTTNd/uudalTrRzvXJ77n7IusYg1rVpglOeq/87jB 3ORMA X-Developer-Key: i=msp@baylibre.com; a=openpgp; fpr=BADD88DB889FDC3E8A3D5FE612FA6A01E0A45B41 ti,always-on property doesn't exist. ti,timer-alwon is meant here. Fix this minor bug in the comment. Signed-off-by: Markus Schneider-Pargmann (TI.com) --- drivers/clocksource/timer-ti-dm-systimer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/timer-ti-dm-systimer.c b/drivers/clocksour= ce/timer-ti-dm-systimer.c index eb0dfe4b9b7caf31c21dd065a69f38641cb0c053..3804c1234522499bb43cf174afc= 017cedb79ea38 100644 --- a/drivers/clocksource/timer-ti-dm-systimer.c +++ b/drivers/clocksource/timer-ti-dm-systimer.c @@ -226,7 +226,7 @@ static bool __init dmtimer_is_preferred(struct device_n= ode *np) * Some omap3 boards with unreliable oscillator must not use the counter_3= 2k * or dmtimer1 with 32 KiHz source. Additionally, the boards with unreliab= le * oscillator should really set counter_32k as disabled, and delete dmtime= r1 - * ti,always-on property, but let's not count on it. For these quirky case= s, + * ti,timer-alwon property, but let's not count on it. For these quirky ca= ses, * we prefer using the always-on secure dmtimer12 with the internal 32 KiHz * clock as the clocksource, and any available dmtimer as clockevent. * --=20 2.53.0 From nobody Thu Apr 2 01:49:43 2026 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 940FF3939A8 for ; Mon, 9 Mar 2026 10:46:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773053175; cv=none; b=D8jpGe3iSI4Fjj1LVObJHei8qxbIY0xRBFqbOK0MkVW49ffge3bqGZzPLudzXbZ5c/rNdb3gpAsfcDxPKMUdBP8JbXCtIDlkgs++wNAPidZP0jeGw0QeAWin3ejs3tpqULouu46y3cVAwnxjzYAA3HfV+KFAOApAH1nYq2nyWeg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773053175; c=relaxed/simple; bh=/4+/I+xACo8o1pq1GNFp9mr9gtvBNDmBJ4CnJOiAlIM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Tjtmtdm8Qh2K4ESYDNcqr/b3HfEae2ueMZ+LXV6coRnyC715Jrl1Fe+KdZKxM18dJMepD58lELvkkwKq3X6CP23iOvsKMaenkpLHsMYGwTQ0FefniURlmtN5w5VbYhsSV6F+WL0xc5H45edw8uzJUG7f3S1ErIQq/tdjHZvkvts= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=WcmlIGWj; arc=none smtp.client-ip=209.85.221.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="WcmlIGWj" Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-439aeed8a5bso8833374f8f.3 for ; Mon, 09 Mar 2026 03:46:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1773053172; x=1773657972; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=037qXJLh1k8MKzhXahCvSNB8hzzf7Oq4rDLkvzKBXlg=; b=WcmlIGWjJB4fKApI4e3TLW19UgI05DA8MP1am4BwCpIH1ZgFSv0PX3DruX7gWazAN3 tSIIaxOzZO6JMkeHOeWGHtBdWK0Zfr4pbcyyA4VoC3JLeZHXY1vzEndeljYWj3n8H3X3 2FVr0X+mR8V0/9w4dG/AHG+7Z38nuEs63G9S8OxMk36b5Rys5G7ebIcc8pXR/DnQthCf zeCPmiWtj7mSP/+QVtdMoxS/v90C5FRvQxPaVovRtw+mLigAW6predt60vEQEmX7vP3f XAmJHN/WvHC39WxHi2S47pPlgpQYQXzFYEGnHAhkBzHFdW1azTLd87Z4y5EYLDqoyz9A zchQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773053172; x=1773657972; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=037qXJLh1k8MKzhXahCvSNB8hzzf7Oq4rDLkvzKBXlg=; b=mhciT+7cV5bPxW7RuVmQvaAOaqNmVBGRyZ7E0jLzTAdzmsrCAQVZbastcVWjTrpA9d WoGhWfweYIeXQiL6Jhk17Q5NeXlylFwn6Dg+1QkMF8STYS4RAYG44wFNAxg+MN/x2I4b xp+p7FynyynHXpPWYH+DIXkiUzZI91dArZEFZ7KaehFQxTFWkDUoZ5pHjUsew+FAflzV LwPbXY0WRDs+xMEn54jSxx381RAf7X1TlFTYOZ9HQW/NGPg6YrzNuDbOLhjlY5oBLGvW BiBsv77Ep9sm8YveXi+RoI71X99HYZdPrSOa0qmdOALlHwa9VKOjS87zLAGVI3J60GQb 9Suw== X-Forwarded-Encrypted: i=1; AJvYcCWAbVQYcdUTKK4WsQ13zjQt8tESHEtju9lrGVtAMMAHCPSIu2HsXgeFFISLywqyBcAsk3x0iaRTQxvBKu4=@vger.kernel.org X-Gm-Message-State: AOJu0YyQk7laJyHe9ftRDAApE2ShAwDl7WhOTVRdeNFlyjYryeQTeXrL hRsLZD7EZob0weCm6eNKD/vCc0KdEYkb7xKchvFAXWfwCkU6wRlrVLe+AfYSqxMmjr8= X-Gm-Gg: ATEYQzzf9g4b7uR4uQh//A447im01npX3z34saU9wiKrKpXqPao2gL+je5vRGJUfLSz zYpchKJYL0Oap+7PTxNh6a9c5aPQVvr+Imf5YkBWKWSEeiGYBS1NTEcDoASQEB5qpIA6WewDIMS l40VgHThAIcpYzmDvsysc3LYPwd9nuzWGfuTfi4dX6JKoKObghXMHpn0u7SSBqf36Cc6+e+Tzu3 CeVZPBCVhU1KzRqaXO9cLHQyHhnSW4V8aVnNGh456sN+lqk3QUg8/3YerlHfJcZfgRabW/WLXvj X0S/USLwsXz9DSKtGWOz4JAsnhC59TNnERAA/fzt+GyIWWayJvzc+/hvickMannaQBC2eniFrC3 siGIruJvUtk+ZQNkh7fPWabj79LqSvHcaiRdmJc/7zspTkcLCbmqLhvAfNLM2yuLUBMVW6+TnXY 0n5xmhMdBhjxb9g64AO5frlWCE9KQ9Amo= X-Received: by 2002:a05:6000:144c:b0:439:c4ea:41a0 with SMTP id ffacd0b85a97d-439da8a0402mr15885656f8f.59.1773053171783; Mon, 09 Mar 2026 03:46:11 -0700 (PDT) Received: from localhost ([2001:4090:a244:8139:5278:cf5a:3494:5e80]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439dada3b43sm26092345f8f.13.2026.03.09.03.46.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Mar 2026 03:46:11 -0700 (PDT) From: "Markus Schneider-Pargmann (TI.com)" Date: Mon, 09 Mar 2026 11:45:47 +0100 Subject: [PATCH v4 2/3] clocksource/drivers/timer-ti-dm: Add clocksource support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260309-topic-ti-dm-clkevt-v6-16-v4-2-bb8d2a04c45e@baylibre.com> References: <20260309-topic-ti-dm-clkevt-v6-16-v4-0-bb8d2a04c45e@baylibre.com> In-Reply-To: <20260309-topic-ti-dm-clkevt-v6-16-v4-0-bb8d2a04c45e@baylibre.com> To: Daniel Lezcano , Thomas Gleixner Cc: Vishal Mahaveer , Kevin Hilman , Dhruva Gole , Sebin Francis , Kendall Willis , Akashdeep Kaur , linux-kernel@vger.kernel.org, "Markus Schneider-Pargmann (TI.com)" X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6133; i=msp@baylibre.com; h=from:subject:message-id; bh=/4+/I+xACo8o1pq1GNFp9mr9gtvBNDmBJ4CnJOiAlIM=; b=owGbwMvMwCXWejAsc4KoVzDjabUkhsx1S54+Cj0yeX7EhEMcsRG9BSsyshr4FxyUeHfptqdef Xf5G/WIjlIWBjEuBlkxRZbOxNC0//I7jyUvWrYZZg4rE8gQBi5OAZhIqAYjQ+/CfRFpv5bmPPx2 TM4p6/2GsmtbY3VU7/ka2S0wvratJYbhfxlL9UETmebw9f0FqxYqeU1437h89/e9Ktz7pm5TnlX tyAQA X-Developer-Key: i=msp@baylibre.com; a=openpgp; fpr=BADD88DB889FDC3E8A3D5FE612FA6A01E0A45B41 Add support for using the TI Dual-Mode Timer as a clocksource. The driver automatically picks the first timer that is marked as always-on on with the "ti,timer-alwon" property to be the clocksource. The timer can then be used for CPU independent time keeping. Signed-off-by: Markus Schneider-Pargmann (TI.com) --- drivers/clocksource/timer-ti-dm.c | 137 ++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 137 insertions(+) diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-= ti-dm.c index 793e7cdcb1b16b58db3a81668e3c8144efc7baaf..75f38394e2598d76c41dd2b250c= 0c42f9f48bbe0 100644 --- a/drivers/clocksource/timer-ti-dm.c +++ b/drivers/clocksource/timer-ti-dm.c @@ -20,6 +20,7 @@ =20 #include #include +#include #include #include #include @@ -27,8 +28,10 @@ #include #include #include +#include #include #include +#include =20 #include #include @@ -148,6 +151,15 @@ static u32 omap_reserved_systimers; static LIST_HEAD(omap_timer_list); static DEFINE_SPINLOCK(dm_timer_lock); =20 +struct dmtimer_clocksource { + struct clocksource dev; + struct dmtimer *timer; + unsigned int loadval; +}; + +static resource_size_t omap_dm_timer_clocksource_base; +static void __iomem *omap_dm_timer_sched_clock_counter; + enum { REQUEST_ANY =3D 0, REQUEST_BY_ID, @@ -1185,6 +1197,117 @@ static const struct dev_pm_ops omap_dm_timer_pm_ops= =3D { =20 static const struct of_device_id omap_timer_match[]; =20 +static void omap_dm_timer_find_alwon(void) +{ + struct device_node *np; + + for_each_matching_node(np, omap_timer_match) { + struct resource res; + + if (!of_device_is_available(np)) + continue; + + if (!of_property_read_bool(np, "ti,timer-alwon")) + continue; + + if (of_address_to_resource(np, 0, &res)) + continue; + + omap_dm_timer_clocksource_base =3D res.start; + + of_node_put(np); + return; + } + + omap_dm_timer_clocksource_base =3D RESOURCE_SIZE_MAX; +} + +static struct dmtimer_clocksource *omap_dm_timer_to_clocksource(struct clo= cksource *cs) +{ + return container_of(cs, struct dmtimer_clocksource, dev); +} + +static u64 omap_dm_timer_read_cycles(struct clocksource *cs) +{ + struct dmtimer_clocksource *clksrc =3D omap_dm_timer_to_clocksource(cs); + struct dmtimer *timer =3D clksrc->timer; + + return (u64)__omap_dm_timer_read_counter(timer); +} + +static u64 notrace omap_dm_timer_read_sched_clock(void) +{ + /* Posted mode is not active here, so we can read directly */ + return readl_relaxed(omap_dm_timer_sched_clock_counter); +} + +static void omap_dm_timer_clocksource_suspend(struct clocksource *cs) +{ + struct dmtimer_clocksource *clksrc =3D omap_dm_timer_to_clocksource(cs); + struct dmtimer *timer =3D clksrc->timer; + + clksrc->loadval =3D __omap_dm_timer_read_counter(timer); + __omap_dm_timer_stop(timer); +} + +static void omap_dm_timer_clocksource_resume(struct clocksource *cs) +{ + struct dmtimer_clocksource *clksrc =3D omap_dm_timer_to_clocksource(cs); + struct dmtimer *timer =3D clksrc->timer; + + dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, clksrc->loadval); + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, OMAP_TIMER_CTRL_ST | OMAP_TIMER= _CTRL_AR); +} + +static void omap_dm_timer_clocksource_unregister(void *data) +{ + struct clocksource *cs =3D data; + + clocksource_unregister(cs); +} + +static int omap_dm_timer_setup_clocksource(struct dmtimer *timer) +{ + struct device *dev =3D &timer->pdev->dev; + struct dmtimer_clocksource *clksrc; + int err; + + __omap_dm_timer_init_regs(timer); + + timer->reserved =3D 1; + + clksrc =3D devm_kzalloc(dev, sizeof(*clksrc), GFP_KERNEL); + if (!clksrc) + return -ENOMEM; + + clksrc->timer =3D timer; + + clksrc->dev.name =3D "omap_dm_timer"; + clksrc->dev.rating =3D 300; + clksrc->dev.read =3D omap_dm_timer_read_cycles; + clksrc->dev.mask =3D CLOCKSOURCE_MASK(32); + clksrc->dev.flags =3D CLOCK_SOURCE_IS_CONTINUOUS; + clksrc->dev.suspend =3D omap_dm_timer_clocksource_suspend; + clksrc->dev.resume =3D omap_dm_timer_clocksource_resume; + + dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, 0); + dmtimer_write(timer, OMAP_TIMER_LOAD_REG, 0); + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, OMAP_TIMER_CTRL_ST | OMAP_TIMER= _CTRL_AR); + + omap_dm_timer_sched_clock_counter =3D timer->func_base + _OMAP_TIMER_COUN= TER_OFFSET; + sched_clock_register(omap_dm_timer_read_sched_clock, 32, timer->fclk_rate= ); + + err =3D clocksource_register_hz(&clksrc->dev, timer->fclk_rate); + if (err) + return dev_err_probe(dev, err, "Could not register as clocksource\n"); + + err =3D devm_add_action_or_reset(dev, omap_dm_timer_clocksource_unregiste= r, &clksrc->dev); + if (err) + return dev_err_probe(dev, err, "Could not register clocksource_unregiste= r action\n"); + + return 0; +} + /** * omap_dm_timer_probe - probe function called for every registered device * @pdev: pointer to current timer platform device @@ -1198,8 +1321,12 @@ static int omap_dm_timer_probe(struct platform_devic= e *pdev) struct dmtimer *timer; struct device *dev =3D &pdev->dev; const struct dmtimer_platform_data *pdata; + struct resource *res; int ret; =20 + if (!omap_dm_timer_clocksource_base) + omap_dm_timer_find_alwon(); + pdata =3D of_device_get_match_data(dev); if (!pdata) pdata =3D dev_get_platdata(dev); @@ -1272,6 +1399,16 @@ static int omap_dm_timer_probe(struct platform_devic= e *pdev) =20 timer->pdev =3D pdev; =20 + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (omap_dm_timer_clocksource_base && res && + res->start =3D=3D omap_dm_timer_clocksource_base && + !IS_ERR_OR_NULL(timer->fclk)) { + ret =3D omap_dm_timer_setup_clocksource(timer); + if (ret) + return ret; + } + pm_runtime_enable(dev); =20 if (!timer->reserved) { --=20 2.53.0 From nobody Thu Apr 2 01:49:43 2026 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 120BA392C4D for ; Mon, 9 Mar 2026 10:46:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773053177; cv=none; b=PYJKqZwE6GWt2qmP0Aiu9kqnPwEYLMDsqsCoU5g6JTcl/dcmp0oyQZyoA6NOGQY9mn85AXfVFfI9JpWw0K5xvzm4phkELw1FS2TJThBfhup6gC4xRBm07eZgDL9KDKNf7HaUIV4l27i9JAF4l0yyyjji6V38d+nbwxD5ihvDwLU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773053177; c=relaxed/simple; bh=eUAqIxEHyaYABwI+Jee8cvytUjiOhaL5zu6R0o6tHUI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TD4GjdncB6Zg/uMSx0FCpyuPuI6M/GW/3fZcIYfw9W6z+K8rGztK1/YZDVRUuvs+u/wHw1d3NUB0WPb1szQYcXRpln1RxtIO2k0bXbCLd6RB/Fam7tb8yF/lEC6zYRXAjd6vmP2/ACHlzrl7oLZcYlOKjf1pkAfNPtnyBrq6BeQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=ohtIjhKZ; arc=none smtp.client-ip=209.85.221.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="ohtIjhKZ" Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-439c5b40f60so4509432f8f.0 for ; Mon, 09 Mar 2026 03:46:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1773053173; x=1773657973; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=qfhSqbpupN4IJx0kwDfVRiWpYBljSt7jU/bnXNCnZpc=; b=ohtIjhKZGxRjsT7WlV6SfNEY4Ti1sAcDgYXqVUe4dGPm/hPtXgJlqs0S6uj0Yva9Ti e2z5Phpkv3eO7mSOVCP79gcAlILBmWq/AAF7auX/uOh+Yqp95sYPYIF6zCfoYDqCEJDI Qbkias4kVi+1LV7M5dGHEyZ/GfwwUEY6J91FkUzLvYpFEknLMZL7FgYmqKJ6jzG+kwTG qTatqp04GTPIS4y5xeb4ghYlUH6WMpk8rB8fQfmwr/p1sOpwoAYla/PgnY6uKb/o9NJz uDHlqJD8utsj/0cgq2T+tqf9bzd9HktfMyXX7wgMBks6NQI14VqGT1DAXdUXDHPB5zoy 3TrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773053173; x=1773657973; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=qfhSqbpupN4IJx0kwDfVRiWpYBljSt7jU/bnXNCnZpc=; b=F+7PQFsOyFMPm3FWxokl1m1MJZyPmyB8ZJb+L/z4l49ooA28SVsWVVcTEhyz/RYbID OEvdeFGTISFww6YHvB18l0KyVoiDdvil/ZVnnU2xeF11Tiosja0JgpSG3IXm+BOrRuLW G2HwfRZr5MuJ98Z0rw/rSvAcUdJjlMKigohxxujZh/SVsjM7OQ8cpt3J50xo6vIyjfUd m6S/Tx/zSYAaZP0quTEN87LqJnVO9TnpGoVkBFsIEyBhHz58s+z0Mx4gGugG8FMAWa+J AGqd8dMItNR0G9QDJ7ouf8TfsFVyDIWrTuHEH+ID+G/zxqW4TLBsBRGgY3SxfA3yzgRu tvuQ== X-Forwarded-Encrypted: i=1; AJvYcCVD3beA7ULxp+iylLDJRbl0J9lheH3HFpI9TyvWd7JwQc5hYjqxVq+zH+mIFVKV5rt5YeQig1TWtGe7DZQ=@vger.kernel.org X-Gm-Message-State: AOJu0Yz8HDas/iMmkuRrddjGZCJDtbMyW5xME5AfXfCA2vScXqTpWO++ i/X5xhbaPf/EWV5u6KNK15cP9wr4g/RpxN2bqmJ/R2D16XN0IIPEckjPLjgkoEfdqEo= X-Gm-Gg: ATEYQzxs9GOyyTWYhjlBIBL5zjeZY9as1g10DbvVuJaBU3gMOA9i4TFCK40wZsxX3bM Ez1DLI/22Dsm77FlypDcYJEZ64McE5kJxs+QfjC+yZ5ZIUdLxtdO9RV9DuDCEHkZ1Waw8J9gKAL mJBRyq7cNoRTjq3TWrZJH1VMFA7gYXD3g/M9otDF0w/aJExNP37krQGLufGU3Ka78bpSjOEizal PG7WWLkRTjvyTRZeKTLPbxBDDyiShLgkiZJIrc34nKTNweRIXeOKaPWcIpM+4X2/zb/63XsGzpx gMMr7s7vZbKLyerjdWaj2WR8iaS2JkRH/FtR3gdGgyEdCFcd4qfUuZ1FCr/34DN6EbApd1ha8x5 KkgfzoyEQr3meM6EypSaw+bOksvcbCq9femhkdppJ35i9mypDaayUz9b2SvdrUUcrjVtaBWH/KW TM5RSXWxEdjFV2tby2/zSC X-Received: by 2002:a05:6000:2003:b0:439:a72e:bb1f with SMTP id ffacd0b85a97d-439da683f72mr17751338f8f.50.1773053173240; Mon, 09 Mar 2026 03:46:13 -0700 (PDT) Received: from localhost ([2001:4090:a244:8139:5278:cf5a:3494:5e80]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439dad8da01sm27057106f8f.1.2026.03.09.03.46.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Mar 2026 03:46:12 -0700 (PDT) From: "Markus Schneider-Pargmann (TI.com)" Date: Mon, 09 Mar 2026 11:45:48 +0100 Subject: [PATCH v4 3/3] clocksource/drivers/timer-ti-dm: Add clockevent support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260309-topic-ti-dm-clkevt-v6-16-v4-3-bb8d2a04c45e@baylibre.com> References: <20260309-topic-ti-dm-clkevt-v6-16-v4-0-bb8d2a04c45e@baylibre.com> In-Reply-To: <20260309-topic-ti-dm-clkevt-v6-16-v4-0-bb8d2a04c45e@baylibre.com> To: Daniel Lezcano , Thomas Gleixner Cc: Vishal Mahaveer , Kevin Hilman , Dhruva Gole , Sebin Francis , Kendall Willis , Akashdeep Kaur , linux-kernel@vger.kernel.org, "Markus Schneider-Pargmann (TI.com)" X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6712; i=msp@baylibre.com; h=from:subject:message-id; bh=eUAqIxEHyaYABwI+Jee8cvytUjiOhaL5zu6R0o6tHUI=; b=owGbwMvMwCXWejAsc4KoVzDjabUkhsx1S179OuZ5bcUx8y1p1n8k7R+f2zzDM2nl6a6buzS1p p+6ncx0qKOUhUGMi0FWTJGlMzE07b/8zmPJi5ZthpnDygQyhIGLUwAmUryc4Q+HTEv5uf5HT7+t T20wP/F2I6vriQWdDT93Moc8+XtPcPZXhv+JRRc3Vz3ddDdpfdy3EC+bv1fd166IkWnbG7CrtZT 7y2dmAA== X-Developer-Key: i=msp@baylibre.com; a=openpgp; fpr=BADD88DB889FDC3E8A3D5FE612FA6A01E0A45B41 Add support for using the TI Dual-Mode Timer for clockevents. The second always on device with the "ti,timer-alwon" property is selected to be used for clockevents. The first one is used as clocksource. This allows clockevents to be setup independently of the CPU. Signed-off-by: Markus Schneider-Pargmann (TI.com) --- drivers/clocksource/timer-ti-dm.c | 138 ++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 133 insertions(+), 5 deletions(-) diff --git a/drivers/clocksource/timer-ti-dm.c b/drivers/clocksource/timer-= ti-dm.c index 75f38394e2598d76c41dd2b250c0c42f9f48bbe0..cefed71ac243e86e951405e5080= 1239e35abe290 100644 --- a/drivers/clocksource/timer-ti-dm.c +++ b/drivers/clocksource/timer-ti-dm.c @@ -21,8 +21,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -157,7 +159,14 @@ struct dmtimer_clocksource { unsigned int loadval; }; =20 +struct omap_dm_timer_clockevent { + struct clock_event_device dev; + struct dmtimer *timer; + u32 period; +}; + static resource_size_t omap_dm_timer_clocksource_base; +static resource_size_t omap_dm_timer_clockevent_base; static void __iomem *omap_dm_timer_sched_clock_counter; =20 enum { @@ -1201,6 +1210,9 @@ static void omap_dm_timer_find_alwon(void) { struct device_node *np; =20 + if (omap_dm_timer_clocksource_base && omap_dm_timer_clockevent_base) + return; + for_each_matching_node(np, omap_timer_match) { struct resource res; =20 @@ -1213,13 +1225,22 @@ static void omap_dm_timer_find_alwon(void) if (of_address_to_resource(np, 0, &res)) continue; =20 - omap_dm_timer_clocksource_base =3D res.start; + if (!omap_dm_timer_clocksource_base) { + omap_dm_timer_clocksource_base =3D res.start; + continue; + } =20 - of_node_put(np); - return; + if (res.start !=3D omap_dm_timer_clocksource_base) { + omap_dm_timer_clockevent_base =3D res.start; + + of_node_put(np); + return; + } } =20 - omap_dm_timer_clocksource_base =3D RESOURCE_SIZE_MAX; + if (!omap_dm_timer_clocksource_base) + omap_dm_timer_clocksource_base =3D RESOURCE_SIZE_MAX; + omap_dm_timer_clockevent_base =3D RESOURCE_SIZE_MAX; } =20 static struct dmtimer_clocksource *omap_dm_timer_to_clocksource(struct clo= cksource *cs) @@ -1308,6 +1329,105 @@ static int omap_dm_timer_setup_clocksource(struct d= mtimer *timer) return 0; } =20 +static struct omap_dm_timer_clockevent *to_dm_timer_clockevent(struct cloc= k_event_device *evt) +{ + return container_of(evt, struct omap_dm_timer_clockevent, dev); +} + +static int omap_dm_timer_evt_set_next_event(unsigned long cycles, + struct clock_event_device *evt) +{ + struct omap_dm_timer_clockevent *clkevt =3D to_dm_timer_clockevent(evt); + struct dmtimer *timer =3D clkevt->timer; + + dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, 0xffffffff - cycles); + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, OMAP_TIMER_CTRL_ST); + + return 0; +} + +static int omap_dm_timer_evt_shutdown(struct clock_event_device *evt) +{ + struct omap_dm_timer_clockevent *clkevt =3D to_dm_timer_clockevent(evt); + struct dmtimer *timer =3D clkevt->timer; + + __omap_dm_timer_stop(timer); + + return 0; +} + +static int omap_dm_timer_evt_set_periodic(struct clock_event_device *evt) +{ + struct omap_dm_timer_clockevent *clkevt =3D to_dm_timer_clockevent(evt); + struct dmtimer *timer =3D clkevt->timer; + + omap_dm_timer_evt_shutdown(evt); + + omap_dm_timer_set_load(&timer->cookie, clkevt->period); + dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, clkevt->period); + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, + OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST); + + return 0; +} + +static irqreturn_t omap_dm_timer_evt_interrupt(int irq, void *dev_id) +{ + struct omap_dm_timer_clockevent *clkevt =3D dev_id; + struct dmtimer *timer =3D clkevt->timer; + + __omap_dm_timer_write_status(timer, OMAP_TIMER_INT_OVERFLOW); + + clkevt->dev.event_handler(&clkevt->dev); + + return IRQ_HANDLED; +} + +static int omap_dm_timer_setup_clockevent(struct dmtimer *timer) +{ + struct device *dev =3D &timer->pdev->dev; + struct omap_dm_timer_clockevent *clkevt; + int ret; + + clkevt =3D devm_kzalloc(dev, sizeof(*clkevt), GFP_KERNEL); + if (!clkevt) + return -ENOMEM; + + timer->reserved =3D 1; + clkevt->timer =3D timer; + + clkevt->dev.name =3D "omap_dm_timer"; + clkevt->dev.features =3D CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + clkevt->dev.rating =3D 300; + clkevt->dev.set_next_event =3D omap_dm_timer_evt_set_next_event; + clkevt->dev.set_state_shutdown =3D omap_dm_timer_evt_shutdown; + clkevt->dev.set_state_periodic =3D omap_dm_timer_evt_set_periodic; + clkevt->dev.set_state_oneshot =3D omap_dm_timer_evt_shutdown; + clkevt->dev.set_state_oneshot_stopped =3D omap_dm_timer_evt_shutdown; + clkevt->dev.tick_resume =3D omap_dm_timer_evt_shutdown; + clkevt->dev.cpumask =3D cpu_possible_mask; + clkevt->period =3D 0xffffffff - DIV_ROUND_CLOSEST(timer->fclk_rate, HZ); + + __omap_dm_timer_init_regs(timer); + __omap_dm_timer_stop(timer); + __omap_dm_timer_enable_posted(timer); + + ret =3D devm_request_irq(dev, timer->irq, omap_dm_timer_evt_interrupt, + IRQF_TIMER, "omap_dm_timer_clockevent", clkevt); + if (ret) { + dev_err(dev, "Failed to request interrupt: %d\n", ret); + return ret; + } + + __omap_dm_timer_int_enable(timer, OMAP_TIMER_INT_OVERFLOW); + + clockevents_config_and_register(&clkevt->dev, timer->fclk_rate, + 3, + 0xffffffff); + + return 0; +} + /** * omap_dm_timer_probe - probe function called for every registered device * @pdev: pointer to current timer platform device @@ -1324,7 +1444,7 @@ static int omap_dm_timer_probe(struct platform_device= *pdev) struct resource *res; int ret; =20 - if (!omap_dm_timer_clocksource_base) + if (!omap_dm_timer_clocksource_base || !omap_dm_timer_clockevent_base) omap_dm_timer_find_alwon(); =20 pdata =3D of_device_get_match_data(dev); @@ -1401,6 +1521,14 @@ static int omap_dm_timer_probe(struct platform_devic= e *pdev) =20 res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); =20 + if (omap_dm_timer_clockevent_base && res && + res->start =3D=3D omap_dm_timer_clockevent_base && + !IS_ERR_OR_NULL(timer->fclk)) { + ret =3D omap_dm_timer_setup_clockevent(timer); + if (ret) + return ret; + } + if (omap_dm_timer_clocksource_base && res && res->start =3D=3D omap_dm_timer_clocksource_base && !IS_ERR_OR_NULL(timer->fclk)) { --=20 2.53.0