From nobody Thu Apr 9 10:29:38 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E41E93B531C; Mon, 9 Mar 2026 14:37:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773067073; cv=none; b=tEMiBRZwe3Mgp/bL+kLticAgEzuoRPA+jV/jl27nsAAiwnso7EmNd+Pa5K/B2WfjQT7YUH3WzVj6STe4KJSzPbc2OvGkQO0dx/pDnYYqQDgrpsGALvxmSPsbSwNNOQmC/9demtRL9cqletoDgB0wuQtepPXyyX72b3Gm215Sclg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773067073; c=relaxed/simple; bh=36gpqweckQuwig/VTbNshI12gGxp4mxbbamVYCxghKY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eLAgCmUFEVX/gNZkxE5IsZ18ie/biK/C0A7udFYkIoRAikcGI2h0juU8/kbLve0m2SNsN6Efnc8xURMjSqw3DnIAK5vtYKuXBT5ZFOjXvR0CHLwolxwQf8HY+zVtde37BxLo+/tQZJ5yLF8K76pEsDHTvm3cBTEL5R3QAiDmkVk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=LHdyTiGr; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="LHdyTiGr" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id BD5ECC42878; Mon, 9 Mar 2026 14:38:10 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 5E5F15FFB8; Mon, 9 Mar 2026 14:37:50 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A46F710369A24; Mon, 9 Mar 2026 15:37:48 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1773067069; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=s59uMvTFEuSOWz+yJUE8MxE0epOkB5QW4cN16/Yd3Vs=; b=LHdyTiGrYErClrAVzOJV8Cbx3M49OwUXcng7G+KUcOjeHJeaQT/emGTUOwOgMoGBEWx5kf enBY/sGQBV28uxBgfiC/sq57NN769wyl9yqL29T3URKYGdK0x1keukMFb3i7+QiztiAGHt Fb+81jSsqm4eXjHqI+V1fU9neDRuoz4ppubAJaS0qeWgMHrDcVIUfOjFR2tmJF1v8nLOk2 CqdgGJILCDeKYrl09XNB0DvzzLY34aDUEKoHdzqR4JC/bxKXe88TqP22Dxr1KpFHOWyBBv tdqI2B3ZivNUMOD+4xfntUxBPsAVt3qBcvfaAKrMQAHB68ZoCaZdiK6gDAkNzw== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Mon, 09 Mar 2026 15:37:34 +0100 Subject: [PATCH v9] phy: Add driver for EyeQ5 Ethernet PHY wrapper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260309-macb-phy-v9-1-5afd87d9db43@bootlin.com> References: <20260309-macb-phy-v9-0-5afd87d9db43@bootlin.com> In-Reply-To: <20260309-macb-phy-v9-0-5afd87d9db43@bootlin.com> To: Vinod Koul , Neil Armstrong Cc: linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Beno=C3=AEt_Monin?= , Tawfik Bayouk , Thomas Petazzoni , Luca Ceresoli , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.15-dev X-Last-TLS-Session-Version: TLSv1.3 EyeQ5 embeds a system-controller called OLB. It features many unrelated registers, and some of those are registers used to configure the integration of the RGMII/SGMII Cadence PHY used by MACB/GEM instances. Wrap in a neat generic PHY provider, exposing two PHYs with standard phy_init() / phy_set_mode() / phy_power_on() operations. Reviewed-by: Luca Ceresoli Signed-off-by: Th=C3=A9o Lebrun Reviewed-by: Vladimir Oltean --- MAINTAINERS | 1 + drivers/phy/Kconfig | 13 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-eyeq5-eth.c | 280 ++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 295 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 55af015174a5..6bc2ae3bbd4b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17812,6 +17812,7 @@ F: arch/mips/boot/dts/mobileye/ F: arch/mips/configs/eyeq5_defconfig F: arch/mips/mobileye/board-epm5.its.S F: drivers/clk/clk-eyeq.c +F: drivers/phy/phy-eyeq5-eth.c F: drivers/pinctrl/pinctrl-eyeq5.c F: drivers/reset/reset-eyeq.c F: include/dt-bindings/clock/mobileye,eyeq5-clk.h diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 3970aa1f300f..cb973a5c0d28 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -67,6 +67,19 @@ config PHY_CAN_TRANSCEIVER functional modes using gpios and sets the attribute max link rate, for CAN drivers. =20 +config PHY_EYEQ5_ETH + tristate "Ethernet PHY Driver on EyeQ5" + depends on OF + depends on MACH_EYEQ5 || COMPILE_TEST + select AUXILIARY_BUS + select GENERIC_PHY + default MACH_EYEQ5 + help + Enable this to support the Ethernet PHY integrated on EyeQ5. + It supports both RGMII and SGMII. Registers are located in a + shared register region called OLB. If M is selected, the + module will be called phy-eyeq5-eth. + config PHY_GOOGLE_USB tristate "Google Tensor SoC USB PHY driver" select GENERIC_PHY diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index f49d83f00a3d..05be5759cd10 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_GENERIC_PHY) +=3D phy-core.o obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) +=3D phy-core-mipi-dphy.o obj-$(CONFIG_PHY_AIROHA_PCIE) +=3D phy-airoha-pcie.o obj-$(CONFIG_PHY_CAN_TRANSCEIVER) +=3D phy-can-transceiver.o +obj-$(CONFIG_PHY_EYEQ5_ETH) +=3D phy-eyeq5-eth.o obj-$(CONFIG_PHY_GOOGLE_USB) +=3D phy-google-usb.o obj-$(CONFIG_USB_LGM_PHY) +=3D phy-lgm-usb.o obj-$(CONFIG_PHY_LPC18XX_USB_OTG) +=3D phy-lpc18xx-usb-otg.o diff --git a/drivers/phy/phy-eyeq5-eth.c b/drivers/phy/phy-eyeq5-eth.c new file mode 100644 index 000000000000..c03d77c360f7 --- /dev/null +++ b/drivers/phy/phy-eyeq5-eth.c @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EQ5_PHY_COUNT 2 + +#define EQ5_PHY0_GP 0x128 +#define EQ5_PHY1_GP 0x12c +#define EQ5_PHY0_SGMII 0x134 +#define EQ5_PHY1_SGMII 0x138 + +#define EQ5_GP_TX_SWRST_DIS BIT(0) // Tx SW reset +#define EQ5_GP_TX_M_CLKE BIT(1) // Tx M clock enable +#define EQ5_GP_SYS_SWRST_DIS BIT(2) // Sys SW reset +#define EQ5_GP_SYS_M_CLKE BIT(3) // Sys clock enable +#define EQ5_GP_SGMII_MODE BIT(4) // SGMII mode +#define EQ5_GP_RGMII_DRV GENMASK(8, 5) // RGMII drive strength + +#define EQ5_SGMII_PWR_EN BIT(0) +#define EQ5_SGMII_RST_DIS BIT(1) +#define EQ5_SGMII_PLL_EN BIT(2) +#define EQ5_SGMII_SIG_DET_SW BIT(3) +#define EQ5_SGMII_PWR_STATE BIT(4) +#define EQ5_SGMII_PLL_ACK BIT(18) +#define EQ5_SGMII_PWR_STATE_ACK GENMASK(24, 20) + +/* + * Instead of storing a phy_interface_t, we store this enum. + * + * We do not deal with RGMII timings in this generic PHY driver, + * it is all handled inside the net PHY. + */ +enum eq5_phy_submode { + EQ5_PHY_SUBMODE_SGMII, + EQ5_PHY_SUBMODE_RGMII, +}; + +struct eq5_phy_inst { + struct device *dev; + struct phy *phy; + void __iomem *gp, *sgmii; + enum eq5_phy_submode submode; + bool sgmii_support; +}; + +struct eq5_phy_private { + struct eq5_phy_inst phys[EQ5_PHY_COUNT]; +}; + +static int eq5_phy_exit(struct phy *phy) +{ + struct eq5_phy_inst *inst =3D phy_get_drvdata(phy); + + writel(0, inst->gp); + writel(0, inst->sgmii); + udelay(5); /* settling time */ + return 0; +} + +static int eq5_phy_init(struct phy *phy) +{ + struct eq5_phy_inst *inst =3D phy_get_drvdata(phy); + u32 reg; + + /* + * Hardware stops listening to our instructions once it is started. + * It must be reset to reconfigure it. + */ + eq5_phy_exit(phy); + + reg =3D EQ5_GP_TX_SWRST_DIS | EQ5_GP_TX_M_CLKE | + EQ5_GP_SYS_SWRST_DIS | EQ5_GP_SYS_M_CLKE | + FIELD_PREP(EQ5_GP_RGMII_DRV, 0x9); + writel(reg, inst->gp); + + return 0; +} + +static int eq5_phy_power_on(struct phy *phy) +{ + struct eq5_phy_inst *inst =3D phy_get_drvdata(phy); + u32 reg; + + if (inst->submode =3D=3D EQ5_PHY_SUBMODE_SGMII) { + writel(readl(inst->gp) | EQ5_GP_SGMII_MODE, inst->gp); + + reg =3D EQ5_SGMII_PWR_EN | EQ5_SGMII_RST_DIS | EQ5_SGMII_PLL_EN; + writel(reg, inst->sgmii); + + if (readl_poll_timeout(inst->sgmii, reg, + reg & EQ5_SGMII_PLL_ACK, 1, 100)) { + dev_err(inst->dev, "PLL timeout\n"); + return -ETIMEDOUT; + } + + reg =3D readl(inst->sgmii); + reg |=3D EQ5_SGMII_PWR_STATE | EQ5_SGMII_SIG_DET_SW; + writel(reg, inst->sgmii); + } else { + writel(readl(inst->gp) & ~EQ5_GP_SGMII_MODE, inst->gp); + writel(0, inst->sgmii); + } + + return 0; +} + +static int eq5_phy_power_off(struct phy *phy) +{ + struct eq5_phy_inst *inst =3D phy_get_drvdata(phy); + + writel(readl(inst->gp) & ~EQ5_GP_SGMII_MODE, inst->gp); + writel(0, inst->sgmii); + + return 0; +} + +static int eq5_phy_validate(struct phy *phy, enum phy_mode mode, int submo= de, + union phy_configure_opts *opts) +{ + struct eq5_phy_inst *inst =3D phy_get_drvdata(phy); + + if (mode !=3D PHY_MODE_ETHERNET) + return -EINVAL; + + if (phy_interface_mode_is_rgmii(submode)) + return 0; + + if (inst->sgmii_support && submode =3D=3D PHY_INTERFACE_MODE_SGMII) + return 0; + + return -EINVAL; +} + +static int eq5_phy_set_mode(struct phy *phy, enum phy_mode mode, int submo= de) +{ + struct eq5_phy_inst *inst =3D phy_get_drvdata(phy); + enum eq5_phy_submode target_submode; + int ret; + + ret =3D eq5_phy_validate(phy, mode, submode, NULL); + if (ret) + return ret; + + if (submode =3D=3D PHY_INTERFACE_MODE_SGMII) + target_submode =3D EQ5_PHY_SUBMODE_SGMII; + else + target_submode =3D EQ5_PHY_SUBMODE_RGMII; + + if (target_submode =3D=3D inst->submode) + return 0; + + inst->submode =3D target_submode; + + if (phy->power_count) { + eq5_phy_init(phy); + return eq5_phy_power_on(phy); + } + + return 0; +} + +static const struct phy_ops eq5_phy_ops =3D { + .init =3D eq5_phy_init, + .exit =3D eq5_phy_exit, + .power_on =3D eq5_phy_power_on, + .power_off =3D eq5_phy_power_off, + .set_mode =3D eq5_phy_set_mode, + .validate =3D eq5_phy_validate, +}; + +static struct phy *eq5_phy_xlate(struct device *dev, + const struct of_phandle_args *args) +{ + struct eq5_phy_private *priv =3D dev_get_drvdata(dev); + + if (args->args_count !=3D 1 || args->args[0] >=3D EQ5_PHY_COUNT) + return ERR_PTR(-EINVAL); + + return priv->phys[args->args[0]].phy; +} + +static int eq5_phy_probe_phy(struct device *dev, struct eq5_phy_private *p= riv, + unsigned int index, void __iomem *base, + unsigned int gp, unsigned int sgmii, + bool sgmii_support) +{ + struct eq5_phy_inst *inst =3D &priv->phys[index]; + struct phy *phy; + + phy =3D devm_phy_create(dev, dev->of_node, &eq5_phy_ops); + if (IS_ERR(phy)) + return dev_err_probe(dev, PTR_ERR(phy), + "failed to create PHY %u\n", index); + + inst->dev =3D dev; + inst->phy =3D phy; + inst->gp =3D base + gp; + inst->sgmii =3D base + sgmii; + inst->sgmii_support =3D sgmii_support; + phy_set_drvdata(phy, inst); + + /* + * Init inst->submode based on probe hardware state, allowing + * consumers to power us on without first setting the mode. + */ + if (sgmii_support && (readl(inst->gp) & EQ5_GP_SGMII_MODE)) + inst->submode =3D EQ5_PHY_SUBMODE_SGMII; + else + inst->submode =3D EQ5_PHY_SUBMODE_RGMII; + + return 0; +} + +static int eq5_phy_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct device *dev =3D &adev->dev; + struct phy_provider *provider; + struct eq5_phy_private *priv; + void __iomem *base; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + dev_set_drvdata(dev, priv); + + base =3D (void __iomem *)dev_get_platdata(dev); + + ret =3D eq5_phy_probe_phy(dev, priv, 0, base, EQ5_PHY0_GP, + EQ5_PHY0_SGMII, true); + if (ret) + return ret; + + ret =3D eq5_phy_probe_phy(dev, priv, 1, base, EQ5_PHY1_GP, + EQ5_PHY1_SGMII, false); + if (ret) + return ret; + + provider =3D devm_of_phy_provider_register(dev, eq5_phy_xlate); + if (IS_ERR(provider)) + return dev_err_probe(dev, PTR_ERR(provider), + "registering provider failed\n"); + + return 0; +} + +static const struct auxiliary_device_id eq5_phy_id_table[] =3D { + { .name =3D "clk_eyeq.phy" }, + {} +}; +MODULE_DEVICE_TABLE(auxiliary, eq5_phy_id_table); + +static struct auxiliary_driver eq5_phy_driver =3D { + .probe =3D eq5_phy_probe, + .id_table =3D eq5_phy_id_table, +}; +module_auxiliary_driver(eq5_phy_driver); + +MODULE_DESCRIPTION("EyeQ5 Ethernet PHY driver"); +MODULE_AUTHOR("Th=C3=A9o Lebrun "); +MODULE_LICENSE("GPL"); --=20 2.53.0