From nobody Thu Apr 9 09:51:13 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E5573E95B5; Mon, 9 Mar 2026 17:55:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773078936; cv=none; b=aeWJj7tiapGfv1MjHNtdYAYvAhtdOHS9nsaDszfR7AS9q+K4O+CIf3tqRoQmEejYlTOrcx+BzRoOYbPz+rSDJvi1tDHZvXdwx068csRMbbMW1LmYOBrTnzrOZPev2ZI4w/YDjhSXgW8R0bwv4diDgVhBCcp8hx88Csm7tmbgLNs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773078936; c=relaxed/simple; bh=Q9V6sTMaJ2pd7d5NGrdgzvEcNvyFxJE7OuvaMwzwrfQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LDjJTsSU3ExtUoDWZGFpjsJjKRW+KJzslQXABxh97mcC9JbYgKUXm5WHzi9k6EUrJ2PssOEvvdljm/vH3PcfAJFBc7uyfhRcMiAaiNN0v72JQoALfcZ/cGcIwDU1lLDgyqj97U44l/GRxok0KOcyQREODYtYQW8hxt2e4zJ7WrY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BBqzAVcc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BBqzAVcc" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1924EC4CEF7; Mon, 9 Mar 2026 17:55:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773078936; bh=Q9V6sTMaJ2pd7d5NGrdgzvEcNvyFxJE7OuvaMwzwrfQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=BBqzAVccYflp8biEyYqWk5Jgx0vSSzaJgvtYW6vpkQ/HVrPQoON9eExNw46BhzkDP 0uAw41qa+p1VlYbyvZ6KhS4OhfoAtpoWoNvrXHOg0FJaTHMZ8VMLdmDgT+sJC3qS5t BsArHu1eS0Qy3OxKiHwm5OYAbiPeU8qpMmOXBz1uepLvVEm+g+p7C3sJKWIk0CdB6c 2/HIKqG+ALSmYJwLwbJlnEiMPHiclKcQuBuHPryR6noC5NuzMfgD0ysi0bovIy7DOK KFNBfOtrYU16Z8RQsnkvB/dNxkTfSzKFSttVqMIFgHDcregeZp3NTV2tpvATQm2tzX U6H45CZhoilkw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05CD5FCA16E; Mon, 9 Mar 2026 17:55:36 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Mon, 09 Mar 2026 18:55:20 +0100 Subject: [PATCH v8 1/5] net: stmmac: Use helper macro for loop over queue-based arrays Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260309-dwmac_multi_irq-v8-1-f0cc5bc811a7@oss.nxp.com> References: <20260309-dwmac_multi_irq-v8-0-f0cc5bc811a7@oss.nxp.com> In-Reply-To: <20260309-dwmac_multi_irq-v8-0-f0cc5bc811a7@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, rmk+kernel@armlinux.org.uk, vladimir.oltean@nxp.com, boon.khai.ng@altera.com, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773078934; l=4143; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=AN9BxArjvT+LtwWtaoyDzsO4XeDTxufZg6uDwPtH3+8=; b=8zmy0Wg+/alVIyq8vDTkwX/2ouFXubxQdbigH7oUaZvyZHMnrqY+gtBnRuGivKrD6kjmNjgi/ DlXIdSvF53lAnnh49NzL1XEMBVcLhvDEuUb+EXyx0oQpvF2QXYXwMV/ X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" The stmmac driver contains similar pattern for processing queue-based arrays, ie. interrupt lines, etc. Factor out the for loop and provide a macro STMMAC_FOREACH_MTL_QUEUE(var, limit). Signed-off-by: Jan Petrous (OSS) --- drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c | 2 +- drivers/net/ethernet/stmicro/stmmac/stmmac.h | 3 +++ drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 16 ++++++++-------- 3 files changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/= net/ethernet/stmicro/stmmac/dwxgmac2_core.c index 49893b9fb88c..3890e82c69f6 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c @@ -233,7 +233,7 @@ static void dwxgmac2_prog_mtl_tx_algorithms(struct mac_= device_info *hw, writel(value, ioaddr + XGMAC_MTL_OPMODE); =20 /* Set ETS if desired */ - for (i =3D 0; i < MTL_MAX_TX_QUEUES; i++) { + STMMAC_FOREACH_MTL_QUEUE(i, MTL_MAX_TX_QUEUES) { value =3D readl(ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(i)); value &=3D ~XGMAC_TSA; if (ets) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/eth= ernet/stmicro/stmmac/stmmac.h index 51c96a738151..c972ad8e79f8 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h @@ -382,6 +382,9 @@ enum stmmac_state { =20 extern const struct dev_pm_ops stmmac_simple_pm_ops; =20 +#define STMMAC_FOREACH_MTL_QUEUE(var, limit) \ + for (var =3D 0; var < (limit); var++) + int stmmac_mdio_unregister(struct net_device *ndev); int stmmac_mdio_register(struct net_device *ndev); int stmmac_mdio_reset(struct mii_bus *mii); diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/ne= t/ethernet/stmicro/stmmac/stmmac_main.c index edf0799b7236..b920ca17b2be 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -3875,7 +3875,7 @@ static int stmmac_request_irq_multi_msi(struct net_de= vice *dev) } =20 /* Request Rx MSI irq */ - for (i =3D 0; i < priv->plat->rx_queues_to_use; i++) { + STMMAC_FOREACH_MTL_QUEUE(i, priv->plat->rx_queues_to_use) { if (i >=3D MTL_MAX_RX_QUEUES) break; if (priv->rx_irq[i] =3D=3D 0) @@ -3899,7 +3899,7 @@ static int stmmac_request_irq_multi_msi(struct net_de= vice *dev) } =20 /* Request Tx MSI irq */ - for (i =3D 0; i < priv->plat->tx_queues_to_use; i++) { + STMMAC_FOREACH_MTL_QUEUE(i, priv->plat->tx_queues_to_use) { if (i >=3D MTL_MAX_TX_QUEUES) break; if (priv->tx_irq[i] =3D=3D 0) @@ -4084,10 +4084,10 @@ static int __stmmac_open(struct net_device *dev, struct stmmac_dma_conf *dma_conf) { struct stmmac_priv *priv =3D netdev_priv(dev); + int ret, i; u32 chan; - int ret; =20 - for (int i =3D 0; i < MTL_MAX_TX_QUEUES; i++) + STMMAC_FOREACH_MTL_QUEUE(i, MTL_MAX_TX_QUEUES) if (priv->dma_conf.tx_queue[i].tbs & STMMAC_TBS_EN) dma_conf->tx_queue[i].tbs =3D priv->dma_conf.tx_queue[i].tbs; memcpy(&priv->dma_conf, dma_conf, sizeof(*dma_conf)); @@ -7734,9 +7734,9 @@ static int __stmmac_dvr_probe(struct device *device, priv->device =3D device; priv->dev =3D ndev; =20 - for (i =3D 0; i < MTL_MAX_RX_QUEUES; i++) + STMMAC_FOREACH_MTL_QUEUE(i, MTL_MAX_RX_QUEUES) u64_stats_init(&priv->xstats.rxq_stats[i].napi_syncp); - for (i =3D 0; i < MTL_MAX_TX_QUEUES; i++) { + STMMAC_FOREACH_MTL_QUEUE(i, MTL_MAX_TX_QUEUES) { u64_stats_init(&priv->xstats.txq_stats[i].q_syncp); u64_stats_init(&priv->xstats.txq_stats[i].napi_syncp); } @@ -7759,9 +7759,9 @@ static int __stmmac_dvr_probe(struct device *device, priv->sfty_irq =3D res->sfty_irq; priv->sfty_ce_irq =3D res->sfty_ce_irq; priv->sfty_ue_irq =3D res->sfty_ue_irq; - for (i =3D 0; i < MTL_MAX_RX_QUEUES; i++) + STMMAC_FOREACH_MTL_QUEUE(i, MTL_MAX_RX_QUEUES) priv->rx_irq[i] =3D res->rx_irq[i]; - for (i =3D 0; i < MTL_MAX_TX_QUEUES; i++) + STMMAC_FOREACH_MTL_QUEUE(i, MTL_MAX_TX_QUEUES) priv->tx_irq[i] =3D res->tx_irq[i]; =20 if (!is_zero_ether_addr(res->mac)) --=20 2.47.0 From nobody Thu Apr 9 09:51:13 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D9373E95A8; Mon, 9 Mar 2026 17:55:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773078936; cv=none; b=rk92sAowZNroPvOSK9ZXLicsVd1Gn/WOB+p3ChAcabITduZCKtAkaWR90j7FNS+LDcpqSZVFh4W6y0k5A8n/iybzG5iOqbwcNnXsees0QRZUfdY1VIE4dB6rkPsLkBvQdh0IdE5u2uy5ni+wUOEmY5GjzormDJCsKNnDrsPXMe8= ARC-Message-Signature: i=1; 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b=NWT2VJzjI7rUn6ThArNkkVhm+veNCDjx9zTf5LZEC5g5duRryVHwdAgB2Q8WPqKde gTVdLiMZiE3TsXYYE0VK4Rl47bFqqZLVEb6j7bIHUscX+R4q7nHWRGJ00nNbRhKcD6 0pBEcUtnA26zTtfKpfZ+jz3c3y3fYGRpq+zVSOfO7Jp0NxWc24JS0d0E1G2ovXmbi5 3PG5aoEj2ueqGOQIN1+L0gxMQtKbezmpgewieuSj3L3I7jShDayEQDarTiOaNkZyq6 dDcqHk8+z8i1hhyjUqQcrxN8OZAonZrZefQ3kJwwMkzjrT5DuQTVDyNJM79MmlDNAD G1SH6E7fKrJCw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17CC0FCA170; Mon, 9 Mar 2026 17:55:36 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Mon, 09 Mar 2026 18:55:21 +0100 Subject: [PATCH v8 2/5] net: stmmac: platform: read channels irq Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260309-dwmac_multi_irq-v8-2-f0cc5bc811a7@oss.nxp.com> References: <20260309-dwmac_multi_irq-v8-0-f0cc5bc811a7@oss.nxp.com> In-Reply-To: <20260309-dwmac_multi_irq-v8-0-f0cc5bc811a7@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, rmk+kernel@armlinux.org.uk, vladimir.oltean@nxp.com, boon.khai.ng@altera.com, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773078934; l=2726; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=/ncF81mYqriMzIkXDHCjmpdMkczIZjJbkswTEDIvT3Y=; b=EEY2RABUzz4sng03Nd2qT3obzQpPPoTeNQaOhH84h3l0S0WqTxsqd94iBOVl8n25CaMMSaPth NsBhGyKJ/HnDWx4eNPPLMDxjE64GUDdA+DS8GERCQk4pRLc+TLf0Pac X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" Read IRQ resources for all rx/tx channels, to allow Multi-IRQ mode for platform glue drivers. Reviewed-by: Matthias Brugger Signed-off-by: Jan Petrous (OSS) --- .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 57 ++++++++++++++++++= +++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/driver= s/net/ethernet/stmicro/stmmac/stmmac_platform.c index 5c9fd91a1db9..7c299e47ff14 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -697,9 +697,47 @@ struct clk *stmmac_pltfr_find_clk(struct plat_stmmacen= et_data *plat_dat, } EXPORT_SYMBOL_GPL(stmmac_pltfr_find_clk); =20 +/** + * stmmac_pltfr_get_irq_array - Read per-channel IRQs from platform device + * @pdev: platform device + * @fmt: IRQ name format string (e.g., "tx-queue-%d") + * @irqs: array to store IRQ numbers + * @num: maximum number of IRQs to read + * + * Return: 0 on success, -EPROBE_DEFER if IRQ is deferred, -EINVAL on erro= r. + * Missing IRQs are set to 0 and iteration stops at first missing IRQ. + */ +static int stmmac_pltfr_get_irq_array(struct platform_device *pdev, + const char *fmt, int *irqs, size_t num) +{ + char name[16]; + int i; + + STMMAC_FOREACH_MTL_QUEUE(i, num) { + if (snprintf(name, sizeof(name), fmt, i) >=3D sizeof(name)) + return -EINVAL; + + irqs[i] =3D platform_get_irq_byname_optional(pdev, name); + if (irqs[i] =3D=3D -EPROBE_DEFER) + return -EPROBE_DEFER; + + if (irqs[i] <=3D 0) { + dev_dbg(&pdev->dev, "IRQ %s not found\n", name); + + /* Stop on first unset irq */ + irqs[i] =3D 0; + break; + } + } + + return 0; +} + int stmmac_get_platform_resources(struct platform_device *pdev, struct stmmac_resources *stmmac_res) { + int ret; + memset(stmmac_res, 0, sizeof(*stmmac_res)); =20 /* Get IRQ information early to have an ability to ask for deferred @@ -735,7 +773,24 @@ int stmmac_get_platform_resources(struct platform_devi= ce *pdev, =20 stmmac_res->addr =3D devm_platform_ioremap_resource(pdev, 0); =20 - return PTR_ERR_OR_ZERO(stmmac_res->addr); + if (IS_ERR(stmmac_res->addr)) + return PTR_ERR(stmmac_res->addr); + + /* TX channels irq */ + ret =3D stmmac_pltfr_get_irq_array(pdev, "tx-queue-%d", + stmmac_res->tx_irq, + MTL_MAX_TX_QUEUES); + if (ret) + return ret; + + /* RX channels irq */ + ret =3D stmmac_pltfr_get_irq_array(pdev, "rx-queue-%d", + stmmac_res->rx_irq, + MTL_MAX_RX_QUEUES); + if (ret) + return ret; + + return 0; } EXPORT_SYMBOL_GPL(stmmac_get_platform_resources); =20 --=20 2.47.0 From nobody Thu Apr 9 09:51:13 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DB223E95B2; Mon, 9 Mar 2026 17:55:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773078936; cv=none; b=eZI3BHf6sBWw0r/qMAq0vj8ZWRNRm+1EDer18ZTLTu6fyyEk6Iy+UGd6yM4MDmiItsQM4IM6DdSaxK+fbRghN0pP4ld5sH9asmPyvw9jrQY56dKI09a5tfLx9HpqKMD+IDOwO6ElzvsV0KQH16MEzi25/wTmGrdkQUa7URJB8/0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Mon, 9 Mar 2026 17:55:36 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Mon, 09 Mar 2026 18:55:22 +0100 Subject: [PATCH v8 3/5] arm64: dts: s32: set Ethernet channel irqs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260309-dwmac_multi_irq-v8-3-f0cc5bc811a7@oss.nxp.com> References: <20260309-dwmac_multi_irq-v8-0-f0cc5bc811a7@oss.nxp.com> In-Reply-To: <20260309-dwmac_multi_irq-v8-0-f0cc5bc811a7@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, rmk+kernel@armlinux.org.uk, vladimir.oltean@nxp.com, boon.khai.ng@altera.com, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773078934; l=4163; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=GJtLVXXJ6B4rcW9eI+Zdnzjbg44iN/frnopr12Ti4EU=; b=dRgGMtpIhwLE31Kfv0ZvOKeCnsTl3jIHIkX0AEFXq8hvvZBREhA704LaPYuG0VXdG7PZe5o3j QLTH3l1SequA0XOclFdfI0RyKZ2WpjMSuk+Yi1rtavjwvSRMXNnpEu0 X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" The GMAC Ethernet controller found on S32G2/S32G3 and S32R45 contains up to 5 RX and 5 TX channels. It can operate in two interrupt modes: 1) Sharing IRQ mode: only MAC IRQ line is used for all channels. 2) Multiple IRQ mode: every channel uses two IRQ lines, one for RX and second for TX. Specify all IRQ twins for all channels. Reviewed-by: Matthias Brugger Signed-off-by: Jan Petrous (OSS) --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 26 +++++++++++++++++++++++--- arch/arm64/boot/dts/freescale/s32g3.dtsi | 26 +++++++++++++++++++++++--- 2 files changed, 46 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts= /freescale/s32g2.dtsi index 51d00dac12de..5a553d503137 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -3,7 +3,7 @@ * NXP S32G2 SoC family * * Copyright (c) 2021 SUSE LLC - * Copyright 2017-2021, 2024-2025 NXP + * Copyright 2017-2021, 2024-2026 NXP */ =20 #include @@ -732,8 +732,28 @@ gmac0: ethernet@4033c000 { reg =3D <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ interrupt-parent =3D <&gic>; - interrupts =3D ; - interrupt-names =3D "macirq"; + interrupts =3D , + /* CHN 0: tx, rx */ + , + , + /* CHN 1: tx, rx */ + , + , + /* CHN 2: tx, rx */ + , + , + /* CHN 3: tx, rx */ + , + , + /* CHN 4: tx, rx */ + , + ; + interrupt-names =3D "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4"; snps,mtl-rx-config =3D <&mtl_rx_setup>; snps,mtl-tx-config =3D <&mtl_tx_setup>; status =3D "disabled"; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts= /freescale/s32g3.dtsi index e314f3c7d61d..b43e6f001f4d 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright 2021-2025 NXP + * Copyright 2021-2026 NXP * * Authors: Ghennadi Procopciuc * Ciprian Costea @@ -809,8 +809,28 @@ gmac0: ethernet@4033c000 { reg =3D <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ interrupt-parent =3D <&gic>; - interrupts =3D ; - interrupt-names =3D "macirq"; + interrupts =3D , + /* CHN 0: tx, rx */ + , + , + /* CHN 1: tx, rx */ + , + , + /* CHN 2: tx, rx */ + , + , + /* CHN 3: tx, rx */ + , + , + /* CHN 4: tx, rx */ + , + ; + interrupt-names =3D "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4"; snps,mtl-rx-config =3D <&mtl_rx_setup>; snps,mtl-tx-config =3D <&mtl_tx_setup>; status =3D "disabled"; --=20 2.47.0 From nobody Thu Apr 9 09:51:13 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88DC03E95B6; Mon, 9 Mar 2026 17:55:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773078936; cv=none; b=ujJGKbvXeyQfYQDINKwu6et6p2vY6j/PvzPa3KKY85Bqd44VdxE6XAgOmIldnTs6EM9TYy3bgt8y4CllnOgsQTDcKpufzYIIekTGclMfHd3bZvJaSH0XUkG0sMluTYV6krcbf446BrLdfuvIyUIvuNCyDYNNziT36JdiCd6S4x8= ARC-Message-Signature: i=1; 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b=n0FYS2z7jiGBg4DOJZ7LSyxEMh4sKKlt7ejVuuvb8VXwm222dPC99FjS3G9aL27gU lYAJkcT2Z9RyX0YEgi70fK8SfD0uQ2ox4HHPWBswMiNlVTSfdmUsYk16EwXE4FKqlJ HZLlJaIHrtqtAojq4LBrikrkNKu/l31VnbZ23Vxs1XZqiGo+R7jFnkIP+DOwMqdC1B PSKAPCV9gMbZGyYssIAMWzER13+BdkiFuk2a5B7nv1DbdSxAIUvJWPPbK5fO44euSC /ABITc5Li0dPeBhxSo9ZzzgHvv7lRp/6i18hlD86ocU6nWkj9XCeG4HXH3fCuKhini 7D94T7HlDK5Cg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 385C2FCA173; Mon, 9 Mar 2026 17:55:36 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Mon, 09 Mar 2026 18:55:23 +0100 Subject: [PATCH v8 4/5] dt-bindings: net: nxp,s32-dwmac: Declare per-queue interrupts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260309-dwmac_multi_irq-v8-4-f0cc5bc811a7@oss.nxp.com> References: <20260309-dwmac_multi_irq-v8-0-f0cc5bc811a7@oss.nxp.com> In-Reply-To: <20260309-dwmac_multi_irq-v8-0-f0cc5bc811a7@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, rmk+kernel@armlinux.org.uk, vladimir.oltean@nxp.com, boon.khai.ng@altera.com, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773078934; l=3455; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=Ulgz8SoBFJZWXNyBqoPUpgpX/c4gObaapFU2nTXzIJo=; b=ergnlc+wxNhdFd9fZAaVc89ycrqccTBtO+1Fv3e7Lq+1bN5IceECAGwLw26cK3xmGS7ggv8sC iXraSEw3XS3CwNqXm6V86D1O/JaLuthvSIkWM66/8W6KfSBCbc17rwL X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" The DWMAC IP on NXP S32G/R SoCs has connected queue-based IRQ lines, set them to allow using Multi-IRQ mode. Reviewed-by: Matthias Brugger Reviewed-by: Rob Herring (Arm) Signed-off-by: Jan Petrous (OSS) --- .../devicetree/bindings/net/nxp,s32-dwmac.yaml | 44 ++++++++++++++++++= +--- 1 file changed, 39 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml b/Doc= umentation/devicetree/bindings/net/nxp,s32-dwmac.yaml index 1b2934f3c87c..3a0e41b63c3d 100644 --- a/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -# Copyright 2021-2024 NXP +# Copyright 2021-2026 NXP %YAML 1.2 --- $id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml# @@ -16,6 +16,8 @@ description: the SoC S32R45 has two instances. The devices can use RGMII/RMII/MII interface over Pinctrl device or the output can be routed to the embedded SerDes for SGMII connectivity. + The DWMAC instances have connected all RX/TX queues interrupts, + enabling load balancing of data traffic across all CPU cores. =20 properties: compatible: @@ -45,10 +47,22 @@ properties: FlexTimer Modules connect to GMAC_0. =20 interrupts: - maxItems: 1 + minItems: 11 + maxItems: 11 =20 interrupt-names: - const: macirq + items: + - const: macirq + - const: tx-queue-0 + - const: rx-queue-0 + - const: tx-queue-1 + - const: rx-queue-1 + - const: tx-queue-2 + - const: rx-queue-2 + - const: tx-queue-3 + - const: rx-queue-3 + - const: tx-queue-4 + - const: rx-queue-4 =20 clocks: items: @@ -88,8 +102,28 @@ examples: <0x0 0x4007c004 0x0 0x4>; /* GMAC_0_CTRL_STS */ nxp,phy-sel =3D <&gpr 0x4>; interrupt-parent =3D <&gic>; - interrupts =3D ; - interrupt-names =3D "macirq"; + interrupts =3D , + /* CHN 0: tx, rx */ + , + , + /* CHN 1: tx, rx */ + , + , + /* CHN 2: tx, rx */ + , + , + /* CHN 3: tx, rx */ + , + , + /* CHN 4: tx, rx */ + , + ; + interrupt-names =3D "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4"; snps,mtl-rx-config =3D <&mtl_rx_setup>; snps,mtl-tx-config =3D <&mtl_tx_setup>; clocks =3D <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>; --=20 2.47.0 From nobody Thu Apr 9 09:51:13 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D02B03E9F75; Mon, 9 Mar 2026 17:55:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773078936; cv=none; b=bTo3hpSGl5U+KtHqGU1w2aGbh6AIbPQiCE3kacuykYkoj0ZeSsWwxBwEZynK7/R3vvBcowYXuNs8IKVj0CVEwrMM2auZNmyoNRvd0tAjoCqfo5I15tok7xtVC00Kn5WqLxOhQo0KFi3MXbXYmgJcgY+0Thhs3hXAQ0A2H5YcfPM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773078936; c=relaxed/simple; bh=ZezFSr32pT7ms/HOoEkJXINjhxxXzSKhdAF4TkA5u20=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=L6hpNmtiPvcCrWiIbaV66DwzshhaUWB5HTvMfohNu+G1Mb6otZq5kjD0alOMu4NgzYeD1AAYKiAFyV+dKNMvll4BN7VsSk3RYJRkC25bPmTyPejpizxFS1ncERb1jEXILStUA8MO6DxsjfL2je+M33iV88fxx66CRxkoAGR39Tk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=knNm3sye; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="knNm3sye" Received: by smtp.kernel.org (Postfix) with ESMTPS id 54F56C2BCB4; Mon, 9 Mar 2026 17:55:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773078936; bh=ZezFSr32pT7ms/HOoEkJXINjhxxXzSKhdAF4TkA5u20=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=knNm3syeZRNgKge4u292si+PXIkwFTkONyzhIGpX3wxCWxjvwza25tO/CCvhpQQFr h2+k6YWpSFOI30HQUtLn9yAkeMwEDaUhNce0yDhDhAy7r0AYkbvKV+b97zKYz/28uU sh45Wa/mJNBRyxGYILlPfBAXhbjAgw79mF4h7SEeC4RuBS7XOssGP2mw8VPylPsgFe fL3H5sS0gpIGz2K8jq8bYS6p+o1PIzHHQHrQyoNCuJQp6cwBtmuNXC/ZQiX0uEc4sW 5KfdrK32nUE/k/2V0cubDAtdkboTzFtvtYLSIsm4G4O707vOuWYwdbJ5DjyoDzb7nL vEwE6/ytMftbA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49995FCA171; Mon, 9 Mar 2026 17:55:36 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Mon, 09 Mar 2026 18:55:24 +0100 Subject: [PATCH v8 5/5] stmmac: s32: enable support for Multi-IRQ mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260309-dwmac_multi_irq-v8-5-f0cc5bc811a7@oss.nxp.com> References: <20260309-dwmac_multi_irq-v8-0-f0cc5bc811a7@oss.nxp.com> In-Reply-To: <20260309-dwmac_multi_irq-v8-0-f0cc5bc811a7@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, rmk+kernel@armlinux.org.uk, vladimir.oltean@nxp.com, boon.khai.ng@altera.com, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773078934; l=4702; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=Ccg7iBM1Fl+oVJULpuGtFE+LiMWCMv+ramMC+vtotcs=; b=TauJNyXlklHqzzs9EdPPUbvJPNT0FDkCEIZoutsGNVvCyNTQZqCFb336k/psw/nmcceEGsp/G lrGYC/1aEkKDPRPiNiM9sxMwykFy79sNUGkRwlJvOyehvA13zBm73FZ X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" Based on previous changes in platform driver, the vendor glue driver can enable Multi-IRQ mode, if needed. To get enabled Multi-IRQ mode for dwmac-s32, the driver checks: 1) property of 'snps,mtl-xx-config' subnode defines 'snps,xx-queues-to-use' bigger then one, ie: ethernet@4033c000 { compatible =3D "nxp,s32g2-dwmac"; ... snps,mtl-rx-config =3D <&mtl_rx_setup>; ... mtl_rx_setup: rx-queues-config { snps,rx-queues-to-use =3D <2>; }; 2) queue based IRQs are set, ie: ethernet@4033c000 { compatible =3D "nxp,s32g2-dwmac"; ... interrupts =3D , /* CHN 0: tx, rx */ , , /* CHN 1: tx, rx */ , ; interrupt-names =3D "macirq", "tx-queue-0", "rx-queue-0", "tx-queue-1", "rx-queue-1"; If those prerequisites are met, the driver switches to Multi-IRQ mode, using per-queue IRQs for rx/tx data pathr: [ 1.387045] s32-dwmac 4033c000.ethernet: Multi-IRQ mode (per queue IRQs)= selected Now the driver owns all queues IRQs: root@s32g399aevb3:~# grep eth /proc/interrupts 29: 0 0 0 0 0 0 0 0 GICv3 89 Level eth0:mac 30: 0 0 0 0 0 0 0 0 GICv3 91 Level eth0:rx-0 31: 0 0 0 0 0 0 0 0 GICv3 93 Level eth0:rx-1 32: 0 0 0 0 0 0 0 0 GICv3 95 Level eth0:rx-2 33: 0 0 0 0 0 0 0 0 GICv3 97 Level eth0:rx-3 34: 0 0 0 0 0 0 0 0 GICv3 99 Level eth0:rx-4 35: 0 0 0 0 0 0 0 0 GICv3 90 Level eth0:tx-0 36: 0 0 0 0 0 0 0 0 GICv3 92 Level eth0:tx-1 37: 0 0 0 0 0 0 0 0 GICv3 94 Level eth0:tx-2 38: 0 0 0 0 0 0 0 0 GICv3 96 Level eth0:tx-3 39: 0 0 0 0 0 0 0 0 GICv3 98 Level eth0:tx-4 Otherwise, if one of the prerequisite don't met, the driver continue with MAC IRQ mode: [ 1.387045] s32-dwmac 4033c000.ethernet: MAC IRQ mode selected And only MAC IRQ will be attached: root@s32g399aevb3:~# grep eth /proc/interrupts 29: 0 0 0 0 0 0 0 0 GICv3 89 Level eth0:mac What represents the original MAC IRQ mode and is fully backward compatible. Reviewed-by: Matthias Brugger Signed-off-by: Jan Petrous (OSS) --- drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c | 36 +++++++++++++++++++++= +++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/= ethernet/stmicro/stmmac/dwmac-s32.c index af594a096676..d4e0c9f44fb3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c @@ -2,7 +2,7 @@ /* * NXP S32G/R GMAC glue layer * - * Copyright 2019-2024 NXP + * Copyright 2019-2026 NXP * */ =20 @@ -110,6 +110,37 @@ static void s32_gmac_exit(struct device *dev, void *pr= iv) clk_disable_unprepare(gmac->rx_clk); } =20 +static void s32_gmac_setup_multi_irq(struct device *dev, + struct plat_stmmacenet_data *plat, + struct stmmac_resources *res) +{ + int i; + + /* RX IRQs */ + STMMAC_FOREACH_MTL_QUEUE(i, plat->rx_queues_to_use) { + if (res->rx_irq[i] <=3D 0) { + dev_dbg(dev, "Missing RX queue %d interrupt\n", i); + goto mac_irq_mode; + } + } + + /* TX IRQs */ + STMMAC_FOREACH_MTL_QUEUE(i, plat->tx_queues_to_use) { + if (res->tx_irq[i] <=3D 0) { + dev_dbg(dev, "Missing TX queue %d interrupt\n", i); + goto mac_irq_mode; + } + } + + plat->flags |=3D STMMAC_FLAG_MULTI_MSI_EN; + dev_info(dev, "Multi-IRQ mode (per queue IRQs) selected\n"); + return; + +mac_irq_mode: + plat->flags &=3D ~STMMAC_FLAG_MULTI_MSI_EN; + dev_info(dev, "MAC IRQ mode selected\n"); +} + static int s32_dwmac_probe(struct platform_device *pdev) { struct plat_stmmacenet_data *plat; @@ -165,6 +196,9 @@ static int s32_dwmac_probe(struct platform_device *pdev) plat->core_type =3D DWMAC_CORE_GMAC4; plat->pmt =3D 1; plat->flags |=3D STMMAC_FLAG_SPH_DISABLE; + + s32_gmac_setup_multi_irq(dev, plat, &res); + plat->rx_fifo_size =3D 20480; plat->tx_fifo_size =3D 20480; =20 --=20 2.47.0