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This encompasses 5 SS USB QMP PHYs (3 combo and 2 uni) and 6 M31 eUSB2 PHYs. All controllers are SNPS DWC3 based, so describe them as flattened DWC3 QCOM nodes. Signed-off-by: Wesley Cheng Co-developed-by: Abel Vesa Reviewed-by: Konrad Dybcio Tested-by: Pankaj Patil Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/glymur.dtsi | 691 +++++++++++++++++++++++++++++++= +++- 1 file changed, 686 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index e269cec7942c..2aa9af8c96ce 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -750,11 +750,11 @@ gcc: clock-controller@100000 { <0>, /* UFS PHY RX Symbol 0 */ <0>, /* UFS PHY RX Symbol 1 */ <0>, /* UFS PHY TX Symbol 0 */ - <0>, /* USB3 PHY 0 */ - <0>, /* USB3 PHY 1 */ - <0>, /* USB3 PHY 2 */ - <0>, /* USB3 UNI PHY pipe 0 */ - <0>, /* USB3 UNI PHY pipe 1 */ + <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_mp_qmpphy0 QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_mp_qmpphy1 QMP_USB43DP_USB3_PIPE_CLK>, <0>, /* USB4 PHY 0 pcie pipe */ <0>, /* USB4 PHY 0 Max pipe */ <0>, /* USB4 PHY 1 pcie pipe */ @@ -2264,6 +2264,254 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, }; }; =20 + usb_hs_phy: phy@fa0000 { + compatible =3D "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + reg =3D <0x0 0x00fa0000 0x0 0x154>; + #phy-cells =3D <0>; + + clocks =3D <&tcsr TCSR_USB2_1_CLKREF_EN>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; + + status =3D "disabled"; + }; + + usb_mp_hsphy0: phy@fa1000 { + compatible =3D "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg =3D <0x0 0x00fa1000 0x0 0x29c>; + #phy-cells =3D <0>; + + clocks =3D <&tcsr TCSR_USB2_1_CLKREF_EN>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; + + status =3D "disabled"; + }; + + usb_mp_hsphy1: phy@fa2000 { + compatible =3D "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg =3D <0x0 0x00fa2000 0x0 0x29c>; + #phy-cells =3D <0>; + + clocks =3D <&tcsr TCSR_USB2_2_CLKREF_EN>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; + + status =3D "disabled"; + }; + + usb_mp_qmpphy0: phy@fa3000 { + compatible =3D "qcom,glymur-qmp-usb3-uni-phy"; + reg =3D <0x0 0x00fa3000 0x0 0x2000>; + + clocks =3D <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&tcsr TCSR_USB3_0_CLKREF_EN>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; + clock-names =3D "aux", + "clkref", + "ref", + "com_aux", + "pipe"; + + power-domains =3D <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; + + resets =3D <&gcc GCC_USB3_MP_SS0_PHY_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; + reset-names =3D "phy", + "phy_phy"; + + clock-output-names =3D "usb3_uni_phy_0_pipe_clk_src"; + #clock-cells =3D <0>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_mp_qmpphy1: phy@fa5000 { + compatible =3D "qcom,glymur-qmp-usb3-uni-phy"; + reg =3D <0x0 0x00fa5000 0x0 0x2000>; + + clocks =3D <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&tcsr TCSR_USB3_1_CLKREF_EN>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; + clock-names =3D "aux", + "clkref", + "ref", + "com_aux", + "pipe"; + + power-domains =3D <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; + + resets =3D <&gcc GCC_USB3_MP_SS1_PHY_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; + reset-names =3D "phy", + "phy_phy"; + + clock-output-names =3D "usb3_uni_phy_1_pipe_clk_src"; + + #clock-cells =3D <0>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_0_hsphy: phy@fd3000 { + compatible =3D "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg =3D <0x0 0x00fd3000 0x0 0x29c>; + #phy-cells =3D <0>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + status =3D "disabled"; + }; + + usb_0_qmpphy: phy@fd5000 { + compatible =3D "qcom,glymur-qmp-usb3-dp-phy"; + reg =3D <0x0 0x00fd5000 0x0 0x8000>; + + clocks =3D <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names =3D "aux", + "ref", + "com_aux", + "usb3_pipe"; + + resets =3D <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; + + reset-names =3D "phy", + "common"; + + power-domains =3D <&gcc GCC_USB_0_PHY_GDSC>; + + #clock-cells =3D <1>; + #phy-cells =3D <1>; + + mode-switch; + orientation-switch; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_0_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb_0_qmpphy_usb_ss_in: endpoint { + remote-endpoint =3D <&usb_0_dwc3_ss>; + }; + }; + + port@2 { + reg =3D <2>; + + usb_dp_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + + usb_1_hsphy: phy@fdd000 { + compatible =3D "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg =3D <0x0 0x00fdd000 0x0 0x29c>; + #phy-cells =3D <0>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_SEC_BCR>; + + status =3D "disabled"; + }; + + usb_1_qmpphy: phy@fde000 { + compatible =3D "qcom,glymur-qmp-usb3-dp-phy"; + reg =3D <0x0 0x00fde000 0x0 0x8000>; + + clocks =3D <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>, + <&tcsr TCSR_USB4_1_CLKREF_EN>; + clock-names =3D "aux", + "ref", + "com_aux", + "usb3_pipe", + "clkref"; + + power-domains =3D <&gcc GCC_USB_1_PHY_GDSC>; + + resets =3D <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB3PHY_PHY_SEC_BCR>; + reset-names =3D "phy", + "common"; + + #clock-cells =3D <1>; + #phy-cells =3D <1>; + + mode-switch; + orientation-switch; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_1_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint =3D <&usb_1_dwc3_ss>; + }; + }; + + port@2 { + reg =3D <2>; + + usb_1_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + cnoc_main: interconnect@1500000 { compatible =3D "qcom,glymur-cnoc-main"; reg =3D <0x0 0x01500000 0x0 0x17080>; @@ -3367,6 +3615,439 @@ lpass_ag_noc: interconnect@7e40000 { #interconnect-cells =3D <2>; }; =20 + usb_2_hsphy: phy@88e0000 { + compatible =3D "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg =3D <0x0 0x088e0000 0x0 0x29c>; + #phy-cells =3D <0>; + + clocks =3D <&tcsr TCSR_USB2_4_CLKREF_EN>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_TERT_BCR>; + + status =3D "disabled"; + }; + + usb_2_qmpphy: phy@88e1000 { + compatible =3D "qcom,glymur-qmp-usb3-dp-phy"; + reg =3D <0x0 0x088e1000 0x0 0x8000>; + + clocks =3D <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>, + <&tcsr TCSR_USB4_2_CLKREF_EN>; + clock-names =3D "aux", + "ref", + "com_aux", + "usb3_pipe", + "clkref"; + + power-domains =3D <&gcc GCC_USB_2_PHY_GDSC>; + + resets =3D <&gcc GCC_USB3_PHY_TERT_BCR>, + <&gcc GCC_USB3PHY_PHY_TERT_BCR>; + reset-names =3D "phy", + "common"; + + #clock-cells =3D <1>; + #phy-cells =3D <1>; + + mode-switch; + orientation-switch; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_2_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb_2_qmpphy_usb_ss_in: endpoint { + remote-endpoint =3D <&usb_2_dwc3_ss>; + }; + }; + + port@2 { + reg =3D <2>; + + usb_2_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + + usb_0: usb@a600000 { + compatible =3D "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg =3D <0x0 0x0a600000 0x0 0xfc100>; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended =3D <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 90 IRQ_TYPE_EDGE_BOTH>, + <&pdc 60 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_EDGE_BOTH>; + interrupt-names =3D "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains =3D <&gcc GCC_USB30_PRIM_GDSC>; + resets =3D <&gcc GCC_USB30_PRIM_BCR>; + + iommus =3D <&apps_smmu 0x1420 0x0>; + phys =3D <&usb_0_hsphy>, + <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names =3D "usb2-phy", + "usb3-phy"; + + snps,hird-threshold =3D /bits/ 8 <0x0>; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + usb-role-switch; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_0_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb_0_dwc3_ss: endpoint { + remote-endpoint =3D <&usb_0_qmpphy_usb_ss_in>; + }; + }; + }; + }; + + usb_1: usb@a800000 { + compatible =3D "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg =3D <0x0 0x0a800000 0x0 0xfc100>; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended =3D <&intc GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 88 IRQ_TYPE_EDGE_BOTH>, + <&pdc 87 IRQ_TYPE_EDGE_BOTH>, + <&pdc 76 IRQ_TYPE_EDGE_BOTH>; + interrupt-names =3D "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + resets =3D <&gcc GCC_USB30_SEC_BCR>; + power-domains =3D <&gcc GCC_USB30_SEC_GDSC>; + + iommus =3D <&apps_smmu 0x1460 0x0>; + + phys =3D <&usb_1_hsphy>, + <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names =3D "usb2-phy", + "usb3-phy"; + + snps,hird-threshold =3D /bits/ 8 <0x0>; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb_1_dwc3_ss: endpoint { + remote-endpoint =3D <&usb_1_qmpphy_usb_ss_in>; + }; + }; + }; + }; + + usb_2: usb@a000000 { + compatible =3D "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg =3D <0x0 0x0a000000 0x0 0xfc100>; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, + <&gcc GCC_USB30_TERT_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, + <&gcc GCC_USB30_TERT_SLEEP_CLK>, + <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended =3D <&intc GIC_SPI 871 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 89 IRQ_TYPE_EDGE_BOTH>, + <&pdc 81 IRQ_TYPE_EDGE_BOTH>, + <&pdc 75 IRQ_TYPE_EDGE_BOTH>; + interrupt-names =3D "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + resets =3D <&gcc GCC_USB30_TERT_BCR>; + power-domains =3D <&gcc GCC_USB30_TERT_GDSC>; + + iommus =3D <&apps_smmu 0x420 0x0>; + + phys =3D <&usb_2_hsphy>, + <&usb_2_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names =3D "usb2-phy", + "usb3-phy"; + + snps,hird-threshold =3D /bits/ 8 <0x0>; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_2_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb_2_dwc3_ss: endpoint { + remote-endpoint =3D <&usb_2_qmpphy_usb_ss_in>; + }; + }; + }; + }; + + usb_hs: usb@a2f8800 { + compatible =3D "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg =3D <0x0 0x0a200000 0x0 0xfc100>; + + clocks =3D <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + assigned-clocks =3D <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <200000000>; + + interrupts-extended =3D <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 92 IRQ_TYPE_EDGE_BOTH>, + <&pdc 57 IRQ_TYPE_EDGE_BOTH>, + <&intc GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "hs_phy_irq"; + + resets =3D <&gcc GCC_USB20_PRIM_BCR>; + + power-domains =3D <&gcc GCC_USB20_PRIM_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + iommus =3D <&apps_smmu 0x0ce0 0x0>; + + interconnects =3D <&aggre3_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "usb-ddr", + "apps-usb"; + + phys =3D <&usb_hs_phy>; + phy-names =3D "usb2-phy"; + + snps,hird-threshold =3D /bits/ 8 <0x0>; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + dr_mode =3D "host"; + + maximum-speed =3D "high-speed"; + + status =3D "disabled"; + }; + + usb_mp: usb@a400000 { + compatible =3D "qcom,glymur-dwc3-mp", "qcom,snps-dwc3"; + reg =3D <0x0 0x0a400000 0x0 0xfc100>; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_SLEEP_CLK>, + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended =3D <&intc GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 12 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 11 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 13 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 78 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 77 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "dwc_usb3", + "pwr_event_1", + "pwr_event_2", + "hs_phy_1", + "hs_phy_2", + "dp_hs_phy_1", + "dm_hs_phy_1", + "dp_hs_phy_2", + "dm_hs_phy_2", + "ss_phy_1", + "ss_phy_2"; + + resets =3D <&gcc GCC_USB30_MP_BCR>; + power-domains =3D <&gcc GCC_USB30_MP_GDSC>; + + iommus =3D <&apps_smmu 0xda0 0x0>; + + phys =3D <&usb_mp_hsphy0>, + <&usb_mp_qmpphy0>, + <&usb_mp_hsphy1>, + <&usb_mp_qmpphy1>; + phy-names =3D "usb2-0", + "usb3-0", + "usb2-1", + "usb3-1"; + + snps,hird-threshold =3D /bits/ 8 <0x0>; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,has-lpm-erratum; + tx-fifo-resize; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + dr_mode =3D "host"; + + status =3D "disabled"; + }; + + dispcc: clock-controller@af00000 { compatible =3D "qcom,glymur-dispcc"; reg =3D <0x0 0x0af00000 0x0 0x20000>; --=20 2.48.1