From nobody Thu Apr 9 14:59:32 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8405A175A63; Mon, 9 Mar 2026 06:33:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773038036; cv=none; b=H3jky3EGk3HLQRRs/0gif6JaTFGFzTzBrL5rih/rVzw4CcZGymea6TP1HoVwMm2s9MJQmruMtabmQ3MOh108xwh+cPmgxC1k1OIlWopoVP6Xe2QB6ilFm4Y+iEzRmuQBUC0Dw3h9z3Ch+lUvges3yqJumruSuttmFvMQsTDepUQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773038036; c=relaxed/simple; bh=QwPr0xj/TxSpnfwsXKR/KjZxXEMMUpqZ0qsadjMWYv4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Vg6Ln3S7LYW4dw/uZpWsTp6KUCDQAn09HGIprKzJ3ZTSqV6pGckw+kV8ly02gfVWWZw/unDmhZ9e85b1r3WUR7Ki4Bppm5u8AerA7Vd/TWrRvuOHAD8otrgk6+KThBh9KANPOgxokzc7dXOPJTBWiFAMQIIRjhcSWTiZTjCo9XQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=U6SoBA5W; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="U6SoBA5W" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4E7D2C19423; Mon, 9 Mar 2026 06:33:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773038036; bh=QwPr0xj/TxSpnfwsXKR/KjZxXEMMUpqZ0qsadjMWYv4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=U6SoBA5WvgR2JZFh+f5HLW9C6NUI5hr+VYxkyDTSpf//d9xs5Gh9v/GEuoG6sD6g4 n2pBnxBX1Edy66H0TsOeGuofh5RJ3l/vD+d3ktKsiwhIZi4RYUvJ5/2hG6lBk94+4/ Ll8tcXbh8Frp1KR7/phJZNiDj2cxU/Mg+mIBBsAQe2Tp9gsjLlaCnJb7xwUKSeEBMq Sc5SAVsN44w5q+nAAJLGzBOp0TmqV/dxxksaBARxYdlvapIw34Ps3SblsDCj1Upkl1 a+7w3hmVsZRVXIrtA7lzWy4YGz9wcKZd5FAt57QMZLrfvmEivfVLcr3/ZZQLNNhzeT PjCzTklOJnsgA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3ABF8EF36E7; Mon, 9 Mar 2026 06:33:56 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Mon, 09 Mar 2026 06:33:53 +0000 Subject: [PATCH v6 2/3] dmaengine: amlogic: Add general DMA driver for A9 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260309-amlogic-dma-v6-2-63349d23bd4b@amlogic.com> References: <20260309-amlogic-dma-v6-0-63349d23bd4b@amlogic.com> In-Reply-To: <20260309-amlogic-dma-v6-0-63349d23bd4b@amlogic.com> To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kees Cook , "Gustavo A. R. Silva" , Frank Li Cc: linux-amlogic@lists.infradead.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773038034; l=19830; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=fg+iSUyAhauPn+s3neDx9F3/qejdQdyggzajzfDsxWY=; b=r1hZWMyAO2llm5OSnjoUZeVO81Ns7QmWzDCnDy1yGGxNE0ZsElArsxBv+h23obVFyqa2Gl2Ry BvXcbfQaW3+ArhUh1cvZ2VLLGu1K8AyIG1svbIi/8B/+b4nWF8d4Kya X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Amlogic A9 SoCs include a general-purpose DMA controller that can be used by multiple peripherals, such as I2C PIO and I3C. Each peripheral group is associated with a dedicated DMA channel in hardware. Signed-off-by: Xianwei Zhao Reviewed-by: Frank Li --- drivers/dma/Kconfig | 9 + drivers/dma/Makefile | 1 + drivers/dma/amlogic-dma.c | 585 ++++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 595 insertions(+) diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 66cda7cc9f7a..8d4578513acf 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -85,6 +85,15 @@ config AMCC_PPC440SPE_ADMA help Enable support for the AMCC PPC440SPe RAID engines. =20 +config AMLOGIC_DMA + tristate "Amlogic general DMA support" + depends on ARCH_MESON || COMPILE_TEST + select DMA_ENGINE + select REGMAP_MMIO + help + Enable support for the Amlogic general DMA engines. THis DMA + controller is used some Amlogic SoCs, such as A9. + config APPLE_ADMAC tristate "Apple ADMAC support" depends on ARCH_APPLE || COMPILE_TEST diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index a54d7688392b..fc28dade5b69 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_DMATEST) +=3D dmatest.o obj-$(CONFIG_ALTERA_MSGDMA) +=3D altera-msgdma.o obj-$(CONFIG_AMBA_PL08X) +=3D amba-pl08x.o obj-$(CONFIG_AMCC_PPC440SPE_ADMA) +=3D ppc4xx/ +obj-$(CONFIG_AMLOGIC_DMA) +=3D amlogic-dma.o obj-$(CONFIG_APPLE_ADMAC) +=3D apple-admac.o obj-$(CONFIG_ARM_DMA350) +=3D arm-dma350.o obj-$(CONFIG_AT_HDMAC) +=3D at_hdmac.o diff --git a/drivers/dma/amlogic-dma.c b/drivers/dma/amlogic-dma.c new file mode 100644 index 000000000000..120cd9dd3ca3 --- /dev/null +++ b/drivers/dma/amlogic-dma.c @@ -0,0 +1,585 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright (C) 2025 Amlogic, Inc. All rights reserved + * Author: Xianwei Zhao + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dmaengine.h" + +#define RCH_REG_BASE 0x0 +#define WCH_REG_BASE 0x2000 +/* + * Each rch (read from memory) REG offset Rch_offset 0x0 each channel tot= al 0x40 + * rch addr =3D DMA_base + Rch_offset+ chan_id * 0x40 + reg_offset + */ +#define RCH_READY 0x0 +#define RCH_STATUS 0x4 +#define RCH_CFG 0x8 +#define CFG_CLEAR BIT(25) +#define CFG_PAUSE BIT(26) +#define CFG_ENABLE BIT(27) +#define CFG_DONE BIT(28) +#define RCH_ADDR 0xc +#define RCH_LEN 0x10 +#define RCH_RD_LEN 0x14 +#define RCH_PRT 0x18 +#define RCH_SYCN_STAT 0x1c +#define RCH_ADDR_LOW 0x20 +#define RCH_ADDR_HIGH 0x24 +/* if work on 64, it work with RCH_PRT */ +#define RCH_PTR_HIGH 0x28 + +/* + * Each wch (write to memory) REG offset Wch_offset 0x2000 each channel t= otal 0x40 + * wch addr =3D DMA_base + Wch_offset+ chan_id * 0x40 + reg_offset + */ +#define WCH_READY 0x0 +#define WCH_TOTAL_LEN 0x4 +#define WCH_CFG 0x8 +#define WCH_ADDR 0xc +#define WCH_LEN 0x10 +#define WCH_RD_LEN 0x14 +#define WCH_PRT 0x18 +#define WCH_CMD_CNT 0x1c +#define WCH_ADDR_LOW 0x20 +#define WCH_ADDR_HIGH 0x24 +/* if work on 64, it work with RCH_PRT */ +#define WCH_PTR_HIGH 0x28 + +/* DMA controller reg */ +#define RCH_INT_MASK 0x1000 +#define WCH_INT_MASK 0x1004 +#define CLEAR_W_BATCH 0x1014 +#define CLEAR_RCH 0x1024 +#define CLEAR_WCH 0x1028 +#define RCH_ACTIVE 0x1038 +#define WCH_ACTIVE 0x103c +#define RCH_DONE 0x104c +#define WCH_DONE 0x1050 +#define RCH_ERR 0x1060 +#define RCH_LEN_ERR 0x1064 +#define WCH_ERR 0x1068 +#define DMA_BATCH_END 0x1078 +#define WCH_EOC_DONE 0x1088 +#define WDMA_RESP_ERR 0x1098 +#define UPT_PKT_SYNC 0x10a8 +#define RCHN_CFG 0x10ac +#define WCHN_CFG 0x10b0 +#define MEM_PD_CFG 0x10b4 +#define MEM_BUS_CFG 0x10b8 +#define DMA_GMV_CFG 0x10bc +#define DMA_GMR_CFG 0x10c0 + +#define DMA_MAX_LINK 8 +#define MAX_CHAN_ID 32 +#define SG_MAX_LEN GENMASK(26, 0) + +struct aml_dma_sg_link { +#define LINK_LEN GENMASK(26, 0) +#define LINK_IRQ BIT(27) +#define LINK_EOC BIT(28) +#define LINK_LOOP BIT(29) +#define LINK_ERR BIT(30) +#define LINK_OWNER BIT(31) + u32 ctl; + u64 address; + u32 revered; +} __packed; + +struct aml_dma_chan { + struct dma_chan chan; + struct dma_async_tx_descriptor desc; + struct aml_dma_dev *aml_dma; + struct aml_dma_sg_link *sg_link; + dma_addr_t sg_link_phys; + int sg_link_cnt; + int data_len; + enum dma_status pre_status; + enum dma_status status; + enum dma_transfer_direction direction; + int chan_id; + /* reg_base (direction + chan_id) */ + int reg_offs; +}; + +struct aml_dma_dev { + struct dma_device dma_device; + void __iomem *base; + struct regmap *regmap; + struct clk *clk; + int irq; + struct platform_device *pdev; + struct aml_dma_chan *aml_rch[MAX_CHAN_ID]; + struct aml_dma_chan *aml_wch[MAX_CHAN_ID]; + unsigned int chan_nr; + unsigned int chan_used; + struct aml_dma_chan aml_chans[]__counted_by(chan_nr); +}; + +static struct aml_dma_chan *to_aml_dma_chan(struct dma_chan *chan) +{ + return container_of(chan, struct aml_dma_chan, chan); +} + +static dma_cookie_t aml_dma_tx_submit(struct dma_async_tx_descriptor *tx) +{ + return dma_cookie_assign(tx); +} + +static int aml_dma_alloc_chan_resources(struct dma_chan *chan) +{ + struct aml_dma_chan *aml_chan =3D to_aml_dma_chan(chan); + struct aml_dma_dev *aml_dma =3D aml_chan->aml_dma; + size_t size =3D size_mul(sizeof(struct aml_dma_sg_link), DMA_MAX_LINK); + + aml_chan->sg_link =3D dma_alloc_coherent(aml_dma->dma_device.dev, size, + &aml_chan->sg_link_phys, GFP_KERNEL); + if (!aml_chan->sg_link) + return -ENOMEM; + + /* offset is the same RCH_CFG and WCH_CFG */ + regmap_set_bits(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, CFG_CLEAR); + aml_chan->status =3D DMA_COMPLETE; + dma_async_tx_descriptor_init(&aml_chan->desc, chan); + aml_chan->desc.tx_submit =3D aml_dma_tx_submit; + regmap_clear_bits(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, CFG_CLEA= R); + + return 0; +} + +static void aml_dma_free_chan_resources(struct dma_chan *chan) +{ + struct aml_dma_chan *aml_chan =3D to_aml_dma_chan(chan); + struct aml_dma_dev *aml_dma =3D aml_chan->aml_dma; + + aml_chan->status =3D DMA_COMPLETE; + dma_free_coherent(aml_dma->dma_device.dev, + sizeof(struct aml_dma_sg_link) * DMA_MAX_LINK, + aml_chan->sg_link, aml_chan->sg_link_phys); +} + +/* DMA transfer state update how many data reside it */ +static enum dma_status aml_dma_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct aml_dma_chan *aml_chan =3D to_aml_dma_chan(chan); + struct aml_dma_dev *aml_dma =3D aml_chan->aml_dma; + u32 residue, done; + + regmap_read(aml_dma->regmap, aml_chan->reg_offs + RCH_RD_LEN, &done); + residue =3D aml_chan->data_len - done; + dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, + residue); + + return aml_chan->status; +} + +static struct dma_async_tx_descriptor *aml_dma_prep_slave_sg + (struct dma_chan *chan, struct scatterlist *sgl, + unsigned int sg_len, enum dma_transfer_direction direction, + unsigned long flags, void *context) +{ + struct aml_dma_chan *aml_chan =3D to_aml_dma_chan(chan); + struct aml_dma_dev *aml_dma =3D aml_chan->aml_dma; + struct aml_dma_sg_link *sg_link; + struct scatterlist *sg; + int idx =3D 0; + u64 paddr; + u32 reg, link_count, avail, chan_id; + u32 i; + + if (aml_chan->direction !=3D direction) { + dev_err(aml_dma->dma_device.dev, "direction not support\n"); + return NULL; + } + + switch (aml_chan->status) { + case DMA_IN_PROGRESS: + dev_err(aml_dma->dma_device.dev, "not support multi tx_desciptor\n"); + return NULL; + + case DMA_COMPLETE: + aml_chan->data_len =3D 0; + chan_id =3D aml_chan->chan_id; + reg =3D (direction =3D=3D DMA_DEV_TO_MEM) ? WCH_INT_MASK : RCH_INT_MASK; + regmap_set_bits(aml_dma->regmap, reg, BIT(chan_id)); + + break; + default: + dev_err(aml_dma->dma_device.dev, "status error\n"); + return NULL; + } + + link_count =3D sg_nents_for_dma(sgl, sg_len, SG_MAX_LEN); + + if (link_count > DMA_MAX_LINK) { + dev_err(aml_dma->dma_device.dev, + "maximum number of sg exceeded: %d > %d\n", + sg_len, DMA_MAX_LINK); + aml_chan->status =3D DMA_ERROR; + return NULL; + } + + aml_chan->status =3D DMA_IN_PROGRESS; + + for_each_sg(sgl, sg, sg_len, i) { + avail =3D sg_dma_len(sg); + paddr =3D sg->dma_address; + while (avail > SG_MAX_LEN) { + sg_link =3D &aml_chan->sg_link[idx++]; + /* set dma address and len to sglink*/ + sg_link->address =3D paddr; + sg_link->ctl =3D FIELD_PREP(LINK_LEN, SG_MAX_LEN); + paddr =3D paddr + SG_MAX_LEN; + avail =3D avail - SG_MAX_LEN; + } + sg_link =3D &aml_chan->sg_link[idx++]; + /* set dma address and len to sglink*/ + sg_link->address =3D paddr; + sg_link->ctl =3D FIELD_PREP(LINK_LEN, avail); + + aml_chan->data_len +=3D sg_dma_len(sg); + } + aml_chan->sg_link_cnt =3D idx; + + return &aml_chan->desc; +} + +static int aml_dma_chan_pause(struct dma_chan *chan) +{ + struct aml_dma_chan *aml_chan =3D to_aml_dma_chan(chan); + struct aml_dma_dev *aml_dma =3D aml_chan->aml_dma; + + regmap_set_bits(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, CFG_PAUSE); + aml_chan->pre_status =3D aml_chan->status; + aml_chan->status =3D DMA_PAUSED; + + return 0; +} + +static int aml_dma_chan_resume(struct dma_chan *chan) +{ + struct aml_dma_chan *aml_chan =3D to_aml_dma_chan(chan); + struct aml_dma_dev *aml_dma =3D aml_chan->aml_dma; + + regmap_clear_bits(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, CFG_PAUS= E); + aml_chan->status =3D aml_chan->pre_status; + + return 0; +} + +static int aml_dma_terminate_all(struct dma_chan *chan) +{ + struct aml_dma_chan *aml_chan =3D to_aml_dma_chan(chan); + struct aml_dma_dev *aml_dma =3D aml_chan->aml_dma; + int chan_id =3D aml_chan->chan_id; + + aml_dma_chan_pause(chan); + regmap_set_bits(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, CFG_CLEAR); + + if (aml_chan->direction =3D=3D DMA_MEM_TO_DEV) + regmap_set_bits(aml_dma->regmap, RCH_INT_MASK, BIT(chan_id)); + else if (aml_chan->direction =3D=3D DMA_DEV_TO_MEM) + regmap_set_bits(aml_dma->regmap, WCH_INT_MASK, BIT(chan_id)); + + aml_chan->status =3D DMA_COMPLETE; + + return 0; +} + +static void aml_dma_issue_pending(struct dma_chan *chan) +{ + struct aml_dma_chan *aml_chan =3D to_aml_dma_chan(chan); + struct aml_dma_dev *aml_dma =3D aml_chan->aml_dma; + struct aml_dma_sg_link *sg_link; + int chan_id =3D aml_chan->chan_id; + int idx =3D aml_chan->sg_link_cnt - 1; + + /* the last sg set eoc flag */ + sg_link =3D &aml_chan->sg_link[idx]; + sg_link->ctl |=3D LINK_EOC; + if (aml_chan->direction =3D=3D DMA_MEM_TO_DEV) { + regmap_write(aml_dma->regmap, aml_chan->reg_offs + RCH_ADDR, + aml_chan->sg_link_phys); + regmap_write(aml_dma->regmap, aml_chan->reg_offs + RCH_LEN, aml_chan->da= ta_len); + regmap_clear_bits(aml_dma->regmap, RCH_INT_MASK, BIT(chan_id)); + /* for rch (tx) need set cfg 0 to trigger start */ + regmap_write(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, 0); + } else if (aml_chan->direction =3D=3D DMA_DEV_TO_MEM) { + regmap_write(aml_dma->regmap, aml_chan->reg_offs + WCH_ADDR, + aml_chan->sg_link_phys); + regmap_write(aml_dma->regmap, aml_chan->reg_offs + WCH_LEN, aml_chan->da= ta_len); + regmap_clear_bits(aml_dma->regmap, WCH_INT_MASK, BIT(chan_id)); + } +} + +static irqreturn_t aml_dma_interrupt_handler(int irq, void *dev_id) +{ + struct aml_dma_dev *aml_dma =3D dev_id; + struct aml_dma_chan *aml_chan; + u32 done, eoc_done, err, err_l, end; + int i =3D 0; + + /* deal with rch normal complete and error */ + regmap_read(aml_dma->regmap, RCH_DONE, &done); + regmap_read(aml_dma->regmap, RCH_ERR, &err); + regmap_read(aml_dma->regmap, RCH_LEN_ERR, &err_l); + err =3D err | err_l; + + done =3D done | err; + + while (done) { + i =3D ffs(done) - 1; + aml_chan =3D aml_dma->aml_rch[i]; + regmap_write(aml_dma->regmap, CLEAR_RCH, BIT(aml_chan->chan_id)); + if (!aml_chan) { + dev_err(aml_dma->dma_device.dev, "idx %d rch not initialized\n", i); + done &=3D ~BIT(i); + continue; + } + aml_chan->status =3D (err & (1 << i)) ? DMA_ERROR : DMA_COMPLETE; + dma_cookie_complete(&aml_chan->desc); + dmaengine_desc_get_callback_invoke(&aml_chan->desc, NULL); + done &=3D ~BIT(i); + } + + /* deal with wch normal complete and error */ + regmap_read(aml_dma->regmap, DMA_BATCH_END, &end); + if (end) + regmap_write(aml_dma->regmap, CLEAR_W_BATCH, end); + + regmap_read(aml_dma->regmap, WCH_DONE, &done); + regmap_read(aml_dma->regmap, WCH_EOC_DONE, &eoc_done); + done =3D done | eoc_done; + + regmap_read(aml_dma->regmap, WCH_ERR, &err); + regmap_read(aml_dma->regmap, WDMA_RESP_ERR, &err_l); + err =3D err | err_l; + + done =3D done | err; + i =3D 0; + while (done) { + i =3D ffs(done) - 1; + aml_chan =3D aml_dma->aml_wch[i]; + regmap_write(aml_dma->regmap, CLEAR_WCH, BIT(aml_chan->chan_id)); + if (!aml_chan) { + dev_err(aml_dma->dma_device.dev, "idx %d wch not initialized\n", i); + done &=3D ~BIT(i); + continue; + } + aml_chan->status =3D (err & (1 << i)) ? DMA_ERROR : DMA_COMPLETE; + dma_cookie_complete(&aml_chan->desc); + dmaengine_desc_get_callback_invoke(&aml_chan->desc, NULL); + done &=3D ~BIT(i); + } + + return IRQ_HANDLED; +} + +static struct dma_chan *aml_of_dma_xlate(struct of_phandle_args *dma_spec,= struct of_dma *ofdma) +{ + struct aml_dma_dev *aml_dma =3D (struct aml_dma_dev *)ofdma->of_dma_data; + struct aml_dma_chan *aml_chan =3D NULL; + u32 type; + u32 phy_chan_id; + + if (dma_spec->args_count !=3D 2) + return NULL; + + type =3D dma_spec->args[0]; + phy_chan_id =3D dma_spec->args[1]; + + if (phy_chan_id >=3D MAX_CHAN_ID) + return NULL; + + if (type =3D=3D DMA_TX) { + aml_chan =3D aml_dma->aml_rch[phy_chan_id]; + if (!aml_chan) { + if (aml_dma->chan_used >=3D aml_dma->chan_nr) { + dev_err(aml_dma->dma_device.dev, "some dma clients err used\n"); + return NULL; + } + aml_chan =3D &aml_dma->aml_chans[aml_dma->chan_used]; + aml_dma->chan_used++; + aml_chan->direction =3D DMA_MEM_TO_DEV; + aml_chan->chan_id =3D phy_chan_id; + aml_chan->reg_offs =3D RCH_REG_BASE + 0x40 * aml_chan->chan_id; + aml_dma->aml_rch[phy_chan_id] =3D aml_chan; + } + } else if (type =3D=3D DMA_RX) { + aml_chan =3D aml_dma->aml_wch[phy_chan_id]; + if (!aml_chan) { + if (aml_dma->chan_used >=3D aml_dma->chan_nr) { + dev_err(aml_dma->dma_device.dev, "some dma clients err used\n"); + return NULL; + } + aml_chan =3D &aml_dma->aml_chans[aml_dma->chan_used]; + aml_dma->chan_used++; + aml_chan->direction =3D DMA_DEV_TO_MEM; + aml_chan->chan_id =3D phy_chan_id; + aml_chan->reg_offs =3D WCH_REG_BASE + 0x40 * aml_chan->chan_id; + aml_dma->aml_wch[phy_chan_id] =3D aml_chan; + } + } else { + dev_err(aml_dma->dma_device.dev, "type %d not supported\n", type); + return NULL; + } + + return dma_get_slave_channel(&aml_chan->chan); +} + +static int aml_dma_probe(struct platform_device *pdev) +{ + struct device_node *np =3D pdev->dev.of_node; + struct dma_device *dma_dev; + struct aml_dma_dev *aml_dma; + int ret, i, len; + u32 chan_nr; + + const struct regmap_config aml_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D 0x3000, + }; + + ret =3D of_property_read_u32(np, "dma-channels", &chan_nr); + if (ret) + return dev_err_probe(&pdev->dev, ret, "failed to read dma-channels\n"); + + len =3D sizeof(struct aml_dma_dev) + sizeof(struct aml_dma_chan) * chan_n= r; + aml_dma =3D devm_kzalloc(&pdev->dev, len, GFP_KERNEL); + if (!aml_dma) + return -ENOMEM; + + aml_dma->chan_nr =3D chan_nr; + + aml_dma->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(aml_dma->base)) + return PTR_ERR(aml_dma->base); + + aml_dma->regmap =3D devm_regmap_init_mmio(&pdev->dev, aml_dma->base, + &aml_regmap_config); + if (IS_ERR_OR_NULL(aml_dma->regmap)) + return PTR_ERR(aml_dma->regmap); + + aml_dma->clk =3D devm_clk_get_enabled(&pdev->dev, NULL); + if (IS_ERR(aml_dma->clk)) + return PTR_ERR(aml_dma->clk); + + aml_dma->irq =3D platform_get_irq(pdev, 0); + + aml_dma->pdev =3D pdev; + aml_dma->dma_device.dev =3D &pdev->dev; + + dma_dev =3D &aml_dma->dma_device; + INIT_LIST_HEAD(&dma_dev->channels); + + /* Initialize channel parameters */ + for (i =3D 0; i < chan_nr; i++) { + struct aml_dma_chan *aml_chan =3D &aml_dma->aml_chans[i]; + + aml_chan->aml_dma =3D aml_dma; + aml_chan->chan.device =3D &aml_dma->dma_device; + dma_cookie_init(&aml_chan->chan); + + /* Add the channel to aml_chan list */ + list_add_tail(&aml_chan->chan.device_node, + &aml_dma->dma_device.channels); + } + aml_dma->chan_used =3D 0; + + dma_set_max_seg_size(dma_dev->dev, SG_MAX_LEN); + + dma_cap_set(DMA_SLAVE, dma_dev->cap_mask); + dma_dev->device_alloc_chan_resources =3D aml_dma_alloc_chan_resources; + dma_dev->device_free_chan_resources =3D aml_dma_free_chan_resources; + dma_dev->device_tx_status =3D aml_dma_tx_status; + dma_dev->device_prep_slave_sg =3D aml_dma_prep_slave_sg; + + dma_dev->device_pause =3D aml_dma_chan_pause; + dma_dev->device_resume =3D aml_dma_chan_resume; + dma_dev->device_terminate_all =3D aml_dma_terminate_all; + dma_dev->device_issue_pending =3D aml_dma_issue_pending; + /* PIO 4 bytes and I2C 1 byte */ + dma_dev->dst_addr_widths =3D BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_SL= AVE_BUSWIDTH_1_BYTE); + dma_dev->directions =3D BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); + dma_dev->residue_granularity =3D DMA_RESIDUE_GRANULARITY_BURST; + + ret =3D dmaenginem_async_device_register(dma_dev); + if (ret) + return dev_err_probe(&pdev->dev, ret, "failed to register dmaenginem\n"); + + ret =3D of_dma_controller_register(np, aml_of_dma_xlate, aml_dma); + if (ret) + goto err_dmaenginem_register; + + regmap_write(aml_dma->regmap, RCH_INT_MASK, 0xffffffff); + regmap_write(aml_dma->regmap, WCH_INT_MASK, 0xffffffff); + + ret =3D devm_request_irq(&pdev->dev, aml_dma->irq, aml_dma_interrupt_hand= ler, + IRQF_SHARED, dev_name(&pdev->dev), aml_dma); + if (ret) { + dev_err(&pdev->dev, "failed to reqest_irq\n"); + goto err_of_dma_controller; + } + + platform_set_drvdata(pdev, aml_dma); + + return 0; + +err_of_dma_controller: + of_dma_controller_free(np); +err_dmaenginem_register: + dma_async_device_unregister(dma_dev); + + return ret; +} + +static void aml_dma_remove(struct platform_device *pdev) +{ + struct aml_dma_dev *aml_dma =3D platform_get_drvdata(pdev); + + of_dma_controller_free((&pdev->dev)->of_node); + dma_async_device_unregister(&aml_dma->dma_device); +} + +static const struct of_device_id aml_dma_ids[] =3D { + { .compatible =3D "amlogic,a9-dma", }, + {}, +}; +MODULE_DEVICE_TABLE(of, aml_dma_ids); + +static struct platform_driver aml_dma_driver =3D { + .probe =3D aml_dma_probe, + .remove =3D aml_dma_remove, + .driver =3D { + .name =3D "aml-dma", + .of_match_table =3D aml_dma_ids, + }, +}; + +module_platform_driver(aml_dma_driver); + +MODULE_DESCRIPTION("GENERAL DMA driver for Amlogic"); +MODULE_AUTHOR("Xianwei Zhao "); +MODULE_LICENSE("GPL"); --=20 2.52.0