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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ae83e9ad26sm114274845ad.28.2026.03.08.16.36.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Mar 2026 16:37:00 -0700 (PDT) From: Sibi Sankar To: robh@kernel.org, krzk+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, bryan.odonoghue@linaro.org, ilpo.jarvinen@linux.intel.com, hansg@kernel.org Cc: conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org Subject: [PATCH V3 1/5] dt-bindings: embedded-controller: Add EC bindings for Qualcomm reference devices Date: Mon, 9 Mar 2026 05:06:42 +0530 Message-Id: <20260308233646.2318676-2-sibi.sankar@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260308233646.2318676-1-sibi.sankar@oss.qualcomm.com> References: <20260308233646.2318676-1-sibi.sankar@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=IYSKmGqa c=1 sm=1 tr=0 ts=69ae081e cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=gEfo2CItAAAA:8 a=pGLkceISAAAA:8 a=EUspDBNiAAAA:8 a=6bqoFnLgofmmdwMbvCAA:9 a=GvdueXVYPmCkWapjIL-Q:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-GUID: uXIhQZoBQ9woQSp04NUB1OqMdirIOtzv X-Proofpoint-ORIG-GUID: uXIhQZoBQ9woQSp04NUB1OqMdirIOtzv X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA4MDIxOCBTYWx0ZWRfX5rwePkJynxF+ kBSHL9SnqdgWAh+iAk6iBZxiz1fNQKmMWIQePuLDNDPggwJHVlI1igUT2YNOI3CSn5J4EccVx7Y jIxb5LF3CjutAMWmTv/ipbR0avJPicRwg+Xmj1OV5FmTqHAICCX1/VvWLmPEvRxwM/5u2TaGZE+ 5uNN+IIn2LXmmpfxqBfTfWbAwLLNoV9AT7ML0tblaMo/ckABMKF+U7ESimY3CWsjcfEnqxdcTva P00NqHprMrN19H+r7cWp/PCcCES6/sASDX4XImEnRQCGP9wZ6eXoUrlxvtFXGXRraZQ6/mdAjrK C0Co4El/DNZqzLx0hu2750AQOi5DbJRaU52zlRngXJkCQQcGAaWAr180GbhfSinB2gENlQTju1K U9LdtibMmJQ5BlQPkar4tfAoDRgOY9T1c2ZXOVre5RQW/BPJXZaZl0QhU6cql40Srra56RD8L6i Y83KuB+vRRI6wNYNjww== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-08_07,2026-03-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 phishscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603080218 Content-Type: text/plain; charset="utf-8" From: Maya Matuszczyk Add bindings for the EC firmware running on Hamoa/Purwa and Glymur reference devices, which run on IT8987 and Nuvoton MCUs respectively. Signed-off-by: Maya Matuszczyk Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar --- .../embedded-controller/qcom,hamoa-ec.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/embedded-controller/q= com,hamoa-ec.yaml diff --git a/Documentation/devicetree/bindings/embedded-controller/qcom,ham= oa-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/qcom,ham= oa-ec.yaml new file mode 100644 index 000000000000..ea093b71d269 --- /dev/null +++ b/Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-ec.y= aml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/embedded-controller/qcom,hamoa-ec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Hamoa Embedded Controller. + +maintainers: + - Sibi Sankar + +description: + Qualcomm Snapdragon based Hamoa/Purwa and Glymur reference devices have = an + EC running on IT8987 and Nuvoton MCU chips respectively. The EC handles = things + like fan control, temperature sensors, access to EC internal state chang= es. + +properties: + compatible: + items: + - enum: + - qcom,glymur-nuvoton-ec + - qcom,hamoa-it8987-ec + - const: qcom,hamoa-ec + + reg: + const: 0x76 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + embedded-controller@76 { + compatible =3D "qcom,hamoa-it8987-ec", "qcom,hamoa-ec"; + reg =3D <0x76>; + + interrupts-extended =3D <&tlmm 66 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +... --=20 2.34.1 From nobody Thu Apr 9 13:31:47 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B61D02FFDEB for ; Sun, 8 Mar 2026 23:37:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ae83e9ad26sm114274845ad.28.2026.03.08.16.37.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Mar 2026 16:37:04 -0700 (PDT) From: Sibi Sankar To: robh@kernel.org, krzk+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, bryan.odonoghue@linaro.org, ilpo.jarvinen@linux.intel.com, hansg@kernel.org Cc: conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, Maya Matuszczyk Subject: [PATCH V3 2/5] platform: arm64: Add driver for EC found on Qualcomm reference devices Date: Mon, 9 Mar 2026 05:06:43 +0530 Message-Id: <20260308233646.2318676-3-sibi.sankar@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260308233646.2318676-1-sibi.sankar@oss.qualcomm.com> References: <20260308233646.2318676-1-sibi.sankar@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: CZLYtVSyU0Lcp5guogK9WahWVMgi-Nni X-Proofpoint-GUID: CZLYtVSyU0Lcp5guogK9WahWVMgi-Nni X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA4MDIxOCBTYWx0ZWRfXwor5u0CwBEIt /k+IHf+mYE+HZc41Mb76Z1v2lyGoKYyNLZxekBknfuLkaD2PF35Udh5erVZbe5snfMfWv745uoR sNNTbfmq4ji/+qdWk8ZG3eKECWtyYztawOb4E53WMT9x11U3+eH+7eSVHoeYdHLtQyLSvPmARwu HsrcEPdpS0uqksSo2ZnLJGW3noscldet2/ScJlHb5KD598DtM2pEuJ9kTC8Yshrc4lZhi2CmHgP FTM9p2CydvO4UEGviQ+GOd+pUhmdVarxf1sCKI550o8yDCg7i72uFGnvzF/sY1h2e+ticmj286K 331bUN5RE6aNa2a2kUPhenVth2LOZC5wVZEOlu2gxGblqm4CdGY6wk7GkgMMILMMC9wL0h3QVdR 4zcmRSf1tGN0+mAmE6g6JPuRS0djJfZ8w3vlW7wUl4CxQ9xPmPq8ebRQHupEYt9zl/MtLG5FH2L jTN4QLDCQomi3Uss0+Q== X-Authority-Analysis: v=2.4 cv=dcqNHHXe c=1 sm=1 tr=0 ts=69ae0823 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=VwQbUJbxAAAA:8 a=pGLkceISAAAA:8 a=EUspDBNiAAAA:8 a=E2FcRaxJAAAA:8 a=689zGLOwWasileE73dUA:9 a=uG9DUKGECoFWVXl0Dc02:22 a=Yev8HTsh1NrKSfoOyGCL:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-08_07,2026-03-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 impostorscore=0 malwarescore=0 priorityscore=1501 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603080218 Content-Type: text/plain; charset="utf-8" Add Embedded controller driver support for Hamoa/Purwa/Glymur qualcomm reference boards. It handles fan control, temperature sensors, access to EC state changes and supports reporting suspend entry/exit to the EC. Co-developed-by: Maya Matuszczyk Signed-off-by: Maya Matuszczyk Signed-off-by: Sibi Sankar --- MAINTAINERS | 7 + drivers/platform/arm64/Kconfig | 12 + drivers/platform/arm64/Makefile | 1 + drivers/platform/arm64/qcom-hamoa-ec.c | 462 +++++++++++++++++++++++++ 4 files changed, 482 insertions(+) create mode 100644 drivers/platform/arm64/qcom-hamoa-ec.c diff --git a/MAINTAINERS b/MAINTAINERS index 2882a67bdf6d..dc72093375ed 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21932,6 +21932,13 @@ S: Supported W: https://wireless.wiki.kernel.org/en/users/Drivers/wcn36xx F: drivers/net/wireless/ath/wcn36xx/ =20 +QUALCOMM HAMOA EMBEDDED CONTROLLER DRIVER +M: Sibi Sankar +L: linux-arm-msm@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-ec.yaml +F: drivers/platform/arm64/qcom-hamoa-ec.c + QUANTENNA QTNFMAC WIRELESS DRIVER M: Igor Mitsyanko R: Sergey Matyukevich diff --git a/drivers/platform/arm64/Kconfig b/drivers/platform/arm64/Kconfig index 10f905d7d6bf..025cdf091f9e 100644 --- a/drivers/platform/arm64/Kconfig +++ b/drivers/platform/arm64/Kconfig @@ -90,4 +90,16 @@ config EC_LENOVO_THINKPAD_T14S =20 Say M or Y here to include this support. =20 +config EC_QCOM_HAMOA + tristate "Embedded Controller driver for Qualcomm Hamoa/Glymur reference = devices" + depends on ARCH_QCOM || COMPILE_TEST + depends on I2C + help + Say M or Y here to enable the Embedded Controller driver for Qualcomm + Snapdragon-based Hamoa/Glymur reference devices. The driver handles fan + control, temperature sensors, access to EC state changes and supports + reporting suspend entry/exit to the EC. + + This driver currently supports Hamoa/Purwa/Glymur reference devices. + endif # ARM64_PLATFORM_DEVICES diff --git a/drivers/platform/arm64/Makefile b/drivers/platform/arm64/Makef= ile index 60c131cff6a1..7681be4a46e9 100644 --- a/drivers/platform/arm64/Makefile +++ b/drivers/platform/arm64/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_EC_ACER_ASPIRE1) +=3D acer-aspire1-ec.o obj-$(CONFIG_EC_HUAWEI_GAOKUN) +=3D huawei-gaokun-ec.o obj-$(CONFIG_EC_LENOVO_YOGA_C630) +=3D lenovo-yoga-c630.o obj-$(CONFIG_EC_LENOVO_THINKPAD_T14S) +=3D lenovo-thinkpad-t14s.o +obj-$(CONFIG_EC_QCOM_HAMOA) +=3D qcom-hamoa-ec.o diff --git a/drivers/platform/arm64/qcom-hamoa-ec.c b/drivers/platform/arm6= 4/qcom-hamoa-ec.c new file mode 100644 index 000000000000..83aa869fad8f --- /dev/null +++ b/drivers/platform/arm64/qcom-hamoa-ec.c @@ -0,0 +1,462 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Maya Matuszczyk + * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#define EC_SCI_EVT_READ_CMD 0x05 +#define EC_FW_VERSION_CMD 0x0e +#define EC_MODERN_STANDBY_CMD 0x23 +#define EC_FAN_DBG_CONTROL_CMD 0x30 +#define EC_SCI_EVT_CONTROL_CMD 0x35 +#define EC_THERMAL_CAP_CMD 0x42 + +#define EC_FW_VERSION_RESP_LEN 4 +#define EC_THERMAL_CAP_RESP_LEN 3 +#define EC_FAN_DEBUG_CMD_LEN 6 +#define EC_FAN_SPEED_DATA_SIZE 4 + +#define EC_MODERN_STANDBY_ENTER 0x01 +#define EC_MODERN_STANDBY_EXIT 0x00 + +#define EC_FAN_DEBUG_MODE_ON BIT(0) +#define EC_FAN_ON BIT(1) +#define EC_FAN_DEBUG_TYPE_PWM BIT(2) +#define EC_MAX_FAN_CNT 2 +#define EC_FAN_NAME_SIZE 20 +#define EC_FAN_MAX_PWM 255 + +enum qcom_ec_sci_events { + EC_FAN1_STATUS_CHANGE_EVT =3D 0x30, + EC_FAN2_STATUS_CHANGE_EVT, + EC_FAN1_SPEED_CHANGE_EVT, + EC_FAN2_SPEED_CHANGE_EVT, + EC_NEW_LUT_SET_EVT, + EC_FAN_PROFILE_SWITCH_EVT, + EC_THERMISTOR_1_THRESHOLD_CROSS_EVT, + EC_THERMISTOR_2_THRESHOLD_CROSS_EVT, + EC_THERMISTOR_3_THRESHOLD_CROSS_EVT, + /* Reserved: 0x39 - 0x3c/0x3f */ + EC_RECOVERED_FROM_RESET_EVT =3D 0x3d, +}; + +struct qcom_ec_version { + u8 main_version; + u8 sub_version; + u8 test_version; +}; + +struct qcom_ec_thermal_cap { +#define EC_THERMAL_FAN_CNT(x) (FIELD_GET(GENMASK(1, 0), (x))) +#define EC_THERMAL_FAN_TYPE(x) (FIELD_GET(GENMASK(4, 2), (x))) +#define EC_THERMAL_THERMISTOR_MASK(x) (FIELD_GET(GENMASK(7, 0), (x))) + u8 fan_cnt; + u8 fan_type; + u8 thermistor_mask; +}; + +struct qcom_ec_cooling_dev { + struct thermal_cooling_device *cdev; + struct device *parent_dev; + u8 fan_id; + u8 state; +}; + +struct qcom_ec { + struct qcom_ec_cooling_dev *ec_cdev; + struct qcom_ec_thermal_cap thermal_cap; + struct qcom_ec_version version; + struct i2c_client *client; + /* EC bus transaction lock */ + struct mutex lock; +}; + +static int qcom_ec_read(struct qcom_ec *ec, u8 cmd, u8 resp_len, u8 *resp) +{ + int ret; + + mutex_lock(&ec->lock); + ret =3D i2c_smbus_read_i2c_block_data(ec->client, cmd, resp_len, resp); + mutex_unlock(&ec->lock); + if (ret < 0) + return ret; + else if (ret =3D=3D 0 || ret =3D=3D 0xff) + return -EOPNOTSUPP; + + if (resp[0] >=3D resp_len) + return -EINVAL; + + return 0; +} + +/* + * EC Device Firmware Version: + * + * Read Response: + * ---------------------------------------------------------------------- + * | Offset | Name | Description | + * ---------------------------------------------------------------------- + * | 0x00 | Byte count | Number of bytes in response | + * | | | (exluding byte count) | + * ---------------------------------------------------------------------- + * | 0x01 | Test-version | Test-version of EC firmware | + * ---------------------------------------------------------------------- + * | 0x02 | Sub-version | Sub-version of EC firmware | + * ---------------------------------------------------------------------- + * | 0x03 | Main-version | Main-version of EC firmware | + * ---------------------------------------------------------------------- + * + */ +static int qcom_ec_read_fw_version(struct device *dev) +{ + struct i2c_client *client =3D to_i2c_client(dev); + struct qcom_ec *ec =3D i2c_get_clientdata(client); + struct qcom_ec_version *version =3D &ec->version; + u8 resp[EC_FW_VERSION_RESP_LEN]; + int ret; + + ret =3D qcom_ec_read(ec, EC_FW_VERSION_CMD, EC_FW_VERSION_RESP_LEN, resp); + if (ret < 0) + return ret; + + version->main_version =3D resp[3]; + version->sub_version =3D resp[2]; + version->test_version =3D resp[1]; + + dev_dbg(dev, "EC Version %d.%d.%d\n", + version->main_version, version->sub_version, version->test_version); + + return 0; +} + +/* + * EC Device Thermal Capabilities: + * + * Read Response: + * ---------------------------------------------------------------------- + * | Offset | Name | Description | + * ---------------------------------------------------------------------- + * | 0x00 | Byte count | Number of bytes in response | + * | | | (exluding byte count) | + * ---------------------------------------------------------------------- + * | 0x02 (LSB) | EC Thermal | Bit 0-1: Number of fans | + * | 0x3 | Capabilities | Bit 2-4: Type of fan | + * | | | Bit 5-6: Reserved | + * | | | Bit 7: Data Valid/Invalid | + * | | | (Valid - 1, Invalid - 0) + * | | | Bit 8-15: Thermistor 0 - 7 presence | + * | | | (0 present, 1 absent) | + * ---------------------------------------------------------------------- + * + */ +static int qcom_ec_thermal_capabilities(struct device *dev) +{ + struct i2c_client *client =3D to_i2c_client(dev); + struct qcom_ec *ec =3D i2c_get_clientdata(client); + struct qcom_ec_thermal_cap *cap =3D &ec->thermal_cap; + u8 resp[EC_THERMAL_CAP_RESP_LEN]; + int ret; + + ret =3D qcom_ec_read(ec, EC_THERMAL_CAP_CMD, EC_THERMAL_CAP_RESP_LEN, res= p); + if (ret < 0) + return ret; + + cap->fan_cnt =3D max(EC_MAX_FAN_CNT, EC_THERMAL_FAN_CNT(resp[1])); + cap->fan_type =3D EC_THERMAL_FAN_TYPE(resp[1]); + cap->thermistor_mask =3D EC_THERMAL_THERMISTOR_MASK(resp[2]); + + dev_dbg(dev, "Fan count: %d Fan Type: %d Thermistor Mask: %d\n", + cap->fan_cnt, cap->fan_type, cap->thermistor_mask); + + return 0; +} + +static irqreturn_t qcom_ec_irq(int irq, void *data) +{ + struct qcom_ec *ec =3D data; + struct device *dev =3D &ec->client->dev; + int val; + + mutex_lock(&ec->lock); + val =3D i2c_smbus_read_byte_data(ec->client, EC_SCI_EVT_READ_CMD); + mutex_unlock(&ec->lock); + if (val < 0) { + dev_err(dev, "Failed to read EC SCI Event: %d\n", val); + return IRQ_HANDLED; + } + + switch (val) { + case EC_FAN1_STATUS_CHANGE_EVT: + dev_dbg(dev, "Fan1 status changed\n"); + break; + case EC_FAN2_STATUS_CHANGE_EVT: + dev_dbg(dev, "Fan2 status changed\n"); + break; + case EC_FAN1_SPEED_CHANGE_EVT: + dev_dbg(dev, "Fan1 speed crossed low/high trip point\n"); + break; + case EC_FAN2_SPEED_CHANGE_EVT: + dev_dbg(dev, "Fan2 speed crossed low/high trip point\n"); + break; + case EC_NEW_LUT_SET_EVT: + dev_dbg(dev, "New LUT set\n"); + break; + case EC_FAN_PROFILE_SWITCH_EVT: + dev_dbg(dev, "FAN Profile switched\n"); + break; + case EC_THERMISTOR_1_THRESHOLD_CROSS_EVT: + dev_dbg(dev, "Thermistor 1 threshold crossed\n"); + break; + case EC_THERMISTOR_2_THRESHOLD_CROSS_EVT: + dev_dbg(dev, "Thermistor 2 threshold crossed\n"); + break; + case EC_THERMISTOR_3_THRESHOLD_CROSS_EVT: + dev_dbg(dev, "Thermistor 3 threshold crossed\n"); + break; + case EC_RECOVERED_FROM_RESET_EVT: + dev_dbg(dev, "EC recovered from reset\n"); + break; + default: + dev_dbg(dev, "Unknown EC event: %d\n", val); + break; + } + + return IRQ_HANDLED; +} + +static int qcom_ec_sci_evt_control(struct device *dev, bool enable) +{ + struct i2c_client *client =3D to_i2c_client(dev); + struct qcom_ec *ec =3D i2c_get_clientdata(client); + u8 control =3D enable ? 1 : 0; + int ret; + + mutex_lock(&ec->lock); + ret =3D i2c_smbus_write_byte_data(client, EC_SCI_EVT_CONTROL_CMD, control= ); + mutex_unlock(&ec->lock); + + return ret; +} + +static int qcom_ec_fan_get_max_state(struct thermal_cooling_device *cdev, = unsigned long *state) +{ + *state =3D EC_FAN_MAX_PWM; + + return 0; +} + +static int qcom_ec_fan_get_cur_state(struct thermal_cooling_device *cdev, = unsigned long *state) +{ + struct qcom_ec_cooling_dev *ec_cdev =3D cdev->devdata; + + *state =3D ec_cdev->state; + + return 0; +} + +/* + * Fan Debug control command: + * + * Command Payload: + * -----------------------------------------------------------------------= ------- + * | Offset | Name | Description | + * -----------------------------------------------------------------------= ------- + * | 0x00 | Command | Fan control command | + * -----------------------------------------------------------------------= ------- + * | 0x01 | Fan ID | 0x1 : Fan 1 | + * | | | 0x2 : Fan 2 | + * -----------------------------------------------------------------------= ------- + * | 0x02 | Byte count =3D 4| Size of data to set fan speed | + * -----------------------------------------------------------------------= ------- + * | 0x03 | Mode | Bit 0: Debug Mode On/Off (0 - OFF, 1 - ON ) | + * | | | Bit 1: Fan On/Off (0 - Off, 1 - ON) | + * | | | Bit 2: Debug Type (0 - RPM, 1 - PWM) | + * -----------------------------------------------------------------------= ------- + * | 0x04 (LSB) | Speed in RPM | RPM value, if mode selected is RPM | + * | 0x05 | | | + * -----------------------------------------------------------------------= ------- + * | 0x06 | Speed in PWM | PWM value, if mode selected is PWM (0 - 255) | + * _______________________________________________________________________= _______ + * + */ +static int qcom_ec_fan_set_cur_state(struct thermal_cooling_device *cdev, = unsigned long state) +{ + struct qcom_ec_cooling_dev *ec_cdev =3D cdev->devdata; + struct device *dev =3D ec_cdev->parent_dev; + struct i2c_client *client =3D to_i2c_client(dev); + + u8 request[6] =3D { ec_cdev->fan_id, EC_FAN_SPEED_DATA_SIZE, + EC_FAN_DEBUG_MODE_ON | EC_FAN_ON | EC_FAN_DEBUG_TYPE_PWM, + 0, 0, state }; + int ret; + + ret =3D i2c_smbus_write_i2c_block_data(client, EC_FAN_DBG_CONTROL_CMD, + sizeof(request), request); + if (ret) { + dev_err(dev, "Failed to set fan pwm: %d\n", ret); + return ret; + } + + ec_cdev->state =3D state; + + return 0; +} + +static const struct thermal_cooling_device_ops qcom_ec_thermal_ops =3D { + .get_max_state =3D qcom_ec_fan_get_max_state, + .get_cur_state =3D qcom_ec_fan_get_cur_state, + .set_cur_state =3D qcom_ec_fan_set_cur_state, +}; + +static int qcom_ec_resume(struct device *dev) +{ + struct i2c_client *client =3D to_i2c_client(dev); + struct qcom_ec *ec =3D i2c_get_clientdata(client); + int ret; + + mutex_lock(&ec->lock); + ret =3D i2c_smbus_write_byte_data(client, EC_MODERN_STANDBY_CMD, EC_MODER= N_STANDBY_ENTER); + mutex_unlock(&ec->lock); + + return ret; +} + +static int qcom_ec_suspend(struct device *dev) +{ + struct i2c_client *client =3D to_i2c_client(dev); + struct qcom_ec *ec =3D i2c_get_clientdata(client); + int ret; + + mutex_lock(&ec->lock); + ret =3D i2c_smbus_write_byte_data(client, EC_MODERN_STANDBY_CMD, EC_MODER= N_STANDBY_EXIT); + mutex_unlock(&ec->lock); + + return ret; +} + +static int qcom_ec_probe(struct i2c_client *client) +{ + struct qcom_ec_cooling_dev *cdev; + struct device *dev =3D &client->dev; + struct qcom_ec *ec; + int ret, i; + + ec =3D devm_kzalloc(dev, sizeof(*ec), GFP_KERNEL); + if (!ec) + return -ENOMEM; + + mutex_init(&ec->lock); + ec->client =3D client; + + ret =3D devm_request_threaded_irq(dev, client->irq, NULL, qcom_ec_irq, + IRQF_ONESHOT, "qcom_ec", ec); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to get irq\n"); + + i2c_set_clientdata(client, ec); + + ret =3D qcom_ec_read_fw_version(dev); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to read ec firmware version\n"); + + ret =3D qcom_ec_thermal_capabilities(dev); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to read thermal capabilities\n"); + + ret =3D qcom_ec_sci_evt_control(dev, true); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to enable SCI events\n"); + + ec->ec_cdev =3D devm_kcalloc(dev, ec->thermal_cap.fan_cnt, sizeof(*ec->ec= _cdev), GFP_KERNEL); + if (!ec->ec_cdev) + return -ENOMEM; + + for (i =3D 0; i < ec->thermal_cap.fan_cnt; i++) { + struct qcom_ec_cooling_dev *ec_cdev =3D &ec->ec_cdev[i]; + char name[EC_FAN_NAME_SIZE]; + + snprintf(name, EC_FAN_NAME_SIZE, "qcom_ec_fan_%d", i); + ec_cdev->fan_id =3D i + 1; + ec_cdev->parent_dev =3D dev; + + ec_cdev->cdev =3D thermal_cooling_device_register(name, ec_cdev, + &qcom_ec_thermal_ops); + if (IS_ERR(ec_cdev->cdev)) { + dev_err_probe(dev, PTR_ERR(cdev), + "Thermal cooling device registration failed\n"); + ret =3D -EINVAL; + goto unroll_cooling_dev; + } + } + + return 0; + +unroll_cooling_dev: + for (i--; i >=3D 0; i--) { + struct qcom_ec_cooling_dev *ec_cdev =3D &ec->ec_cdev[i]; + + if (ec_cdev->cdev) { + thermal_cooling_device_unregister(ec_cdev->cdev); + ec_cdev->cdev =3D NULL; + } + } + + return ret; +} + +static void qcom_ec_remove(struct i2c_client *client) +{ + struct qcom_ec *ec =3D i2c_get_clientdata(client); + struct device *dev =3D &client->dev; + int ret; + + ret =3D qcom_ec_sci_evt_control(dev, false); + if (ret < 0) + dev_err(dev, "Failed to disable SCI events: %d\n", ret); + + for (int i =3D 0; i < ec->thermal_cap.fan_cnt; i++) { + struct qcom_ec_cooling_dev *ec_cdev =3D &ec->ec_cdev[i]; + + if (ec_cdev->cdev) { + thermal_cooling_device_unregister(ec_cdev->cdev); + ec_cdev->cdev =3D NULL; + } + } +} + +static const struct of_device_id qcom_ec_of_match[] =3D { + { .compatible =3D "qcom,hamoa-ec" }, + {} +}; +MODULE_DEVICE_TABLE(of, qcom_ec_of_match); + +static const struct i2c_device_id qcom_ec_i2c_id_table[] =3D { + { "qcom-hamoa-ec", }, + {} +}; +MODULE_DEVICE_TABLE(i2c, qcom_ec_i2c_id_table); + +static DEFINE_SIMPLE_DEV_PM_OPS(qcom_ec_pm_ops, + qcom_ec_suspend, + qcom_ec_resume); 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ae83e9ad26sm114274845ad.28.2026.03.08.16.37.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Mar 2026 16:37:09 -0700 (PDT) From: Sibi Sankar To: robh@kernel.org, krzk+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, bryan.odonoghue@linaro.org, ilpo.jarvinen@linux.intel.com, hansg@kernel.org Cc: conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org Subject: [PATCH V3 3/5] arm64: dts: qcom: glymur-crd: Add Embedded controller node Date: Mon, 9 Mar 2026 05:06:44 +0530 Message-Id: <20260308233646.2318676-4-sibi.sankar@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260308233646.2318676-1-sibi.sankar@oss.qualcomm.com> References: <20260308233646.2318676-1-sibi.sankar@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=IdqKmGqa c=1 sm=1 tr=0 ts=69ae0826 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=h-fhkJo0eXD2C244oGgA:9 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: CQ4H5e78izzfVGS4Gzwc7IewKfec8YVW X-Proofpoint-ORIG-GUID: CQ4H5e78izzfVGS4Gzwc7IewKfec8YVW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA4MDIxOCBTYWx0ZWRfX3mfyIOOye0M1 +VL+O41WNQ3a3upC2DilDxXPtX3MUO3aNAggqhh0J//vVO2i7j/wE57YaIdLUTiDMSM+qKXShV/ NVlQVlGtW71HxcrELWRlxQ89q4eKyhaJbUHdMRwwLjQqPaqcru4/Cz1XC8KjX7ZKbIXV2adaott FNKeALLFx/eEU0CDTSsdsrPAn3cFT+73+pZMyHrLH4Xe0ZrJ0rURhU9VqiiaU2f+CVCY7qb4jG7 p57zSlbi8GK/hFo5EfYngrTH+X/2SQXicuuxFp8uGMvdpvavKvc1e00VnakopP7HR+pu836urat 29ofOXE3M44ub4TwcVzb7wBOshqf/PgIBr1ErwZ90HcrTkTxcw7vy+pxxMX8yBRLBFoWY41XXOx v1W0nMaURtJdg/T8rbDYTFvSP0rls481tR1BjOqZuRJtDwV1oQJQVDG3hqEBPnOeg9miOzzTvK2 Wkolg1wJpPmUVZoiQDg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-08_07,2026-03-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 malwarescore=0 clxscore=1015 phishscore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603080218 Content-Type: text/plain; charset="utf-8" Add embedded controller node for Glymur CRDs which adds fan control, temperature sensors, access to EC state changes through SCI events and suspend entry/exit notifications to the EC. Signed-off-by: Sibi Sankar --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/= qcom/glymur-crd.dts index 877945319012..94abef7f0f1f 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -367,6 +367,22 @@ vreg_l4h_e0_1p2: ldo4 { }; }; =20 +&i2c9 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + embedded-controller@76 { + compatible =3D "qcom,glymur-nuvoton-ec", "qcom,hamoa-ec"; + reg =3D <0x76>; + + interrupts-extended =3D <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 =3D <&ec_int_n_default>; + pinctrl-names =3D "default"; + }; +}; + &pcie3b { vddpe-3v3-supply =3D <&vreg_nvmesec>; =20 @@ -490,6 +506,12 @@ &tlmm { <10 2>, /* OOB UART */ <44 4>; /* Security SPI (TPM) */ =20 + ec_int_n_default: ec-int-n-state { + pins =3D "gpio66"; + function =3D "gpio"; + bias-disable; + }; + pcie4_default: pcie4-default-state { clkreq-n-pins { pins =3D "gpio147"; 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Signed-off-by: Sibi Sankar --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qco= m/x1-crd.dtsi index ded96fb43489..29a1aeb98353 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -1042,6 +1042,16 @@ eusb6_repeater: redriver@4f { =20 #phy-cells =3D <0>; }; + + embedded-controller@76 { + compatible =3D "qcom,hamoa-it8987-ec", "qcom,hamoa-ec"; + reg =3D <0x76>; + + interrupts-extended =3D <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 =3D <&ec_int_n_default>; + pinctrl-names =3D "default"; + }; }; =20 &i2c7 { @@ -1485,6 +1495,12 @@ &tlmm { <44 4>, /* SPI (TPM) */ <238 1>; /* UFS Reset */ =20 + ec_int_n_default: ec-int-n-state { + pins =3D "gpio66"; + function =3D "gpio"; + bias-disable; + }; + edp_reg_en: edp-reg-en-state { pins =3D "gpio70"; function =3D "gpio"; --=20 2.34.1 From nobody Thu Apr 9 13:31:47 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07CF735DA71 for ; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ae83e9ad26sm114274845ad.28.2026.03.08.16.37.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Mar 2026 16:37:17 -0700 (PDT) From: Sibi Sankar To: robh@kernel.org, krzk+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, bryan.odonoghue@linaro.org, ilpo.jarvinen@linux.intel.com, hansg@kernel.org Cc: conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org Subject: [PATCH V3 5/5] arm64: dts: qcom: hamoa-iot-evk: Add Embedded controller node Date: Mon, 9 Mar 2026 05:06:46 +0530 Message-Id: <20260308233646.2318676-6-sibi.sankar@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260308233646.2318676-1-sibi.sankar@oss.qualcomm.com> References: <20260308233646.2318676-1-sibi.sankar@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA4MDIxOCBTYWx0ZWRfXyFy8rcsYfoMS PwutuRSE1C/a3Y0vNljgTmJczjCWubfXiK6qApZSWyQ9ExcFoGus5p4auhgQ1zQTSKNz41BZ0nW bnkNsCi/Zo47Zvk9xv+cxTnJe9j8KX/7DRVdHbmivVSs2+wgdq1Lzq5LEJvbTWQXo84qQSwKGaw GveePHgP4BJmFygJelnCccnSFiE9JNaqPJI758Huz2wI+o4z/Hu02mseRyQ3A67Sj94XERGPofB Jtfbj4THqTaex5Kk9MhcNNECIZs69tU/LO28ye+muwZYGhyc6jRO29FxEQySXAJ9wOSlu3M3D/l KYys+brbJgfoqQ9UY0+RuhzKJVkEk2bf41NV4nziyh+3df8i9Ef2oFKNO7nMJ2Iw4nJTeaoJIUC DLTsQDuXV91z2Q5H8A872G4ngM4BkZh3MHgXrb0aNV7yxsbAqy27WbAOAqF9ilO/WjbAglIq3w0 i7FHr43scDp6EpF+qqA== X-Proofpoint-ORIG-GUID: m577wVZuOkQ894txu2Wj8gfCS09jbW-y X-Authority-Analysis: v=2.4 cv=QZtrf8bv c=1 sm=1 tr=0 ts=69ae082f cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=ltsv1nNgzXx585P2vnAA:9 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: m577wVZuOkQ894txu2Wj8gfCS09jbW-y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-08_07,2026-03-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 phishscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603080218 Content-Type: text/plain; charset="utf-8" Add embedded controller node for Hamoa IOT EVK boards which adds fan control, temperature sensors, access to EC internal state changes and suspend entry/exit notifications to the EC. Signed-off-by: Sibi Sankar --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 10 ++++++++++ arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 6 ++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/d= ts/qcom/hamoa-iot-evk.dts index 630642baa435..3cbbc4a0dfdf 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -799,6 +799,16 @@ eusb6_repeater: redriver@4f { pinctrl-0 =3D <&eusb6_reset_n>; pinctrl-names =3D "default"; }; + + embedded-controller@76 { + compatible =3D "qcom,hamoa-it8987-ec", "qcom,hamoa-ec"; + reg =3D <0x76>; + + interrupts-extended =3D <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 =3D <&ec_int_n_default>; + pinctrl-names =3D "default"; + }; }; =20 &i2c7 { diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/= dts/qcom/hamoa-iot-som.dtsi index b8e3e04a6fbd..763399393daf 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -475,6 +475,12 @@ &remoteproc_cdsp { &tlmm { gpio-reserved-ranges =3D <34 2>; /* TPM LP & INT */ =20 + ec_int_n_default: ec-int-n-state { + pins =3D "gpio66"; + function =3D "gpio"; + bias-disable; + }; + pcie3_default: pcie3-default-state { clkreq-n-pins { pins =3D "gpio144"; --=20 2.34.1