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Bottomley" , linux-arm-msm@vger.kernel.org (open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER...), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 11/12] scsi: ufs: ufs-qcom: Implement vops apply_tx_eqtr_settings() Date: Sun, 8 Mar 2026 08:14:08 -0700 Message-Id: <20260308151409.3779137-12-can.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260308151409.3779137-1-can.guo@oss.qualcomm.com> References: <20260308151409.3779137-1-can.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=U5qfzOru c=1 sm=1 tr=0 ts=69ad9286 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=smRfVIh15VBtCzV98ssA:9 X-Proofpoint-ORIG-GUID: SNyu7LGF_5i8nOpVZPw9pTJEERCfQP5n X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA4MDE0MCBTYWx0ZWRfXxRRrZHpP4IFu NojZIqEFtZgxyAnwoEVl1MX3Txpz50Ge/+NFRr01J49KydSDJoCT+yrw6eCJqHLGVfNa5I/aIYD suTgaXnS4aEXR3CX+6bI3eQY1jUQlaj/gWbIyP+f6RnTS4G96+CIQ/PYtpD+mJDTpqpCseArwM5 uH6hyWVe3S6onRmdsimeFhVMIlLJbIPzoucU8avCJ29ISWAvaJLHRn06Jy61nYHT3Nx/FtaiZNC OVHKmkofq5sIgz96KAnUZFvEqEVfNr8g3F4Qr7iMztXkhb08Nt/I1xk7PXsLLYiLmJ4ujmYUzUH tj2PPUAZIOzPP4PIK13i4cxx/5gd8g4kB2W9JLGAUlrHqshvLbzq0RzRbyqpXZpkX3N814WE4y4 QL8pJZIf27u+S6oSkhMd/2KGBuhY44295HXQLUgtV8d+nWaUWHSHHwfN5qbmkbCJaD0iUMeMH62 WfR45BVUwRQdlq8nspw== X-Proofpoint-GUID: SNyu7LGF_5i8nOpVZPw9pTJEERCfQP5n X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-08_04,2026-03-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603080140 Content-Type: text/plain; charset="utf-8" On some platforms, when Host Software triggers TX Equalization Training, HW does not take TX EQTR settings programmed in PA_TxEQTRSetting, instead HW takes TX EQTR settings from PA_TxEQG1Setting. Implement vops apply_tx_eqtr_setting() to work around it by programming TX EQTR settings to PA_TxEQG1Setting during TX EQTR procedure. Signed-off-by: Can Guo --- drivers/ufs/host/ufs-qcom.c | 31 +++++++++++++++++++++++++++++++ drivers/ufs/host/ufs-qcom.h | 2 ++ 2 files changed, 33 insertions(+) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 3e989c683c29..a7feef2385fd 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -2827,6 +2827,26 @@ static int ufs_qcom_get_rx_fom(struct ufs_hba *hba, return 0; } =20 +static int ufs_qcom_apply_tx_eqtr_settings(struct ufs_hba *hba, + struct ufs_pa_layer_attr *pwr_mode, + struct tx_eqtr_iter *h_iter, + struct tx_eqtr_iter *d_iter) +{ + struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); + u32 setting =3D 0; + int lane; + + if (host->hw_ver.major !=3D 0x7 || host->hw_ver.minor > 0x1) + return 0; + + for (lane =3D 0; lane < h_iter->num_lanes; lane++) { + setting |=3D TX_HS_PRESHOOT_BITS(lane, h_iter->preshoot); + setting |=3D TX_HS_DEEMPHASIS_BITS(lane, h_iter->deemphasis); + } + + return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXEQG1SETTING), setting); +} + static int ufs_qcom_tx_eqtr_notify(struct ufs_hba *hba, enum ufs_notify_change_status status, struct ufs_pa_layer_attr *pwr_mode) @@ -2849,6 +2869,11 @@ static int ufs_qcom_tx_eqtr_notify(struct ufs_hba *h= ba, return 0; =20 if (status =3D=3D PRE_CHANGE) { + ret =3D ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TXEQG1SETTING), + &host->saved_tx_eq_g1_setting); + if (ret) + return ret; + /* PMC to target HS Gear. */ ret =3D ufshcd_change_power_mode(hba, pwr_mode, UFSHCD_PMC_POLICY_DONT_FORCE); @@ -2856,6 +2881,11 @@ static int ufs_qcom_tx_eqtr_notify(struct ufs_hba *h= ba, dev_err(hba->dev, "%s: Failed to PMC to target HS-G%u, Rate-%s: %d\n", __func__, gear, UFS_HS_RATE_STRING(rate), ret); } else { + ret =3D ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXEQG1SETTING), + host->saved_tx_eq_g1_setting); + if (ret) + return ret; + /* PMC back to HS-G1. */ ret =3D ufshcd_change_power_mode(hba, &pwr_mode_hs_g1, UFSHCD_PMC_POLICY_DONT_FORCE); @@ -2898,6 +2928,7 @@ static const struct ufs_hba_variant_ops ufs_hba_qcom_= vops =3D { .config_esi =3D ufs_qcom_config_esi, .freq_to_gear_speed =3D ufs_qcom_freq_to_gear_speed, .get_rx_fom =3D ufs_qcom_get_rx_fom, + .apply_tx_eqtr_settings =3D ufs_qcom_apply_tx_eqtr_settings, .tx_eqtr_notify =3D ufs_qcom_tx_eqtr_notify, }; =20 diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 66fb42453e5c..ebe4e07c7da1 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -350,6 +350,8 @@ struct ufs_qcom_host { u32 phy_gear; =20 bool esi_enabled; + + u32 saved_tx_eq_g1_setting; }; =20 struct ufs_qcom_drvdata { --=20 2.34.1