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Sat, 07 Mar 2026 22:49:17 -0800 (PST) From: Pengyu Luo To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Krishna Manikandan , Jonathan Marek Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Tianyu Gao , White Lewis , Pengyu Luo , Krzysztof Kozlowski Subject: [PATCH v4 1/4] dt-bindings: display: msm-dsi-phy-7nm: Add SC8280XP Date: Sun, 8 Mar 2026 14:48:32 +0800 Message-ID: <20260308064835.479356-2-mitltlatltl@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260308064835.479356-1-mitltlatltl@gmail.com> References: <20260308064835.479356-1-mitltlatltl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since SC8280XP and SA8775P have the same values for the REVISION_ID registers, then we fallback to SA8775P compatible. Signed-off-by: Pengyu Luo Reviewed-by: Krzysztof Kozlowski --- v4: There were no changes to the patch. --- Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml= b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml index 9a9a6c4abf..532f371829 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml @@ -32,6 +32,7 @@ properties: - items: - enum: - qcom,qcs8300-dsi-phy-5nm + - qcom,sc8280xp-dsi-phy-5nm - const: qcom,sa8775p-dsi-phy-5nm =20 reg: --=20 2.53.0 From nobody Thu Apr 9 13:27:13 2026 Received: from mail-pg1-f182.google.com (mail-pg1-f182.google.com [209.85.215.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A88CE265CA6 for ; Sun, 8 Mar 2026 06:49:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Since SC8280XP and SA8775P have the same DSI version(2.5.1), then we fallback to SA8775P compatible. Signed-off-by: Pengyu Luo Reviewed-by: Krzysztof Kozlowski --- v4: There were no changes to the patch. --- .../devicetree/bindings/display/msm/dsi-controller-main.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-m= ain.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-mai= n.yaml index eb6d38dabb..617dd110db 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -49,6 +49,7 @@ properties: - items: - enum: - qcom,qcs8300-dsi-ctrl + - qcom,sc8280xp-dsi-ctrl - const: qcom,sa8775p-dsi-ctrl - const: qcom,mdss-dsi-ctrl - enum: --=20 2.53.0 From nobody Thu Apr 9 13:27:13 2026 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D746B254B19 for ; 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charset="utf-8" Document DSI controller and DSI phy on SC8280XP platform. Signed-off-by: Pengyu Luo Reviewed-by: Krzysztof Kozlowski --- v4: There were no changes to the patch. --- .../display/msm/qcom,sc8280xp-mdss.yaml | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-md= ss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.= yaml index af79406e16..a710cc84ec 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-mdss.yaml @@ -50,6 +50,22 @@ patternProperties: - qcom,sc8280xp-dp - qcom,sc8280xp-edp =20 + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,sc8280xp-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,sc8280xp-dsi-phy-5nm + unevaluatedProperties: false =20 examples: @@ -129,6 +145,20 @@ examples: }; }; =20 + port@1 { + reg =3D <1>; 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Sat, 07 Mar 2026 22:49:47 -0800 (PST) Received: from nuvole ([109.166.36.159]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ae840c9a0csm72503225ad.91.2026.03.07.22.49.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Mar 2026 22:49:46 -0800 (PST) From: Pengyu Luo To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Krishna Manikandan , Jonathan Marek Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Tianyu Gao , White Lewis , Pengyu Luo , Dmitry Baryshkov , Konrad Dybcio Subject: [PATCH v4 4/4] arm64: dts: qcom: sc8280xp: Add dsi nodes on SC8280XP Date: Sun, 8 Mar 2026 14:48:35 +0800 Message-ID: <20260308064835.479356-5-mitltlatltl@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260308064835.479356-1-mitltlatltl@gmail.com> References: <20260308064835.479356-1-mitltlatltl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The DT configuration follows other Samsung 5nm-based Qualcomm SOCs, utilizing the same register layouts and clock structures. However, DSI won't work properly for now until we submit dispcc fixes. And some DSC enabled panels require DPU timing calculation fixes too. (hdisplay / width timing round errors cause the fifo error) Co-developed-by: Tianyu Gao Signed-off-by: Tianyu Gao Signed-off-by: Pengyu Luo Tested-by: White Lewis # HUAWEI Gaokun3 Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- v4: add missing comma --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 404 ++++++++++++++++++++++++- 1 file changed, 396 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 706eb1309d..73d38f1d69 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -5,6 +5,7 @@ */ =20 #include +#include #include #include #include @@ -4652,13 +4653,31 @@ ports { =20 port@0 { reg =3D <0>; + mdss0_intf0_out: endpoint { remote-endpoint =3D <&mdss0_dp0_in>; }; }; =20 + port@1 { + reg =3D <1>; + + mdss0_intf1_out: endpoint { + remote-endpoint =3D <&mdss0_dsi0_in>; + }; + }; + + port@2 { + reg =3D <2>; + + mdss0_intf2_out: endpoint { + remote-endpoint =3D <&mdss0_dsi1_in>; + }; + }; + port@4 { reg =3D <4>; + mdss0_intf4_out: endpoint { remote-endpoint =3D <&mdss0_dp1_in>; }; @@ -4666,6 +4685,7 @@ mdss0_intf4_out: endpoint { =20 port@5 { reg =3D <5>; + mdss0_intf5_out: endpoint { remote-endpoint =3D <&mdss0_dp3_in>; }; @@ -4673,6 +4693,7 @@ mdss0_intf5_out: endpoint { =20 port@6 { reg =3D <6>; + mdss0_intf6_out: endpoint { remote-endpoint =3D <&mdss0_dp2_in>; }; @@ -4791,6 +4812,189 @@ opp-810000000 { }; }; =20 + mdss0_dsi0: dsi@ae94000 { + compatible =3D "qcom,sc8280xp-dsi-ctrl", + "qcom,sa8775p-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg =3D <0 0x0ae94000 0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss0>; + interrupts =3D <4>; + + clocks =3D <&dispcc0 DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc0 DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc0 DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc0 DISP_CC_MDSS_ESC0_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc0 DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmhpd SC8280XP_MMCX>; + + refgen-supply =3D <&refgen>; + + phys =3D <&mdss0_dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss0_dsi0_in: endpoint { + remote-endpoint =3D <&mdss0_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss0_dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss0_dsi0_phy: phy@ae94400 { + compatible =3D "qcom,sc8280xp-dsi-phy-5nm", + "qcom,sa8775p-dsi-phy-5nm"; + reg =3D <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x280>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + + status =3D "disabled"; + }; + + mdss0_dsi1: dsi@ae96000 { + compatible =3D "qcom,sc8280xp-dsi-ctrl", + "qcom,sa8775p-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg =3D <0 0x0ae96000 0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss0>; + interrupts =3D <5>; + + clocks =3D <&dispcc0 DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc0 DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc0 DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc0 DISP_CC_MDSS_ESC1_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc0 DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents =3D <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmhpd SC8280XP_MMCX>; + + refgen-supply =3D <&refgen>; + + phys =3D <&mdss0_dsi1_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss0_dsi1_in: endpoint { + remote-endpoint =3D <&mdss0_intf2_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss0_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss0_dsi1_phy: phy@ae96400 { + compatible =3D "qcom,sc8280xp-dsi-phy-5nm", + "qcom,sa8775p-dsi-phy-5nm"; + reg =3D <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x280>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + + status =3D "disabled"; + }; + mdss0_dp1: displayport-controller@ae98000 { compatible =3D "qcom,sc8280xp-dp"; reg =3D <0 0xae98000 0 0x200>, @@ -5080,10 +5284,10 @@ dispcc0: clock-controller@af00000 { <&mdss0_dp2_phy 1>, <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>, - <0>, - <0>, - <0>, - <0>; + <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; power-domains =3D <&rpmhpd SC8280XP_MMCX>; =20 #clock-cells =3D <1>; @@ -6011,13 +6215,31 @@ ports { =20 port@0 { reg =3D <0>; + mdss1_intf0_out: endpoint { remote-endpoint =3D <&mdss1_dp0_in>; }; }; =20 + port@1 { + reg =3D <1>; + + mdss1_intf1_out: endpoint { + remote-endpoint =3D <&mdss1_dsi0_in>; + }; + }; + + port@2 { + reg =3D <2>; + + mdss1_intf2_out: endpoint { + remote-endpoint =3D <&mdss1_dsi1_in>; + }; + }; + port@4 { reg =3D <4>; + mdss1_intf4_out: endpoint { remote-endpoint =3D <&mdss1_dp1_in>; }; @@ -6025,6 +6247,7 @@ mdss1_intf4_out: endpoint { =20 port@5 { reg =3D <5>; + mdss1_intf5_out: endpoint { remote-endpoint =3D <&mdss1_dp3_in>; }; @@ -6032,6 +6255,7 @@ mdss1_intf5_out: endpoint { =20 port@6 { reg =3D <6>; + mdss1_intf6_out: endpoint { remote-endpoint =3D <&mdss1_dp2_in>; }; @@ -6147,6 +6371,170 @@ opp-810000000 { }; }; =20 + mdss1_dsi0: dsi@22094000 { + compatible =3D "qcom,sc8280xp-dsi-ctrl", + "qcom,sa8775p-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg =3D <0 0x22094000 0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss1>; + interrupts =3D <4>; + + clocks =3D <&dispcc1 DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc1 DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc1 DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc1 DISP_CC_MDSS_ESC0_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc1 DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmhpd SC8280XP_MMCX>; + + refgen-supply =3D <&refgen>; + + phys =3D <&mdss1_dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss1_dsi0_in: endpoint { + remote-endpoint =3D <&mdss1_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss1_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss1_dsi0_phy: phy@22094400 { + compatible =3D "qcom,sc8280xp-dsi-phy-5nm", + "qcom,sa8775p-dsi-phy-5nm"; + reg =3D <0 0x22094400 0 0x200>, + <0 0x22094600 0 0x280>, + <0 0x22094900 0 0x280>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + + status =3D "disabled"; + }; + + mdss1_dsi1: dsi@22096000 { + compatible =3D "qcom,sc8280xp-dsi-ctrl", + "qcom,sa8775p-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg =3D <0 0x22096000 0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss1>; + interrupts =3D <5>; + + clocks =3D <&dispcc1 DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc1 DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc1 DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc1 DISP_CC_MDSS_ESC1_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc1 DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents =3D <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss1_dsi1_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmhpd SC8280XP_MMCX>; + + refgen-supply =3D <&refgen>; + + phys =3D <&mdss1_dsi1_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss1_dsi1_in: endpoint { + remote-endpoint =3D <&mdss1_intf2_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss1_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss1_dsi1_phy: phy@22096400 { + compatible =3D "qcom,sc8280xp-dsi-phy-5nm", + "qcom,sa8775p-dsi-phy-5nm"; + reg =3D <0 0x22096400 0 0x200>, + <0 0x22096600 0 0x280>, + <0 0x22096900 0 0x280>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + clocks =3D <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", "ref"; + + status =3D "disabled"; + }; + mdss1_dp1: displayport-controller@22098000 { compatible =3D "qcom,sc8280xp-dp"; reg =3D <0 0x22098000 0 0x200>, @@ -6434,10 +6822,10 @@ dispcc1: clock-controller@22100000 { <&mdss1_dp2_phy 1>, <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>, - <0>, - <0>, - <0>, - <0>; + <&mdss1_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss1_dsi1_phy DSI_PIXEL_PLL_CLK>; power-domains =3D <&rpmhpd SC8280XP_MMCX>; =20 #clock-cells =3D <1>; --=20 2.53.0