From nobody Thu Apr 9 15:47:25 2026 Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CB4A7262F; Sun, 8 Mar 2026 02:38:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772937514; cv=none; b=MhMIwk32Lpb0DoEhP4BhXtWQk4RW1L38j5/8l3t9Um2LZPo49BjtQTyOl27VWrkdlNaCPY23PGSwaFTdfNaabK6KvTpWLcmpw01kKTmrDHTRmmrlZZ2agCx8YkBK2bYHABO0iU2kPV4PbGvWiKsJSrs8fUj5WrPtiDK7ocPYGc8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772937514; c=relaxed/simple; bh=ALKbHQepcVq5V8k0MpNIbqkEH+0BGOCyo4yUnQ7Imzk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=YqxgMj/NYc66Z6MhW262P/WM+Tvx/SPNs8JLf32tW0FpegeZwPEyJ/I+h0J5+DWZ3aizPC8PStCnvnkvoyxWz/EGS4kFeheBo9L+3rNbUkM5jtCZVza4KFOja+88f94eEQr7PkY4OFwMdW8r5a9yI4S6KGvGQt/kLDnwHYTp3ew= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from fric.. (unknown [210.73.43.101]) by APP-03 (Coremail) with SMTP id rQCowABnht0M4axptjIICg--.61997S3; Sun, 08 Mar 2026 10:38:06 +0800 (CST) From: Jiakai Xu To: linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org Cc: Shuah Khan , Paolo Bonzini , Andrew Jones , Alexandre Ghiti , Albert Ou , Palmer Dabbelt , Paul Walmsley , Atish Patra , Anup Patel , Jiakai Xu , Jiakai Xu Subject: [PATCH v2 1/2] RISC-V: KVM: Fix array out-of-bounds in pmu_ctr_read() and pmu_fw_ctr_read_hi() Date: Sun, 8 Mar 2026 02:38:02 +0000 Message-Id: <20260308023803.4001232-2-xujiakai2025@iscas.ac.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260308023803.4001232-1-xujiakai2025@iscas.ac.cn> References: <20260308023803.4001232-1-xujiakai2025@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: rQCowABnht0M4axptjIICg--.61997S3 X-Coremail-Antispam: 1UD129KBjvJXoW7WFWfXF18ZFyrAFy5Jw4xWFg_yoW8try5pr sFkasaq3s5trs2qw1Yyw1Dur4jkw4kGan8GrWUWF18Ar4agry3JFyDu3sxJr43AFW2qa4x tw4F9a4xCFW5Xa7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQF14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjcxK6I8E87Iv6xkF7I0E14v26F4UJVW0owAa c4AC62xK8xCEY4vEwIxC4wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzV Aqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S 6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxw ACI402YVCY1x02628vn2kIc2xKxwCY1x0262kKe7AKxVWUtVW8ZwCF04k20xvY0x0EwIxG rwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4 vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IY x2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26c xKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAF wI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JU2sj8UUUUU= X-CM-SenderInfo: 50xmxthndljiysv6x2xfdvhtffof0/1tbiBwsACWmsPtixMwAAsk Content-Type: text/plain; charset="utf-8" When a guest invokes SBI_EXT_PMU_COUNTER_FW_READ or SBI_EXT_PMU_COUNTER_FW_READ_HI on a firmware counter that has not been configured via SBI_EXT_PMU_COUNTER_CFG_MATCH, the pmc->event_idx remains SBI_PMU_EVENT_IDX_INVALID (0xFFFFFFFF). get_event_code() extracts the lower 16 bits, yielding 0xFFFF (65535), which is then used to index into kvpmu->fw_event[]. Since fw_event is only RISCV_KVM_MAX_FW_CTRS (32) entries, this triggers an array-index-out-of-bounds: UBSAN: array-index-out-of-bounds in arch/riscv/kvm/vcpu_pmu.c:255:37 index 65535 is out of range for type 'kvm_fw_event [32]' Add a bounds check on fevent_code before accessing the fw_event array, returning -EINVAL for invalid event codes. Fixes: badc386869e2c ("RISC-V: KVM: Support firmware events") Fixes: 08fb07d6dcf71 ("RISC-V: KVM: Support 64 bit firmware counters on RV3= 2") Signed-off-by: Jiakai Xu Signed-off-by: Jiakai Xu --- V1 -> V2: - Merged the fixes for pmu_ctr_read() and pmu_fw_ctr_read_hi() into a single commit. - Removed the pr_warn, simply returning -EINVAL instead. --- arch/riscv/kvm/vcpu_pmu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c index e873430e596b..2ab67f5b99dc 100644 --- a/arch/riscv/kvm/vcpu_pmu.c +++ b/arch/riscv/kvm/vcpu_pmu.c @@ -227,6 +227,8 @@ static int pmu_fw_ctr_read_hi(struct kvm_vcpu *vcpu, un= signed long cidx, return -EINVAL; =20 fevent_code =3D get_event_code(pmc->event_idx); + if (fevent_code >=3D SBI_PMU_FW_MAX) + return -EINVAL; pmc->counter_val =3D kvpmu->fw_event[fevent_code].value; =20 *out_val =3D pmc->counter_val >> 32; @@ -252,6 +254,8 @@ static int pmu_ctr_read(struct kvm_vcpu *vcpu, unsigned= long cidx, =20 if (pmc->cinfo.type =3D=3D SBI_PMU_CTR_TYPE_FW) { fevent_code =3D get_event_code(pmc->event_idx); + if (fevent_code >=3D SBI_PMU_FW_MAX) + return -EINVAL; pmc->counter_val =3D kvpmu->fw_event[fevent_code].value; } else if (pmc->perf_event) { pmc->counter_val +=3D perf_event_read_value(pmc->perf_event, &enabled, &= running); --=20 2.34.1