From nobody Thu Apr 9 14:09:29 2026 Received: from mout-p-202.mailbox.org (mout-p-202.mailbox.org [80.241.56.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABAE12C0F97; Sun, 8 Mar 2026 05:18:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.241.56.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772947112; cv=none; b=DHmazbbPQf2Vpqsv+Y2rJjhC4SuD/HTxf/WRnNA/yYb/5sn3nQ4hB1k6aBV5nXtQKYmFj8hZyWkCgWfNfKtVMpHphy38UBsACe2HbNCEtTzT2Ga7vCMuJwa9iNn/yZ2+C3caObwGprKd37WfwPj61dC65JcsYHxWMHSaEUan6ng= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772947112; c=relaxed/simple; bh=6VCLjpSEVcMWlsqnU3sm41GHeCIIDj8fxsmOYwSNfLc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sV4EcH8N1jhO7LceRHXuCtigGzjspRIdCfh9rqQa/a8Dsq43Eomxn9NmRWM+hp+IA/sm9hx6LHFRuSohXO1hHu6ukh+6SCV48SO47wgqNHlBpuaw8vMmc95OclMm3O3akJ/mFnosTIO38+01TSq9vdA7OOpPdDoRxMpN5V+eFxQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org; spf=pass smtp.mailfrom=mailbox.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=W6AGXaD2; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=SfPvJb9O; arc=none smtp.client-ip=80.241.56.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mailbox.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="W6AGXaD2"; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="SfPvJb9O" Received: from smtp2.mailbox.org (smtp2.mailbox.org [10.196.197.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-202.mailbox.org (Postfix) with ESMTPS id 4fT7hg3FTXz9t0N; Sun, 8 Mar 2026 06:18:27 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1772947107; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xFoQRbzzGJ6GQLY9ekTrem/KHliTwSgfflqFnYv1J1I=; b=W6AGXaD2yCQxWQHhGQx8Lj7x3lvNGWCvnVIGE+n/s0fO58ctJNp8VsWEwHeJdeFq5DhnbY mefxHsAX7qTf323TVW/OFmRXA78G7NmRmKyMG8qSlMJfWa0/gNCsDPIkuJfaCeB4v/AAyl VGzEzp6sNQFLRmDCMi3GK+eiZevGgXiyI77paevkHup4aY2Pm0dgDHlyYkm5aXoMh4qaws cZO4q+FFfAlGXJOJbGMrKGc08IYlLh4iJKkn26vPzwVENzZu3F0nelRsz7EayJN8oLkHN4 LnEQdUxesNJV6taCTGQGqqYtCAb7Q206/joWsJhnmrdh65P7fSUmrMmrXOoLug== From: Shuwei Wu DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1772947105; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xFoQRbzzGJ6GQLY9ekTrem/KHliTwSgfflqFnYv1J1I=; b=SfPvJb9OoCcu+7pDQ/6PzK0nnTzfuE+b6AGVMJO5+f4XPpO6eY2Y5Cotmglb3M6l0qZ70g WzasThc2w4qN56wg8IhWRlcFCyNqkROMUScDIRuMNvc+H1tjVfcgN8ITQMojUK84dWhzJF GEz9Cyo2aSheb3NPz2ABjTkBpk1Zhhr7pBcevbeqMxh5vIEW/zTEYZRtUY+TjGn4I2L4qH 9aQAWvvr/bQqst97vgKM8nfOPYNEjutEAHWAUKkV74ymgsVDnE7Kkuonq5EeNiRvNFmuip SivYiEQUErdcdnrPPCOw6M9y6nZIs0sMIOypI1ImwJo3NTYXfWyAmidswJIBmA== Date: Sun, 08 Mar 2026 13:17:39 +0800 Subject: [PATCH 1/2] cpufreq: dt-platdev: Add SpacemiT K1 SoC to the allowlist Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260308-shadow-deps-v1-1-0ceb5c7c07eb@mailbox.org> References: <20260308-shadow-deps-v1-0-0ceb5c7c07eb@mailbox.org> In-Reply-To: <20260308-shadow-deps-v1-0-0ceb5c7c07eb@mailbox.org> To: "Rafael J. Wysocki" , Viresh Kumar , Yixun Lan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, devicetree@vger.kernel.org, Shuwei Wu X-Developer-Signature: v=1; a=ed25519-sha256; t=1772947080; l=808; i=shuwei.wu@mailbox.org; s=20251125; h=from:subject:message-id; bh=6VCLjpSEVcMWlsqnU3sm41GHeCIIDj8fxsmOYwSNfLc=; b=YNWJKGrDi++1MHi41bxD8v2brnggQZzBMTXXEScsWmdBco7Lx1xhqOA9txUyDPZ8PD9Kp8QBw /MS4ASbQAHmADzG0L8bQSr8hZx4hhPFhgDS3LqzFTO2MgsxZ9Uo4kau X-Developer-Key: i=shuwei.wu@mailbox.org; a=ed25519; pk=qZs6i2UZnXkmjUrwO5HJxcfpCvgSNrR4dcU5cjtfTSk= X-MBO-RS-ID: 03bc9bd0b2123aa0cdc X-MBO-RS-META: nabprw15aooh1m1w5pegnzxrmoiopiad The SpacemiT K1 SoC uses standard device tree based CPU frequency scaling. Add it to the allowlist to instantiate the cpufreq-dt driver. Signed-off-by: Shuwei Wu --- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq= -dt-platdev.c index a1d11ecd1ac8..d22198d33b7d 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -81,6 +81,7 @@ static const struct of_device_id allowlist[] __initconst = =3D { { .have_governor_per_policy =3D true, }, }, =20 + { .compatible =3D "spacemit,k1", }, { .compatible =3D "st-ericsson,u8500", }, { .compatible =3D "st-ericsson,u8540", }, { .compatible =3D "st-ericsson,u9500", }, --=20 2.52.0 From nobody Thu Apr 9 14:09:29 2026 Received: from mout-p-202.mailbox.org (mout-p-202.mailbox.org [80.241.56.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F4492D94AD; Sun, 8 Mar 2026 05:18:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.241.56.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772947125; cv=none; b=cGq2Rba1ObC13Rce23gioh8nG+jQinHW/jwfvscy8svf1hZl3xbGRKsSH7GunYCXphXmJJXZ7JMdUbtFs8jZsurZcxcBjm18bCudH8SPz6K5aKfxjxup5VW8vG1eSTNsBEnpotCulr7swHCPGxcBh9VMgNRV+to9+S1ZmZYakRU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772947125; c=relaxed/simple; bh=7uC3iROuTHcj106rWtHe9UGVXeEv27CxF42mwez2Gho=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QPkbIJM8fwoAY3GJGNg3khCPjYitTdg1glpJeg1mdE1NpKzepdoDpEBqZudHKB8lclzgUPf12bn2MWBmGbrSGrTlzWoQeMrxlMaXDtyvRdR0qPAkp5DDm4uUf+xT9bNxWKrJ8niqKP3wgiUcBiYEygi0Qzau9oyEKi6bDC9N8vA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org; spf=pass smtp.mailfrom=mailbox.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=Z5LYZkg1; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=M7N0iC7u; arc=none smtp.client-ip=80.241.56.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mailbox.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="Z5LYZkg1"; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="M7N0iC7u" Received: from smtp2.mailbox.org (smtp2.mailbox.org [10.196.197.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-202.mailbox.org (Postfix) with ESMTPS id 4fT7hw40bLz9t0N; Sun, 8 Mar 2026 06:18:40 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1772947120; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=U2zbR+yKhzxXYXiJrsbtpXWNDGggLUiz5aQfOKpnS0Q=; b=Z5LYZkg1QgVuziuumFcX38v7gNG0tTh/QEz/hY5Jp3SDd6p8cCyUN6jiWlVkAT2nqg7+js L9QxjlOxG9TsA4+HpIkgoN5RwwQu2oNy5vXdZmbgj95NVjiST2blFVl2qG4Tmgd5kF0NtP ltFQi6u/DtJFw8ROj2Qa9YomlGgewRHYvNLDSecoRDydDMmXUiqa9OfIIC9srsSJ0SHVxa 2iJ9UA9BMle90Q65jW6iNPsQ1ihfB9mg6EP5TZNCPhpPAK+Oseln7spaDAd/4S4U9DceOo wv9tT4osiygpakGNgUsxTgCMfE7am36ly7DrJSNPKHtxImeMvHGvCQBx80r/wQ== From: Shuwei Wu DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1772947118; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=U2zbR+yKhzxXYXiJrsbtpXWNDGggLUiz5aQfOKpnS0Q=; b=M7N0iC7ufQiQw9VBZ6hFetwL9gslP8wsaTe79Xd3B7iaT8KzmSXu9BllQLnrJw8dZ9VJE3 JDgr1KOw649xwYaw27E0iNF4Q2y9SZz8g2MRo66ePcbBooBLk66KazZXQhHL4J2prC03XQ VHaHP+T4HHa5f64TYIKcS3f/c/uhEjm/1SmnwQZk3Q32W9wrgZhiXnx2tccJ2cpygwi7wk VWNO0yo6ymBp/u8cgcMwgjoh/CZIcPiygiIK2METdY6VmNaWBM4EFBC8iwe9EzoUdbhV6X Y7rBpcEpBCaE9buz2eecEnLvmghXaYKdWWuQlAmic5hz4UIalQsvDL8ABHLt5g== Date: Sun, 08 Mar 2026 13:17:40 +0800 Subject: [PATCH 2/2] riscv: dts: spacemit: Add cpu scaling for K1 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260308-shadow-deps-v1-2-0ceb5c7c07eb@mailbox.org> References: <20260308-shadow-deps-v1-0-0ceb5c7c07eb@mailbox.org> In-Reply-To: <20260308-shadow-deps-v1-0-0ceb5c7c07eb@mailbox.org> To: "Rafael J. Wysocki" , Viresh Kumar , Yixun Lan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, devicetree@vger.kernel.org, Shuwei Wu X-Developer-Signature: v=1; a=ed25519-sha256; t=1772947080; l=7395; i=shuwei.wu@mailbox.org; s=20251125; h=from:subject:message-id; bh=7uC3iROuTHcj106rWtHe9UGVXeEv27CxF42mwez2Gho=; b=VmNFO8sczaz1iKKTUmT+MODs2QmiZZXmtxSebfW55jeRa+xC+PeTVgp1e8PTlHmuH29O3xpx+ 0jTQFr9F9+wD7/vkuBLqy8hHuiDkrGrkdYfJ9HiMGVYaq6BJDEL3h1I X-Developer-Key: i=shuwei.wu@mailbox.org; a=ed25519; pk=qZs6i2UZnXkmjUrwO5HJxcfpCvgSNrR4dcU5cjtfTSk= X-MBO-RS-META: x9osz9e998t94rcicehd4hwu4jy99owh X-MBO-RS-ID: 554dca1a88f477668d1 Add Operating Performance Points (OPP) tables and CPU clock properties for the two clusters in the SpacemiT K1 SoC. Also assign the CPU power supply (cpu-supply) for the Banana Pi BPI-F3 board to fully enable CPU DVFS. Signed-off-by: Shuwei Wu --- arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 34 +++++++++- arch/riscv/boot/dts/spacemit/k1.dtsi | 86 +++++++++++++++++++++= ++++ 2 files changed, 119 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/b= oot/dts/spacemit/k1-bananapi-f3.dts index 444c3b1e6f44..b87bf9d51cb1 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -86,6 +86,38 @@ &combo_phy { status =3D "okay"; }; =20 +&cpu_0 { + cpu-supply =3D <&buck1_3v45>; +}; + +&cpu_1 { + cpu-supply =3D <&buck1_3v45>; +}; + +&cpu_2 { + cpu-supply =3D <&buck1_3v45>; +}; + +&cpu_3 { + cpu-supply =3D <&buck1_3v45>; +}; + +&cpu_4 { + cpu-supply =3D <&buck1_3v45>; +}; + +&cpu_5 { + cpu-supply =3D <&buck1_3v45>; +}; + +&cpu_6 { + cpu-supply =3D <&buck1_3v45>; +}; + +&cpu_7 { + cpu-supply =3D <&buck1_3v45>; +}; + &emmc { bus-width =3D <8>; mmc-hs400-1_8v; @@ -201,7 +233,7 @@ pmic@41 { dldoin2-supply =3D <&buck5>; =20 regulators { - buck1 { + buck1_3v45: buck1 { regulator-min-microvolt =3D <500000>; regulator-max-microvolt =3D <3450000>; regulator-ramp-delay =3D <5000>; diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spa= cemit/k1.dtsi index 529ec68e9c23..5c7bb5d85fc0 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -54,6 +54,8 @@ cpu_0: cpu@0 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <0>; + clocks =3D <&syscon_apmu CLK_CPU_C0_CORE>; + operating-points-v2 =3D <&cluster0_opp_table>; riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", @@ -84,6 +86,8 @@ cpu_1: cpu@1 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <1>; + clocks =3D <&syscon_apmu CLK_CPU_C0_CORE>; + operating-points-v2 =3D <&cluster0_opp_table>; riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", @@ -114,6 +118,8 @@ cpu_2: cpu@2 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <2>; + clocks =3D <&syscon_apmu CLK_CPU_C0_CORE>; + operating-points-v2 =3D <&cluster0_opp_table>; riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", @@ -144,6 +150,8 @@ cpu_3: cpu@3 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <3>; + clocks =3D <&syscon_apmu CLK_CPU_C0_CORE>; + operating-points-v2 =3D <&cluster0_opp_table>; riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", @@ -174,6 +182,8 @@ cpu_4: cpu@4 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <4>; + clocks =3D <&syscon_apmu CLK_CPU_C1_CORE>; + operating-points-v2 =3D <&cluster1_opp_table>; riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", @@ -204,6 +214,8 @@ cpu_5: cpu@5 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <5>; + clocks =3D <&syscon_apmu CLK_CPU_C1_CORE>; + operating-points-v2 =3D <&cluster1_opp_table>; riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", @@ -234,6 +246,8 @@ cpu_6: cpu@6 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <6>; + clocks =3D <&syscon_apmu CLK_CPU_C1_CORE>; + operating-points-v2 =3D <&cluster1_opp_table>; riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", @@ -264,6 +278,8 @@ cpu_7: cpu@7 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <7>; + clocks =3D <&syscon_apmu CLK_CPU_C1_CORE>; + operating-points-v2 =3D <&cluster1_opp_table>; riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", @@ -339,6 +355,76 @@ osc_32k: clock-32k { }; }; =20 + cluster0_opp_table: opp-table-cluster0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-614400000 { + opp-hz =3D /bits/ 64 <614400000>; + opp-microvolt =3D <950000>; + clock-latency-ns =3D <200000>; + }; + + opp-819000000 { + opp-hz =3D /bits/ 64 <819000000>; + opp-microvolt =3D <950000>; + clock-latency-ns =3D <200000>; + }; + + opp-1000000000 { + opp-hz =3D /bits/ 64 <1000000000>; + opp-microvolt =3D <950000>; + clock-latency-ns =3D <200000>; + }; + + opp-1228800000 { + opp-hz =3D /bits/ 64 <1228800000>; + opp-microvolt =3D <950000>; + clock-latency-ns =3D <200000>; + }; + + opp-1600000000 { + opp-hz =3D /bits/ 64 <1600000000>; + opp-microvolt =3D <1050000>; + clock-latency-ns =3D <200000>; + }; + }; + + cluster1_opp_table: opp-table-cluster1 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-614400000 { + opp-hz =3D /bits/ 64 <614400000>; + opp-microvolt =3D <950000>; + clock-latency-ns =3D <200000>; + }; + + opp-819000000 { + opp-hz =3D /bits/ 64 <819000000>; + opp-microvolt =3D <950000>; + clock-latency-ns =3D <200000>; + }; + + opp-1000000000 { + opp-hz =3D /bits/ 64 <1000000000>; + opp-microvolt =3D <950000>; + clock-latency-ns =3D <200000>; + }; + + opp-1228800000 { + opp-hz =3D /bits/ 64 <1228800000>; + opp-microvolt =3D <950000>; + clock-latency-ns =3D <200000>; + }; + + opp-1600000000 { + opp-hz =3D /bits/ 64 <1600000000>; + opp-microvolt =3D <1050000>; + clock-latency-ns =3D <200000>; + }; + }; + soc { compatible =3D "simple-bus"; interrupt-parent =3D <&plic>; --=20 2.52.0