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charset="utf-8" From: Ciprian Marian Costea Add device tree support for the NXP S32N79 automotive SoC [1]. The S32N79 features eight Arm Cortex-A78AE cores organized in four dual-core clusters, with a three-level cache hierarchy (L1/L2 per core, L3 per dual-core cluster) and 32GB of DRAM memory. It includes an SMMUv3 for IOMMU functionality. On S32N79 SoC, peripherals are organized into subsystems, such as: - CIS (Coherent Interconnect Subsystem) - COSS (Connectivity Subsystem) - FSS (Foundation Subsystem) This initial support includes basic peripherals: - GICv3, SMMUv3 from CIS Subsystem - PL011 UARTs and IRQ steering controller from COSS Subsystem - uSDHC from FSS Subsystem Clock and Pin multiplexing settings for the chip are managed over SCMI. [1] https://www.nxp.com/products/processors-and-microcontrollers/s32-automo= tive-platform/s32n-vehicle-super-integration-processors:S32N Co-developed-by: Larisa Grigore Signed-off-by: Larisa Grigore Co-developed-by: Andra-Teodora Ilie Signed-off-by: Andra-Teodora Ilie Co-developed-by: Andrei Cherechesu Signed-off-by: Andrei Cherechesu Signed-off-by: Ciprian Marian Costea --- arch/arm64/boot/dts/freescale/s32n79.dtsi | 362 ++++++++++++++++++++++ 1 file changed, 362 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/s32n79.dtsi diff --git a/arch/arm64/boot/dts/freescale/s32n79.dtsi b/arch/arm64/boot/dt= s/freescale/s32n79.dtsi new file mode 100644 index 000000000000..94ab58783fdc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32n79.dtsi @@ -0,0 +1,362 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * NXP S32N79 SoC + * + * Copyright 2026 NXP + */ + +#include + +/ { + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cis-bus { + compatible =3D "simple-bus"; + ranges =3D <0x4f200000 0x0 0x4f200000 0xc00000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + gic: interrupt-controller@4f200000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x4f200000 0x10000>, /* GIC Dist */ + <0x4f260000 0x100000>; + #interrupt-cells =3D <3>; + interrupt-controller; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <1>; + /* GICR (RD_base + SGI_base) */ + ranges; + + its: msi-controller@4f240000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x4f240000 0x20000>; + #msi-cells =3D <1>; + msi-controller; + }; + }; + + smmu: iommu@4fc00000 { + compatible =3D "arm,smmu-v3"; + reg =3D <0x4fc00000 0x200000>; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + ; + interrupt-names =3D "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells =3D <1>; + dma-coherent; + status =3D "disabled"; + }; + }; + + coss-bus { + compatible =3D "simple-bus"; + ranges =3D <0x4a000000 0x0 0x4a000000 0xff0000>, + <0x4e000000 0x0 0x4e000000 0x1000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + uart0: serial@4a030000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x4a030000 0x1000>; + interrupt-parent =3D <&irqsteer_coss>; + interrupts =3D <264>; + clocks =3D <&clks 0x9a>, <&clks 0x9a>; + clock-names =3D "uartclk", "apb_pclk"; + status =3D "disabled"; + }; + + uart5: serial@4a060000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x4a060000 0x1000>; + interrupt-parent =3D <&irqsteer_coss>; + interrupts =3D <269>; + clocks =3D <&clks 0x9a>, <&clks 0x9a>; + clock-names =3D "uartclk", "apb_pclk"; + status =3D "disabled"; + }; + + uart6: serial@4aa30000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x4aa30000 0x1000>; + interrupt-parent =3D <&irqsteer_coss>; + interrupts =3D <270>; + clocks =3D <&clks 0x9a>, <&clks 0x9a>; + clock-names =3D "uartclk", "apb_pclk"; + status =3D "disabled"; + }; + + uart7: serial@4aa40000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x4aa40000 0x1000>; + interrupt-parent =3D <&irqsteer_coss>; + interrupts =3D <271>; + clocks =3D <&clks 0x9a>, <&clks 0x9a>; + clock-names =3D "uartclk", "apb_pclk"; + status =3D "disabled"; + }; + + irqsteer_coss: interrupt-controller@4ed00000 { + compatible =3D "nxp,s32n79-irqsteer"; + reg =3D <0x4ed00000 0x10000>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupt-parent =3D <&gic>; + interrupts =3D , + , + , + , + , + , + , + ; + clocks =3D <&clks 0x9a>; + clock-names =3D "ipg"; + fsl,channel =3D <0>; + fsl,num-irqs =3D <512>; + status =3D "disabled"; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu2>; + }; + + core1 { + cpu =3D <&cpu3>; + }; + }; + + cluster2 { + core0 { + cpu =3D <&cpu4>; + }; + + core1 { + cpu =3D <&cpu5>; + }; + }; + + cluster3 { + core0 { + cpu =3D <&cpu6>; + }; + + core1 { + cpu =3D <&cpu7>; + }; + }; + }; + + l2_0: l2-cache0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + cache-size =3D <524288>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + + l2_1: l2-cache1 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + cache-size =3D <524288>; + cache-unified; + next-level-cache =3D <&l3_1>; + }; + + l2_2: l2-cache2 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + cache-size =3D <524288>; + cache-unified; + next-level-cache =3D <&l3_2>; + }; + + l2_3: l2-cache3 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-line-size =3D <64>; + cache-sets =3D <512>; + cache-size =3D <524288>; + cache-unified; + next-level-cache =3D <&l3_3>; + }; + + l3_0: l3-cache0 { + compatible =3D "cache"; + cache-level =3D <3>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + cache-size =3D <1048576>; + cache-unified; + }; + + l3_1: l3-cache1 { + compatible =3D "cache"; + cache-level =3D <3>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + cache-size =3D <1048576>; + cache-unified; + }; + + l3_2: l3-cache2 { + compatible =3D "cache"; + cache-level =3D <3>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + cache-size =3D <1048576>; + cache-unified; + }; + + l3_3: l3-cache3 { + compatible =3D "cache"; + cache-level =3D <3>; + cache-line-size =3D <64>; + cache-sets =3D <1024>; + cache-size =3D <1048576>; + cache-unified; + }; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a78ae"; + reg =3D <0x0>; + device_type =3D "cpu"; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + }; + + cpu1: cpu@100 { + compatible =3D "arm,cortex-a78ae"; + reg =3D <0x100>; + device_type =3D "cpu"; + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + }; + + cpu2: cpu@10000 { + compatible =3D "arm,cortex-a78ae"; + reg =3D <0x10000>; + device_type =3D "cpu"; + enable-method =3D "psci"; + next-level-cache =3D <&l2_1>; + }; + + cpu3: cpu@10100 { + compatible =3D "arm,cortex-a78ae"; + reg =3D <0x10100>; + device_type =3D "cpu"; + enable-method =3D "psci"; + next-level-cache =3D <&l2_1>; + }; + + cpu4: cpu@20000 { + compatible =3D "arm,cortex-a78ae"; + reg =3D <0x20000>; + device_type =3D "cpu"; + enable-method =3D "psci"; + next-level-cache =3D <&l2_2>; + }; + + cpu5: cpu@20100 { + compatible =3D "arm,cortex-a78ae"; + reg =3D <0x20100>; + device_type =3D "cpu"; + enable-method =3D "psci"; + next-level-cache =3D <&l2_2>; + }; + + cpu6: cpu@30000 { + compatible =3D "arm,cortex-a78ae"; + reg =3D <0x30000>; + device_type =3D "cpu"; + enable-method =3D "psci"; + next-level-cache =3D <&l2_3>; + }; + + cpu7: cpu@30100 { + compatible =3D "arm,cortex-a78ae"; + reg =3D <0x30100>; + device_type =3D "cpu"; + enable-method =3D "psci"; + next-level-cache =3D <&l2_3>; + }; + }; + + firmware { + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + scmi: scmi { + compatible =3D "arm,scmi-smc"; + #address-cells =3D <1>; + #size-cells =3D <0>; + shmem =3D <&scmi_shbuf>; + arm,smc-id =3D <0xc20000fe>; + status =3D "okay"; + + clks: protocol@14 { + reg =3D <0x14>; + #clock-cells =3D <1>; + }; + }; + }; + + fss-bus { + compatible =3D "simple-bus"; + ranges =3D <0x5b490000 0x0 0x5b490000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + usdhc0: mmc@5b490000 { + compatible =3D "nxp,s32n79-usdhc"; + reg =3D <0x5b490000 0x1000>; + interrupts =3D ; + clocks =3D <&clks 0x58>, <&clks 0x50>, <&clks 0x5f>; + clock-names =3D "ipg", "ahb", "per"; + bus-width =3D <8>; + status =3D "disabled"; + }; + }; + + pmu: pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D ; + }; + + timer: timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; +}; --=20 2.43.0