From nobody Thu Apr 9 17:15:45 2026 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CC6030EF9A for ; Fri, 6 Mar 2026 13:42:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772804556; cv=none; b=BiPau0veQ+vE1ddTWwp5sq2RIkwiwCMC5svHo1MbNS/lfsoV3rhqwx9Unqtr3k5d3cbEHIAorvaEM07GA6RJdlS5RjTZh7AcfZBlZpglcAR9/rYCavOjDXbYrR/Zxg2S/ZlPOhu8RuECucMHcQRrCeieSI/JYKa42exKtKTO5ps= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772804556; c=relaxed/simple; bh=oDDmA+qtseMoqwvqvrsoGzJksVvbHRORAHe+YeEPpbk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iDrXav0HCeKHRTkgOA2+2yc14H23r0zxixF4I1OC3NJ2kvd0mpGsrPijL4y7oZ7tAj7EisPCe4omCdapvBKjZ5d4krLjbyeQbs3lfHgeL//CLhvl47plgocVwanK5XPtMLef4BvlDR1NG+zoou1b1EnEZic3ivFSYn3lBO16E64= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=YRp7ZHT+; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="YRp7ZHT+" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-4806cc07ce7so106397095e9.1 for ; Fri, 06 Mar 2026 05:42:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772804553; x=1773409353; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w7HfjRvaTulj2GfsP2nDOzeVXSEKKzPOa36MxET5CCs=; b=YRp7ZHT+ekkk+WHpMEKikB2NB8guV38oViVAjZ4xZd9kSCUPMgRxi1APcgzDcf2YbU m45NUs0A9FH/oJ6OOw8n+AwGTPYEWCiuqfwHJZdHrYkVH4E73hZT2BGvwM3f8FaNCqlA WMgpTVz7BwtWheaeIPE09+MGg3F1Jy4ncihqVQFCea0zNc7IuyCv/u769DauWG1eEVyx omRSeq9JPfzDvkuuWDyIST2P2hdjRcOzBB3TK6/272Ost5cJ6O9mpYxwk1mcWWoD5f4Q c5iGgiI2OC4DoA+mT6Urta/F/+PjvNmgKv5BnK/fsh+cqPAcefpwlSaQDrqJUmyPUjcV 191Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772804553; x=1773409353; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=w7HfjRvaTulj2GfsP2nDOzeVXSEKKzPOa36MxET5CCs=; b=qQiO6UPOISsTZoc0oWfSK4Vtpl2gZoq1eRVDPxjpHkO8IEGPWvW96qmlRdnz+rQfp8 fr2FnXM/xypjTeKKsnEfe7UGbucC4mqcK8pcl0yhkTUYOcbty+XEL0EJSCMtjz6LMcbe IqmUqRDc3ffZ++ZXZHvFsjqhbUWQkbKmpzm+wHQtXTjk2f48P2PE3BjoW0ZFv9uJl7YL 10w8B/WQu+JhBax3qXkYbAC7rbchLj+DfEqckg5KsXh5yPkKetHjx6Z7iQqItEKQkUEM j3ytLHB+sjXqeeZ+zD8fylNav9cE7ZTa25iqWJykPBUIZ0FZ+ojNr/27bUYvS8A5Ick0 mWXg== X-Forwarded-Encrypted: i=1; AJvYcCWJ6qWXiQHSsnXczujV8s5WPZOITw+/W1asjDlul/0zDgdY6/iEaoZPLFuYAr+hjaHSZLqTs7qYlMetw0c=@vger.kernel.org X-Gm-Message-State: AOJu0YxfJkp8rIp4jlxsWqr4lBGwCAXfjB2zdQIS8SVhmLRxcA3n4xJG jLNaosUzd2TYtVcSTUfMTjKyEAB2vRebWA3e9T9PpMUBV1CQkW+mMHPP X-Gm-Gg: ATEYQzyrnFg7yhv3i5Egz/Z1WL1MZjXT/4xdwWKW1+TygCh0Va8e3V4+jUvg3eoYEhu m2+uk5hFltPf0WWJuZSBSYrhx+ABXuoD2hoHZgInLDYfrxjOjUZEZBOQ/qs7Ng88bhr783SGhkS XQmvcU5A+DpyN64g+ccaMOAP3uIUWyZ9QG7dJQcP2e9UZwYbHA4fLfC579+5Ya4l0xkKA0kH4jJ xICSXFwgIz+ySiThFSd0vCreC19CllFlAc85G7u/r27ZJGJsR0G/p/p6TKpbACiT6fI/uAqlVAd e/Y+QbImJWzzKWXL0bdTy2/6Xck8UdWSe61J8c6XHN7GE234/lzAT83h1sEQfLbkyowPKrBsujO ZqmWXHSN0Td/klccOHBk9VeCar+PNi+tlZFsdUJKA2Z0Kq3XzfsHx54crRpL8CklZiNnrR9//bk 2F8p+dJipnZ4cVR2yE+gQBC79sXzifIoR1Zz7miAqf2DaA2c8= X-Received: by 2002:a05:600c:19cb:b0:480:6c75:ddce with SMTP id 5b1f17b1804b1-485269791a9mr31478995e9.33.1772804552665; Fri, 06 Mar 2026 05:42:32 -0800 (PST) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:d0f3:534:36a3:523a]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439dadb85b8sm4223790f8f.17.2026.03.06.05.42.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 05:42:31 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 1/3] clk: renesas: rzg2l-cpg: Add support for critical resets Date: Fri, 6 Mar 2026 13:42:23 +0000 Message-ID: <20260306134228.871815-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260306134228.871815-1-biju.das.jz@bp.renesas.com> References: <20260306134228.871815-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Some reset lines must remain deasserted at all times after boot, as asserting them would disable critical system functionality with no owning driver to restore them. This mirrors the existing crit_mod_clks mechanism which protects critical module clocks from being disabled. On RZ/G2L family SoCs, DMA reset to be deasseted for routing some peripheral interrupts to CPU. Add crit_resets and num_crit_resets fields to struct rzg2l_cpg_info to allow SoC-specific data tables to declare reset IDs that must never be asserted. Introduce rzg2l_cpg_deassert_crit_resets() to iterate over all critical resets and deassert them. Call it both at probe time and during resume to ensure critical peripherals are held out of reset after power-on and suspend/resume cycles. Signed-off-by: Biju Das --- drivers/clk/renesas/rzg2l-cpg.c | 33 +++++++++++++++++++++++++++++++++ drivers/clk/renesas/rzg2l-cpg.h | 7 +++++++ 2 files changed, 40 insertions(+) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index c0584bab58a3..8165c163143a 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1765,6 +1765,15 @@ static int __rzg2l_cpg_assert(struct reset_controlle= r_dev *rcdev, dev_dbg(rcdev->dev, "%s id:%ld offset:0x%x\n", assert ? "assert" : "deassert", id, CLK_RST_R(reg)); =20 + if (assert) { + unsigned int i; + + for (i =3D 0; i < priv->info->num_crit_resets; i++) { + if (id =3D=3D priv->info->crit_resets[i]) + return 0; + } + } + if (!assert) value |=3D mask; writel(value, priv->base + CLK_RST_R(reg)); @@ -1802,6 +1811,21 @@ static int rzg2l_cpg_deassert(struct reset_controlle= r_dev *rcdev, return __rzg2l_cpg_assert(rcdev, id, false); } =20 +static int rzg2l_cpg_deassert_crit_resets(struct reset_controller_dev *rcd= ev, + const struct rzg2l_cpg_info *info) +{ + unsigned int i; + int ret; + + for (i =3D 0; i < info->num_crit_resets; i++) { + ret =3D rzg2l_cpg_deassert(rcdev, info->crit_resets[i]); + if (ret) + return ret; + } + + return 0; +} + static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev, unsigned long id) { @@ -2051,6 +2075,10 @@ static int __init rzg2l_cpg_probe(struct platform_de= vice *pdev) if (error) return error; =20 + error =3D rzg2l_cpg_deassert_crit_resets(&priv->rcdev, info); + if (error) + return error; + debugfs_create_file("mstop", 0444, NULL, priv, &rzg2l_mod_clock_mstop_fop= s); return 0; } @@ -2058,6 +2086,11 @@ static int __init rzg2l_cpg_probe(struct platform_de= vice *pdev) static int rzg2l_cpg_resume(struct device *dev) { struct rzg2l_cpg_priv *priv =3D dev_get_drvdata(dev); + int ret; + + ret =3D rzg2l_cpg_deassert_crit_resets(&priv->rcdev, priv->info); + if (ret) + return ret; =20 rzg2l_mod_clock_init_mstop(priv); =20 diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cp= g.h index 55e815be16c8..af0a003d93f7 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -276,6 +276,9 @@ struct rzg2l_reset { * @crit_mod_clks: Array with Module Clock IDs of critical clocks that * should not be disabled without a knowledgeable driver * @num_crit_mod_clks: Number of entries in crit_mod_clks[] + * @crit_resets: Array with Reset IDs of critical resets that should not be + * asserted without a knowledgeable driver + * @num_crit_resets: Number of entries in crit_resets[] * @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers */ struct rzg2l_cpg_info { @@ -302,6 +305,10 @@ struct rzg2l_cpg_info { const unsigned int *crit_mod_clks; unsigned int num_crit_mod_clks; =20 + /* Critical Resets that should not be asserted */ + const unsigned int *crit_resets; + unsigned int num_crit_resets; + bool has_clk_mon_regs; }; =20 --=20 2.43.0 From nobody Thu Apr 9 17:15:45 2026 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D58831195B for ; Fri, 6 Mar 2026 13:42:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772804557; cv=none; b=VpAsUxzIfYM5qjavuzZh1Ba4AvAnh/7d0FwFlYPyzJ1sadS/xxHJ9kYp70ipg3tBN1MjTEySsfSXgMEiz84v8hUY9+4d2EMTqp93Yf1jNIjLrcOEZJMoztC7b5aSx3i8E55J0sx7QRCeeHrQAnyL4iGZ/I5FZSYjiXm/gFrhE7Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772804557; c=relaxed/simple; bh=nzB4vn1IjWBHrbgZS/e94Dund4pW6w6VdfFOAfcUVCA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ia3jKmNXgHowEEg0kDnkfal4T9NCTR19OScWFTxiScitXC29wxUHAjI2EjgF/WVdcwkqZrUYgD6YQ0reyhiGSDzsCbqlYeBdaz1rDNY2u/F9dws5deyecxVrYomDlLOf7QjnCeTsFSnEssrXK+3jy9i1M44JOKzXZ9ec7k6bsrE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=YC9Oq7/h; arc=none smtp.client-ip=209.85.221.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="YC9Oq7/h" Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-439b78b638eso6064409f8f.2 for ; Fri, 06 Mar 2026 05:42:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772804554; x=1773409354; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=o6IrVxXy7CXsl37mE9WFjkK5uiaupuO7eK2CML6ou7w=; b=YC9Oq7/hSZsqpVQhhEJcMFvm2hsDb4UFGUcs1Sc5g3V+aK4VkC4bVkV2FISeLXr2Q+ PN73/ROnpud4snalhBychcaQkjQrX4Ew9jlEDHY/OMH7puONU9YpDqslWSCe6hmbK8fh 6uNkdWO2Kak/lMqA/cMwTzdPuJSmwrzJHdb9AkgnfAbVZ4RKA5vk30HQQN0v8ViGnwfs 5rNl4d38UtlKqOun5HqF0Hjp+Jr5WDsmAH7OjCbIzOuzru16dnZcWakUS65bkmwe/qDd VFAe6Zb7mb75WItvqhvj3Q9bGQFxiQemG3XjGCRp5y1sfO222xXNZIsGwzmz9+278Irz 7Kyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772804554; x=1773409354; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=o6IrVxXy7CXsl37mE9WFjkK5uiaupuO7eK2CML6ou7w=; b=h/LgFlq6BiDIBlDbzxa/UWz5USIUj6fjd0HWqi0Mx3/NWq05+jYYlouwj6Qbe1AN4L 00c5tcZ6fBZGFpqSaLL65LiPle+F0yS9vYg2EWH6vXU3D6ixZ6hAaqohMUEOkzRGytDK IPWNSQGVaegn5XfM/NDVHrVV4+sSpDGgc7EmZ513/ykkAw3GnDWFI6ccLYD0Mp0iopGx ixjkgP3QOoj9hbYt6daTnkCYyjW8xjqsWTha/6xVxVJXbySJKrJP07fz9rLW7sAHXCnc rsXV3+JObDSJ37k2QDfR4a6L9qbAxvOz5D3XK+euOg7I3KBDiuZr2ojMtcvKuJ6hqAtl Dg+w== X-Forwarded-Encrypted: i=1; AJvYcCWHPm9v18ztuAMNKbxtKj99ZGSDGA30Yy+zUXT2IG8pSXcwXIQDyVsgQIyqxXAskT9Ln7AZNFE0XvaEg4g=@vger.kernel.org X-Gm-Message-State: AOJu0YxdhVKJGwDjecyDZObZ80hgSeWMY9C/Ih2JZhaESYeJnj8DOTpm tI3Q853PMNg6dkJc2tmocehnmyN1l8KyfWfd/biBrHs56yAgCjO8ceSL X-Gm-Gg: ATEYQzxoM49hT3787kT1bUe7XA7kEapSiBdLoaweR/Q7UZUr8apf9IhmaJmFC4jwrfs /WWbO7aaWkCSNQiUvEDyhr6O3f0ab09lXTtb4le/pNA637J5RWTYMoXSMvb68zqxYP2zBP5+/uB vNM5iIo72IdGCB3tpsM8WQuy29n+QXVvwDLRZjQg2WmUFcYyHzjKseUR8m3xAXAjLZwLcxjDMNH HMp7ugEjW9Ha2m0rKnd1b/X/C46lO3tHjMG6sfXoTv0G52ASqO6z04am3hGZA917lQxwkOsbtVJ aWwt+QiD9uMLZtTjQIvSOYrk2Z1AbasaIN3YxmeWTNDecrp2iZzZeERG8ReC2ZBcuIuQ40r/skX Cytx8Jry9wwsmJ66qSvh+ZRUJ41BtlohVn+b0rHas0vHjxYwdVu8dfhUAQXxjSL9OU3fpLiPWIx mPMe/WouhI4uVSjJAzwGwxC2ps8NNr2FnllvsR3Z76hY99uEs= X-Received: by 2002:a05:6000:430d:b0:439:b82d:3b97 with SMTP id ffacd0b85a97d-439da662378mr3547221f8f.17.1772804553685; Fri, 06 Mar 2026 05:42:33 -0800 (PST) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:d0f3:534:36a3:523a]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439dadb85b8sm4223790f8f.17.2026.03.06.05.42.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 05:42:33 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 2/3] clk: renesas: r9a07g04{3,4}/r9a08g045-cpg: Add critical reset entries Date: Fri, 6 Mar 2026 13:42:24 +0000 Message-ID: <20260306134228.871815-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260306134228.871815-1-biju.das.jz@bp.renesas.com> References: <20260306134228.871815-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/G2L SoC family requires DMA resets to be deasserted for routing some peripheral interrupts to the CPU. Asserting these resets after boot would silently break interrupt delivery with no driver to restore them. Mark the DMA resets as critical by adding them to the crit_resets table in the SoC-specific rzg2l_cpg_info for r9a07g043, r9a07g044, and r9a08g045, preventing __rzg2l_cpg_assert() from driving them active and ensuring they are deasserted on probe and resume. Signed-off-by: Biju Das --- drivers/clk/renesas/r9a07g043-cpg.c | 8 ++++++++ drivers/clk/renesas/r9a07g044-cpg.c | 13 +++++++++++++ drivers/clk/renesas/r9a08g045-cpg.c | 9 +++++++++ 3 files changed, 30 insertions(+) diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a0= 7g043-cpg.c index 33e9a1223c72..01d741ed8dc5 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -379,6 +379,11 @@ static const unsigned int r9a07g043_crit_mod_clks[] __= initconst =3D { MOD_CLK_BASE + R9A07G043_DMAC_ACLK, }; =20 +static const unsigned int r9a07g043_critical_resets[] =3D { + R9A07G043_DMAC_ARESETN, + R9A07G043_DMAC_RST_ASYNC, +}; + #ifdef CONFIG_ARM64 static const unsigned int r9a07g043_no_pm_mod_clks[] =3D { MOD_CLK_BASE + R9A07G043_CRU_SYSCLK, @@ -420,5 +425,8 @@ const struct rzg2l_cpg_info r9a07g043_cpg_info =3D { .num_resets =3D R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */ #endif =20 + /* Critical Resets */ + .crit_resets =3D r9a07g043_critical_resets, + .num_crit_resets =3D ARRAY_SIZE(r9a07g043_critical_resets), .has_clk_mon_regs =3D true, }; diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a0= 7g044-cpg.c index 0dd264877b9a..7f1405cab9c3 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -489,6 +489,11 @@ static const unsigned int r9a07g044_crit_mod_clks[] __= initconst =3D { MOD_CLK_BASE + R9A07G044_DMAC_ACLK, }; =20 +static const unsigned int r9a07g044_critical_resets[] =3D { + R9A07G044_DMAC_ARESETN, + R9A07G044_DMAC_RST_ASYNC, +}; + static const unsigned int r9a07g044_no_pm_mod_clks[] =3D { MOD_CLK_BASE + R9A07G044_CRU_SYSCLK, MOD_CLK_BASE + R9A07G044_CRU_VCLK, @@ -519,6 +524,10 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info =3D { .resets =3D r9a07g044_resets, .num_resets =3D R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */ =20 + /* Critical Resets */ + .crit_resets =3D r9a07g044_critical_resets, + .num_crit_resets =3D ARRAY_SIZE(r9a07g044_critical_resets), + .has_clk_mon_regs =3D true, }; #endif @@ -548,6 +557,10 @@ const struct rzg2l_cpg_info r9a07g054_cpg_info =3D { .resets =3D r9a07g044_resets, .num_resets =3D R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */ =20 + /* Critical Resets */ + .crit_resets =3D r9a07g044_critical_resets, + .num_crit_resets =3D ARRAY_SIZE(r9a07g044_critical_resets), + .has_clk_mon_regs =3D true, }; #endif diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a0= 8g045-cpg.c index 79e7b19c7882..87ee43f9fe18 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -361,6 +361,11 @@ static const unsigned int r9a08g045_crit_mod_clks[] __= initconst =3D { MOD_CLK_BASE + R9A08G045_VBAT_BCLK, }; =20 +static const unsigned int r9a08g045_critical_resets[] =3D { + R9A08G045_DMAC_ARESETN, + R9A08G045_DMAC_RST_ASYNC, +}; + static const unsigned int r9a08g045_no_pm_mod_clks[] =3D { MOD_CLK_BASE + R9A08G045_PCI_CLKL1PM, }; @@ -389,5 +394,9 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info =3D { .resets =3D r9a08g045_resets, .num_resets =3D R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */ =20 + /* Critical Resets */ + .crit_resets =3D r9a08g045_critical_resets, + .num_crit_resets =3D ARRAY_SIZE(r9a08g045_critical_resets), + .has_clk_mon_regs =3D true, }; --=20 2.43.0 From nobody Thu Apr 9 17:15:45 2026 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EF93313E05 for ; Fri, 6 Mar 2026 13:42:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772804558; cv=none; b=EcU6BdP+K/K5y4TiUOWCX5aI1tSezlfNRxooS944wH5daX5L3ZBmEZkkq1oV0ipd9ZV8z78IjLOVM/gTfOEMxBgTuhQ/BGuCEFBZiHE41G3OhFuy5WayUEsee8QQjrasC87EsmoY1hd51hS0ZkgXv8zAwSCy0a/lhpFNN1WOxoc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772804558; c=relaxed/simple; bh=S9/Fzkiyb07FiSnwrS8MQmvi6Fitnuo1uoT04N7PIvE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sUCaM3liFMJIO/tGDtkxso1rzjy0mAJnU89mxp33TjVEUROMuB6kSclhO89wNHf89fs8eaiASBJcH2cwQCNTMpdS8aMJ00r+fgFNZwNssqCkzddKXvKKTlr3e+wvQQYsMM1Do3YIhL+OpGFhnKQnwjUqDHeyKDjAyKP1Vnou9do= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=CkI9fPu+; arc=none smtp.client-ip=209.85.221.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="CkI9fPu+" Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-439aa2f8ebaso4014502f8f.2 for ; Fri, 06 Mar 2026 05:42:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772804555; x=1773409355; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=o0Ng/uajvfzozXdQpYK5vG2wa/u2Xjabl4u/B9UNDME=; b=CkI9fPu+4f/I4luh/7QtYvHZV6uOXYAphvjNk8iEaWpTQ1lFjD0nEHbztDCihwdWx+ Ee2j9SehyGjRh/zQ85uvtnuFohrI/k7JbOymNxt0fxPrLOobx8aBWDuJl6lFS3740LQd HCpLz+qauSHPZOnxvJnx2BCcdk+jSKyCI709i/9o+jnz0w1EFvn9MboUMViWVMD8evDG 0vxb+9Imt3LqARayhWBzn5tGXX+oHdpXJ97cH9U2tvEzyu+MqFRw1ZLQbCyy8pS1QDR4 jYzdIHxXxqy+fz+y/mVPf0jHtd8xw70Tn5dr2X0VAnJDviqpWjjCOQquC6tVIJbOxAeP Hd0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772804555; x=1773409355; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=o0Ng/uajvfzozXdQpYK5vG2wa/u2Xjabl4u/B9UNDME=; b=oVEBe8VoXl1BCs9ukeK61OSqLSBztoMemaLOMyyVmTY7Hk2r259KxYSfdiKE6v2oir dmaNO7BUEtGKlhGiDDbg2BiQgYPCuIONCch8/2FA42hTQmAHqa/fVVc3Zge9oXpjH1hV qIIegSv1h09aXhn9okkU1lmj0SC4t0DdsrxoADMcjs/0f+08hj4i5RYfACle89ZH+XME cdkA4d5y7w2CX0iL7OKjcANKX9eAfukd/He/GQ6MT9QZfZ2Cg8YlvnSv5P5c5vaJ86Jb CDS/bjSs7gaF/3YaJh9XNLY2cDl7CFvt2NATh2EJO+YFi+7oMW6LSEBuNWzZyb77YwqG 7B9g== X-Forwarded-Encrypted: i=1; AJvYcCVZ70uquHVpm6OCWgyv09Y1pTQ/ZWtMpB9s5ezjGL8+nnHK2fZADlT30fgY3G/vGuR/3NbiZhIHh9tJLS4=@vger.kernel.org X-Gm-Message-State: AOJu0Yx3vh+Rs15OthbILNAjIqhip8sd0jHs71dDXh5HyrGVWUpAzMaL YJdzmGGq7jdJIiPo3iSnXIxcXJVhaUJ5VpA3aHIvyLsCbP24GtUjeT+j X-Gm-Gg: ATEYQzwatUn0fNufTSXd2em4Pf5/BADAhxTMuPnE2BMZH1AVqWYYQ3MbzYF2GgGJs5M 3t/Pgm3An2mI3ILdurHFsRWCvvRR0D1shD8pnsEC+nTHIqFMM1vFOgpVqojY9I7ZU0l3q1bWaOY JChVRC2GgNEdwTu2d7v3ppTjSb+I4nM5AyHAUgZNhSUZ1KIY3HpaZBk7DrmH1YlyLC2uBYCTd08 alwHK7NZ4feeByKAmONPMOmWaUy4uKGSb810JKrmkGtohZuKU4yMrq6Xfy2qUDtZYNQYshpQyf+ zfUk4eY/9uJtLry+7SYs7WAilxaK8jBbBRvUjq3IPICkH5Gh8dotC5ZgYYjp0aNkJJ/Nhg059OV j+Ls0BADYMyn5mcqX232IS5coX3MkEvLV0NIXaL6YG65pQzqqqufFOQgoQsT/Kax5G6RC9tyIhu M1zXDDXwYBw2vGzrehso4LeUVmoHlkUAB+vwcJFe1IG+a74fs= X-Received: by 2002:a5d:6384:0:b0:439:de1d:74ae with SMTP id ffacd0b85a97d-439de1d7642mr933964f8f.22.1772804554816; Fri, 06 Mar 2026 05:42:34 -0800 (PST) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:d0f3:534:36a3:523a]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439dadb85b8sm4223790f8f.17.2026.03.06.05.42.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 05:42:34 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 3/3] clk: renesas: rzg2l-cpg: Re-enable critical module clocks during resume Date: Fri, 6 Mar 2026 13:42:25 +0000 Message-ID: <20260306134228.871815-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260306134228.871815-1-biju.das.jz@bp.renesas.com> References: <20260306134228.871815-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das After a suspend/resume cycle, critical module clocks may be left disabled as the hardware state is not automatically restored. Unlike regular clocks which are re-enabled by their respective drivers, critical clocks (CLK_IS_CRITICAL) have no owning driver to restore them, so the CPG driver must take responsibility for re-enabling them on resume. Introduce struct rzg2l_crit_clk_hw to track critical module clock hardware entries in a singly-linked list anchored at crit_clk_hw_head in rzg2l_cpg_priv. Populate the list during module clock registration by checking for the CLK_IS_CRITICAL flag after clk_hw_register() succeeds. On resume, walk the list and re-enable any critical module clock that is found to be disabled, before deassering critical resets, ensuring the correct clock-before-reset restore ordering. Signed-off-by: Biju Das --- drivers/clk/renesas/rzg2l-cpg.c | 42 ++++++++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cp= g.c index 8165c163143a..f16c3962e0bd 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -130,6 +130,12 @@ struct div_hw_data { u32 width; }; =20 +/* Critical clk list */ +struct rzg2l_crit_clk_hw { + struct clk_hw *hw; + struct rzg2l_crit_clk_hw *next; +}; + #define to_div_hw_data(_hw) container_of(_hw, struct div_hw_data, hw_data) =20 struct rzg2l_pll5_param { @@ -168,6 +174,7 @@ struct rzg2l_pll5_mux_dsi_div_param { * @info: Pointer to platform data * @genpd: PM domain * @mux_dsi_div_params: pll5 mux and dsi div parameters + * @crit_clk_hw_head: Head of the linked list critical clk entries */ struct rzg2l_cpg_priv { struct reset_controller_dev rcdev; @@ -186,8 +193,26 @@ struct rzg2l_cpg_priv { struct generic_pm_domain genpd; =20 struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params; + + struct rzg2l_crit_clk_hw *crit_clk_hw_head; }; =20 +static int rzg2l_cpg_add_crit_clk_hw_entry(struct rzg2l_cpg_priv *priv, + struct clk_hw *hw) +{ + struct rzg2l_crit_clk_hw *node; + + node =3D devm_kzalloc(priv->dev, sizeof(*node), GFP_KERNEL); + if (!node) + return -ENOMEM; + + node->hw =3D hw; + node->next =3D priv->crit_clk_hw_head; + priv->crit_clk_hw_head =3D node; + + return 0; +} + static inline u8 rzg2l_cpg_div_ab(u8 a, u8 b) { return (b + 1) << a; @@ -1737,10 +1762,16 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_c= lk *mod, goto fail; } =20 + if (init.flags & CLK_IS_CRITICAL) { + if (rzg2l_cpg_add_crit_clk_hw_entry(priv, &clock->hw)) { + clk =3D ERR_PTR(-ENOMEM); + goto fail; + } + } + clk =3D clock->hw.clk; dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk)); priv->clks[id] =3D clk; - return; =20 fail: @@ -2086,8 +2117,17 @@ static int __init rzg2l_cpg_probe(struct platform_de= vice *pdev) static int rzg2l_cpg_resume(struct device *dev) { struct rzg2l_cpg_priv *priv =3D dev_get_drvdata(dev); + struct rzg2l_crit_clk_hw *node; int ret; =20 + for (node =3D priv->crit_clk_hw_head; node; node =3D node->next) { + if (!rzg2l_mod_clock_is_enabled(node->hw)) { + ret =3D rzg2l_mod_clock_endisable(node->hw, true); + if (ret) + return ret; + } + } + ret =3D rzg2l_cpg_deassert_crit_resets(&priv->rcdev, priv->info); if (ret) return ret; --=20 2.43.0