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([82.78.167.134]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485276b0c38sm38150505e9.9.2026.03.06.04.41.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 04:41:46 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, Frank.Li@kernel.org, biju.das.jz@bp.renesas.com, geert+renesas@glider.be, fabrizio.castro.jz@renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Cc: claudiu.beznea@tuxon.dev, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Claudiu Beznea Subject: [PATCH v9 8/8] dmaengine: sh: rz-dmac: Add device_{pause,resume}() callbacks Date: Fri, 6 Mar 2026 14:41:33 +0200 Message-ID: <20260306124133.2304687-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260306124133.2304687-1-claudiu.beznea.uj@bp.renesas.com> References: <20260306124133.2304687-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The RZ/G2L SCIFA driver uses dmaengine_prep_slave_sg() to enqueue DMA transfers and implements a timeout mechanism on RX to handle cases where a DMA transfer does not complete. The timeout is implemented using an hrtimer. In the hrtimer callback, dmaengine_tx_status() is called (along with dmaengine_pause()) to retrieve the transfer residue and handle incomplete DMA transfers. Add support for device_{pause, resume}() callbacks. Signed-off-by: Claudiu Beznea --- Changes in v9: - updated the patch description Changes in v8: - reported residue for paused channels as well Changes in v7: - use guard() instead of scoped_guard() - in rz_dmac_device_pause() checked the channel is enabled before suspending it to avoid read poll timeouts - added a comment in rz_dmac_device_resume() Changes in v6: - set CHCTRL_SETSUS for pause and CHCTRL_CLRSUS for resume - dropped read-modify-update approach for CHCTRL updates as the HW returns zero when reading CHCTRL - moved the read_poll_timeout_atomic() under spin lock to ensure avoid any races b/w pause and resume functionalities Changes in v5: - used suspend capability of the controller to pause/resume the transfers drivers/dma/sh/rz-dmac.c | 49 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 46 insertions(+), 3 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 3b318fe06f28..6ad41e0285f5 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -134,10 +134,12 @@ struct rz_dmac { #define CHANNEL_8_15_COMMON_BASE 0x0700 =20 #define CHSTAT_ER BIT(4) +#define CHSTAT_SUS BIT(3) #define CHSTAT_EN BIT(0) =20 #define CHCTRL_CLRINTMSK BIT(17) #define CHCTRL_CLRSUS BIT(9) +#define CHCTRL_SETSUS BIT(8) #define CHCTRL_CLRTC BIT(6) #define CHCTRL_CLREND BIT(5) #define CHCTRL_CLRRQ BIT(4) @@ -813,11 +815,18 @@ static enum dma_status rz_dmac_tx_status(struct dma_c= han *chan, if (status =3D=3D DMA_COMPLETE || !txstate) return status; =20 - scoped_guard(spinlock_irqsave, &channel->vc.lock) + scoped_guard(spinlock_irqsave, &channel->vc.lock) { + u32 val; + residue =3D rz_dmac_chan_get_residue(channel, cookie); =20 - /* if there's no residue, the cookie is complete */ - if (!residue) + val =3D rz_dmac_ch_readl(channel, CHSTAT, 1); + if (val & CHSTAT_SUS) + status =3D DMA_PAUSED; + } + + /* if there's no residue and no paused, the cookie is complete */ + if (!residue && status !=3D DMA_PAUSED) return DMA_COMPLETE; =20 dma_set_residue(txstate, residue); @@ -825,6 +834,38 @@ static enum dma_status rz_dmac_tx_status(struct dma_ch= an *chan, return status; } =20 +static int rz_dmac_device_pause(struct dma_chan *chan) +{ + struct rz_dmac_chan *channel =3D to_rz_dmac_chan(chan); + u32 val; + + guard(spinlock_irqsave)(&channel->vc.lock); + + val =3D rz_dmac_ch_readl(channel, CHSTAT, 1); + if (!(val & CHSTAT_EN)) + return 0; + + rz_dmac_ch_writel(channel, CHCTRL_SETSUS, CHCTRL, 1); + return read_poll_timeout_atomic(rz_dmac_ch_readl, val, + (val & CHSTAT_SUS), 1, 1024, + false, channel, CHSTAT, 1); +} + +static int rz_dmac_device_resume(struct dma_chan *chan) +{ + struct rz_dmac_chan *channel =3D to_rz_dmac_chan(chan); + u32 val; + + guard(spinlock_irqsave)(&channel->vc.lock); + + /* Do not check CHSTAT_SUS but rely on HW capabilities. */ + + rz_dmac_ch_writel(channel, CHCTRL_CLRSUS, CHCTRL, 1); + return read_poll_timeout_atomic(rz_dmac_ch_readl, val, + !(val & CHSTAT_SUS), 1, 1024, + false, channel, CHSTAT, 1); +} + /* * -----------------------------------------------------------------------= ------ * IRQ handling @@ -1162,6 +1203,8 @@ static int rz_dmac_probe(struct platform_device *pdev) engine->device_terminate_all =3D rz_dmac_terminate_all; engine->device_issue_pending =3D rz_dmac_issue_pending; engine->device_synchronize =3D rz_dmac_device_synchronize; + engine->device_pause =3D rz_dmac_device_pause; + engine->device_resume =3D rz_dmac_device_resume; =20 engine->copy_align =3D DMAENGINE_ALIGN_1_BYTE; dma_set_max_seg_size(engine->dev, U32_MAX); --=20 2.43.0