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Fri, 06 Mar 2026 04:06:45 -0800 (PST) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Fabien Parent , Val Packett , Luca Leonardo Scorcia , Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , AngeloGioacchino Del Regno , Liam Girdwood , Mark Brown , Louis-Alexis Eyraud , Julien Massot , Gary Bisson , Chen Zhong , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 5/7] regulator: mt6392: Add support for MT6392 regulator Date: Fri, 6 Mar 2026 12:03:09 +0000 Message-ID: <20260306120521.163654-6-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260306120521.163654-1-l.scorcia@gmail.com> References: <20260306120521.163654-1-l.scorcia@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fabien Parent The MT6392 is a regulator found on boards based on the MediaTek MT8167, MT8516, and probably other SoCs. It is a so called PMIC and connects as a slave to a SoC using SPI, wrapped inside PWRAP. Signed-off-by: Fabien Parent Co-developed-by: Val Packett Signed-off-by: Val Packett Signed-off-by: Luca Leonardo Scorcia --- drivers/regulator/Kconfig | 9 + drivers/regulator/Makefile | 1 + drivers/regulator/mt6392-regulator.c | 491 +++++++++++++++++++++ include/linux/regulator/mt6392-regulator.h | 40 ++ 4 files changed, 541 insertions(+) create mode 100644 drivers/regulator/mt6392-regulator.c create mode 100644 include/linux/regulator/mt6392-regulator.h diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index d2335276cce5..66876d730807 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -991,6 +991,15 @@ config REGULATOR_MT6380 This driver supports the control of different power rails of device through regulator interface. =20 +config REGULATOR_MT6392 + tristate "MediaTek MT6392 PMIC" + depends on MFD_MT6397 + help + Say y here to select this option to enable the power regulator of + MediaTek MT6392 PMIC. + This driver supports the control of different power rails of device + through regulator interface. + config REGULATOR_MT6397 tristate "MediaTek MT6397 PMIC" depends on MFD_MT6397 diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 1beba1493241..db5145cfcf36 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -117,6 +117,7 @@ obj-$(CONFIG_REGULATOR_MT6360) +=3D mt6360-regulator.o obj-$(CONFIG_REGULATOR_MT6363) +=3D mt6363-regulator.o obj-$(CONFIG_REGULATOR_MT6370) +=3D mt6370-regulator.o obj-$(CONFIG_REGULATOR_MT6380) +=3D mt6380-regulator.o +obj-$(CONFIG_REGULATOR_MT6392) +=3D mt6392-regulator.o obj-$(CONFIG_REGULATOR_MT6397) +=3D mt6397-regulator.o obj-$(CONFIG_REGULATOR_MTK_DVFSRC) +=3D mtk-dvfsrc-regulator.o obj-$(CONFIG_REGULATOR_QCOM_LABIBB) +=3D qcom-labibb-regulator.o diff --git a/drivers/regulator/mt6392-regulator.c b/drivers/regulator/mt639= 2-regulator.c new file mode 100644 index 000000000000..1c0e9bccfe86 --- /dev/null +++ b/drivers/regulator/mt6392-regulator.c @@ -0,0 +1,491 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. +// Copyright (c) 2020 BayLibre, SAS. +// Author: Chen Zhong +// Author: Fabien Parent +// +// Based on mt6397-regulator.c + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MT6392_BUCK_MODE_AUTO 0 +#define MT6392_BUCK_MODE_FORCE_PWM 1 +#define MT6392_LDO_MODE_NORMAL 0 +#define MT6392_LDO_MODE_LP 1 + +/* + * MT6392 regulators' information + * + * @desc: standard fields of regulator description. + * @qi: Mask for query enable signal status of regulators + * @vselon_reg: Register sections for hardware control mode of bucks + * @vselctrl_reg: Register for controlling the buck control mode. + * @vselctrl_mask: Mask for query buck's voltage control mode. + */ +struct mt6392_regulator_info { + struct regulator_desc desc; + u32 qi; + u32 vselon_reg; + u32 vselctrl_reg; + u32 vselctrl_mask; + u32 modeset_reg; + u32 modeset_mask; +}; + +#define MT6392_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \ + vosel, vosel_mask, voselon, vosel_ctrl, \ + _modeset_reg, _modeset_mask, rampdelay) \ +[MT6392_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6392_volt_range_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6392_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D (max - min)/step + 1, \ + .linear_ranges =3D volt_ranges, \ + .n_linear_ranges =3D ARRAY_SIZE(volt_ranges), \ + .vsel_reg =3D vosel, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(0), \ + .ramp_delay =3D rampdelay, \ + }, \ + .qi =3D BIT(13), \ + .vselon_reg =3D voselon, \ + .vselctrl_reg =3D vosel_ctrl, \ + .vselctrl_mask =3D BIT(1), \ + .modeset_reg =3D _modeset_reg, \ + .modeset_mask =3D _modeset_mask, \ +} + +#define MT6392_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ + vosel_mask, _modeset_reg, _modeset_mask, entime) \ +[MT6392_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6392_volt_table_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6392_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D ARRAY_SIZE(ldo_volt_table), \ + .volt_table =3D ldo_volt_table, \ + .vsel_reg =3D vosel, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + .enable_time =3D entime, \ + }, \ + .qi =3D BIT(15), \ + .modeset_reg =3D _modeset_reg, \ + .modeset_mask =3D _modeset_mask, \ +} + +#define MT6392_LDO_LINEAR(match, vreg, min, max, step, volt_ranges, \ + enreg, enbit, vosel, vosel_mask, _modeset_reg, \ + _modeset_mask, entime) \ +[MT6392_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6392_volt_ldo_range_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6392_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D (max - min)/step + 1, \ + .linear_ranges =3D volt_ranges, \ + .n_linear_ranges =3D ARRAY_SIZE(volt_ranges), \ + .vsel_reg =3D vosel, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + .enable_time =3D entime, \ + }, \ + .qi =3D BIT(15), \ + .modeset_reg =3D _modeset_reg, \ + .modeset_mask =3D _modeset_mask, \ +} + +#define MT6392_REG_FIXED(match, vreg, enreg, enbit, volt, \ + _modeset_reg, _modeset_mask, entime) \ +[MT6392_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6392_volt_fixed_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6392_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D 1, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + .enable_time =3D entime, \ + .min_uV =3D volt, \ + }, \ + .qi =3D BIT(15), \ + .modeset_reg =3D _modeset_reg, \ + .modeset_mask =3D _modeset_mask, \ +} + +#define MT6392_REG_FIXED_NO_MODE(match, vreg, enreg, enbit, volt, \ + entime) \ +[MT6392_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6392_volt_fixed_no_mode_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6392_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D 1, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + .enable_time =3D entime, \ + .min_uV =3D volt, \ + }, \ + .qi =3D BIT(15), \ +} + +static const struct linear_range buck_volt_range1[] =3D { + REGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250), +}; + +static const struct linear_range buck_volt_range2[] =3D { + REGULATOR_LINEAR_RANGE(1400000, 0, 0x7f, 12500), +}; + +static const u32 ldo_volt_table1[] =3D { + 1800000, 1900000, 2000000, 2200000, +}; + +static const struct linear_range ldo_volt_range2[] =3D { + REGULATOR_LINEAR_RANGE(3300000, 0, 3, 100000), +}; + +static const u32 ldo_volt_table3[] =3D { + 1800000, 3300000, +}; + +static const u32 ldo_volt_table4[] =3D { + 3000000, 3300000, +}; + +static const u32 ldo_volt_table5[] =3D { + 1200000, 1300000, 1500000, 1800000, 2000000, 2800000, 3000000, 3300000, +}; + +static const u32 ldo_volt_table6[] =3D { + 1240000, 1390000, +}; + +static const u32 ldo_volt_table7[] =3D { + 1200000, 1300000, 1500000, 1800000, +}; + +static const u32 ldo_volt_table8[] =3D { + 1800000, 2000000, +}; + +static int mt6392_buck_set_mode(struct regulator_dev *rdev, unsigned int m= ode) +{ + int ret, val =3D 0; + struct mt6392_regulator_info *info =3D rdev_get_drvdata(rdev); + + switch (mode) { + case REGULATOR_MODE_FAST: + val =3D MT6392_BUCK_MODE_FORCE_PWM; + break; + case REGULATOR_MODE_NORMAL: + val =3D MT6392_BUCK_MODE_AUTO; + break; + default: + return -EINVAL; + } + + val <<=3D ffs(info->modeset_mask) - 1; + + ret =3D regmap_update_bits(rdev->regmap, info->modeset_reg, + info->modeset_mask, val); + + return ret; +} + +static unsigned int mt6392_buck_get_mode(struct regulator_dev *rdev) +{ + unsigned int val; + unsigned int mode; + int ret; + struct mt6392_regulator_info *info =3D rdev_get_drvdata(rdev); + + ret =3D regmap_read(rdev->regmap, info->modeset_reg, &val); + if (ret < 0) + return ret; + + val &=3D info->modeset_mask; + val >>=3D ffs(info->modeset_mask) - 1; + + if (val & 0x1) + mode =3D REGULATOR_MODE_FAST; + else + mode =3D REGULATOR_MODE_NORMAL; + + return mode; +} + +static int mt6392_ldo_set_mode(struct regulator_dev *rdev, unsigned int mo= de) +{ + int ret, val =3D 0; + struct mt6392_regulator_info *info =3D rdev_get_drvdata(rdev); + + switch (mode) { + case REGULATOR_MODE_STANDBY: + val =3D MT6392_LDO_MODE_LP; + break; + case REGULATOR_MODE_NORMAL: + val =3D MT6392_LDO_MODE_NORMAL; + break; + default: + return -EINVAL; + } + + val <<=3D ffs(info->modeset_mask) - 1; + + ret =3D regmap_update_bits(rdev->regmap, info->modeset_reg, + info->modeset_mask, val); + + return ret; +} + +static unsigned int mt6392_ldo_get_mode(struct regulator_dev *rdev) +{ + unsigned int val; + unsigned int mode; + int ret; + struct mt6392_regulator_info *info =3D rdev_get_drvdata(rdev); + + ret =3D regmap_read(rdev->regmap, info->modeset_reg, &val); + if (ret < 0) + return ret; + + val &=3D info->modeset_mask; + val >>=3D ffs(info->modeset_mask) - 1; + + if (val & 0x1) + mode =3D REGULATOR_MODE_STANDBY; + else + mode =3D REGULATOR_MODE_NORMAL; + + return mode; +} + +static const struct regulator_ops mt6392_volt_range_ops =3D { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .set_mode =3D mt6392_buck_set_mode, + .get_mode =3D mt6392_buck_get_mode, +}; + +static const struct regulator_ops mt6392_volt_table_ops =3D { + .list_voltage =3D regulator_list_voltage_table, + .map_voltage =3D regulator_map_voltage_iterate, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .set_mode =3D mt6392_ldo_set_mode, + .get_mode =3D mt6392_ldo_get_mode, +}; + +static const struct regulator_ops mt6392_volt_ldo_range_ops =3D { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .set_mode =3D mt6392_ldo_set_mode, + .get_mode =3D mt6392_ldo_get_mode, +}; + +static const struct regulator_ops mt6392_volt_fixed_ops =3D { + .list_voltage =3D regulator_list_voltage_linear, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .set_mode =3D mt6392_ldo_set_mode, + .get_mode =3D mt6392_ldo_get_mode, +}; + +static const struct regulator_ops mt6392_volt_fixed_no_mode_ops =3D { + .list_voltage =3D regulator_list_voltage_linear, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, +}; + +/* The array is indexed by id(MT6392_ID_XXX) */ +static struct mt6392_regulator_info mt6392_regulators[] =3D { + MT6392_BUCK("buck_vproc", VPROC, 700000, 1493750, 6250, + buck_volt_range1, MT6392_VPROC_CON7, MT6392_VPROC_CON9, 0x7f, + MT6392_VPROC_CON10, MT6392_VPROC_CON5, MT6392_VPROC_CON2, + 0x100, 12500), + MT6392_BUCK("buck_vsys", VSYS, 1400000, 2987500, 12500, + buck_volt_range2, MT6392_VSYS_CON7, MT6392_VSYS_CON9, 0x7f, + MT6392_VSYS_CON10, MT6392_VSYS_CON5, MT6392_VSYS_CON2, 0x100, + 25000), + MT6392_BUCK("buck_vcore", VCORE, 700000, 1493750, 6250, + buck_volt_range1, MT6392_VCORE_CON7, MT6392_VCORE_CON9, 0x7f, + MT6392_VCORE_CON10, MT6392_VCORE_CON5, MT6392_VCORE_CON2, + 0x100, 12500), + MT6392_REG_FIXED("ldo_vxo22", VXO22, MT6392_ANALDO_CON1, 10, 2200000, + MT6392_ANALDO_CON1, 0x2, 110), + MT6392_LDO("ldo_vaud22", VAUD22, ldo_volt_table1, + MT6392_ANALDO_CON2, 14, MT6392_ANALDO_CON8, 0x60, + MT6392_ANALDO_CON2, 0x2, 264), + MT6392_REG_FIXED_NO_MODE("ldo_vcama", VCAMA, MT6392_ANALDO_CON4, 15, + 2800000, 264), + MT6392_REG_FIXED("ldo_vaud28", VAUD28, MT6392_ANALDO_CON23, 14, 2800000, + MT6392_ANALDO_CON23, 0x2, 264), + MT6392_REG_FIXED("ldo_vadc18", VADC18, MT6392_ANALDO_CON25, 14, 1800000, + MT6392_ANALDO_CON25, 0x2, 264), + MT6392_LDO_LINEAR("ldo_vcn35", VCN35, 3300000, 3600000, 100000, + ldo_volt_range2, MT6392_ANALDO_CON21, 12, MT6392_ANALDO_CON16, + 0xC, MT6392_ANALDO_CON21, 0x2, 264), + MT6392_REG_FIXED("ldo_vio28", VIO28, MT6392_DIGLDO_CON0, 14, 2800000, + MT6392_DIGLDO_CON0, 0x2, 264), + MT6392_REG_FIXED("ldo_vusb", VUSB, MT6392_DIGLDO_CON2, 14, 3300000, + MT6392_DIGLDO_CON2, 0x2, 264), + MT6392_LDO("ldo_vmc", VMC, ldo_volt_table3, + MT6392_DIGLDO_CON3, 12, MT6392_DIGLDO_CON24, 0x10, + MT6392_DIGLDO_CON3, 0x2, 264), + MT6392_LDO("ldo_vmch", VMCH, ldo_volt_table4, + MT6392_DIGLDO_CON5, 14, MT6392_DIGLDO_CON26, 0x80, + MT6392_DIGLDO_CON5, 0x2, 264), + MT6392_LDO("ldo_vemc3v3", VEMC3V3, ldo_volt_table4, + MT6392_DIGLDO_CON6, 14, MT6392_DIGLDO_CON27, 0x80, + MT6392_DIGLDO_CON6, 0x2, 264), + MT6392_LDO("ldo_vgp1", VGP1, ldo_volt_table5, + MT6392_DIGLDO_CON7, 15, MT6392_DIGLDO_CON28, 0xE0, + MT6392_DIGLDO_CON7, 0x2, 264), + MT6392_LDO("ldo_vgp2", VGP2, ldo_volt_table5, + MT6392_DIGLDO_CON8, 15, MT6392_DIGLDO_CON29, 0xE0, + MT6392_DIGLDO_CON8, 0x2, 264), + MT6392_REG_FIXED("ldo_vcn18", VCN18, MT6392_DIGLDO_CON11, 14, 1800000, + MT6392_DIGLDO_CON11, 0x2, 264), + MT6392_LDO("ldo_vcamaf", VCAMAF, ldo_volt_table5, + MT6392_DIGLDO_CON31, 15, MT6392_DIGLDO_CON32, 0xE0, + MT6392_DIGLDO_CON31, 0x2, 264), + MT6392_LDO("ldo_vm", VM, ldo_volt_table6, + MT6392_DIGLDO_CON47, 14, MT6392_DIGLDO_CON48, 0x30, + MT6392_DIGLDO_CON47, 0x2, 264), + MT6392_REG_FIXED("ldo_vio18", VIO18, MT6392_DIGLDO_CON49, 14, 1800000, + MT6392_DIGLDO_CON49, 0x2, 264), + MT6392_LDO("ldo_vcamd", VCAMD, ldo_volt_table7, + MT6392_DIGLDO_CON51, 14, MT6392_DIGLDO_CON52, 0x60, + MT6392_DIGLDO_CON51, 0x2, 264), + MT6392_REG_FIXED("ldo_vcamio", VCAMIO, MT6392_DIGLDO_CON53, 14, 1800000, + MT6392_DIGLDO_CON53, 0x2, 264), + MT6392_REG_FIXED("ldo_vm25", VM25, MT6392_DIGLDO_CON55, 14, 2500000, + MT6392_DIGLDO_CON55, 0x2, 264), + MT6392_LDO("ldo_vefuse", VEFUSE, ldo_volt_table8, + MT6392_DIGLDO_CON57, 14, MT6392_DIGLDO_CON58, 0x10, + MT6392_DIGLDO_CON57, 0x2, 264), +}; + +static int mt6392_set_buck_vosel_reg(struct platform_device *pdev) +{ + struct mt6397_chip *mt6392 =3D dev_get_drvdata(pdev->dev.parent); + int i; + u32 regval; + + for (i =3D 0; i < MT6392_MAX_REGULATOR; i++) { + if (mt6392_regulators[i].vselctrl_reg) { + if (regmap_read(mt6392->regmap, + mt6392_regulators[i].vselctrl_reg, + ®val) < 0) { + dev_err(&pdev->dev, + "Failed to read buck ctrl\n"); + return -EIO; + } + + if (regval & mt6392_regulators[i].vselctrl_mask) { + mt6392_regulators[i].desc.vsel_reg =3D + mt6392_regulators[i].vselon_reg; + } + } + } + + return 0; +} + +static int mt6392_regulator_probe(struct platform_device *pdev) +{ + struct mt6397_chip *mt6392 =3D dev_get_drvdata(pdev->dev.parent); + struct regulator_config config =3D {}; + struct regulator_dev *rdev; + int i; + + /* Query buck controller to select activated voltage register part */ + if (mt6392_set_buck_vosel_reg(pdev)) + return -EIO; + + for (i =3D 0; i < MT6392_MAX_REGULATOR; i++) { + config.dev =3D &pdev->dev; + config.driver_data =3D &mt6392_regulators[i]; + config.regmap =3D mt6392->regmap; + + rdev =3D devm_regulator_register(&pdev->dev, + &mt6392_regulators[i].desc, + &config); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register %s\n", + mt6392_regulators[i].desc.name); + return PTR_ERR(rdev); + } + } + + return 0; +} + +static const struct platform_device_id mt6392_platform_ids[] =3D { + {"mt6392-regulator", 0}, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(platform, mt6392_platform_ids); + +static struct platform_driver mt6392_regulator_driver =3D { + .driver =3D { + .name =3D "mt6392-regulator", + }, + .probe =3D mt6392_regulator_probe, + .id_table =3D mt6392_platform_ids, +}; + +module_platform_driver(mt6392_regulator_driver); + +MODULE_AUTHOR("Chen Zhong "); +MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6392 PMIC"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/regulator/mt6392-regulator.h b/include/linux/reg= ulator/mt6392-regulator.h new file mode 100644 index 000000000000..dfcbcacb5ad4 --- /dev/null +++ b/include/linux/regulator/mt6392-regulator.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Chen Zhong + */ + +#ifndef __LINUX_REGULATOR_MT6392_H +#define __LINUX_REGULATOR_MT6392_H + +enum { + MT6392_ID_VPROC =3D 0, + MT6392_ID_VSYS, + MT6392_ID_VCORE, + MT6392_ID_VXO22, + MT6392_ID_VAUD22, + MT6392_ID_VCAMA, + MT6392_ID_VAUD28, + MT6392_ID_VADC18, + MT6392_ID_VCN35, + MT6392_ID_VIO28, + MT6392_ID_VUSB =3D 10, + MT6392_ID_VMC, + MT6392_ID_VMCH, + MT6392_ID_VEMC3V3, + MT6392_ID_VGP1, + MT6392_ID_VGP2, + MT6392_ID_VCN18, + MT6392_ID_VCAMAF, + MT6392_ID_VM, + MT6392_ID_VIO18, + MT6392_ID_VCAMD, + MT6392_ID_VCAMIO, + MT6392_ID_VM25, + MT6392_ID_VEFUSE, + MT6392_ID_RG_MAX, +}; + +#define MT6392_MAX_REGULATOR MT6392_ID_RG_MAX + +#endif /* __LINUX_REGULATOR_MT6392_H */ --=20 2.43.0