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Fri, 06 Mar 2026 04:06:01 -0800 (PST) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Fabien Parent , Val Packett , Luca Leonardo Scorcia , Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , AngeloGioacchino Del Regno , Liam Girdwood , Mark Brown , Gary Bisson , Julien Massot , Louis-Alexis Eyraud , Chen Zhong , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/7] dt-bindings: mfd: mt6397: Add bindings for MT6392 PMIC Date: Fri, 6 Mar 2026 12:03:05 +0000 Message-ID: <20260306120521.163654-2-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260306120521.163654-1-l.scorcia@gmail.com> References: <20260306120521.163654-1-l.scorcia@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fabien Parent Add the currently supported bindings for the MT6392 PMIC. Signed-off-by: Fabien Parent Signed-off-by: Val Packett Signed-off-by: Luca Leonardo Scorcia --- .../devicetree/bindings/mfd/mediatek,mt6397.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml b/D= ocumentation/devicetree/bindings/mfd/mediatek,mt6397.yaml index 6a89b479d10f..c358b2f8059c 100644 --- a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml @@ -40,6 +40,10 @@ properties: - mediatek,mt6358 - mediatek,mt6359 - mediatek,mt6397 + - items: + - enum: + - mediatek,mt6392 + - const: mediatek,mt6323 - items: - enum: - mediatek,mt6366 @@ -72,6 +76,10 @@ properties: - enum: - mediatek,mt6366-rtc - const: mediatek,mt6358-rtc + - items: + - enum: + - mediatek,mt6392-rtc + - const: mediatek,mt6397-rtc =20 start-year: true =20 --=20 2.43.0 From nobody Thu Apr 9 18:40:10 2026 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56F14385521 for ; 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charset="utf-8" From: Fabien Parent Add binding documentation of the regulator for MT6392 SoCs. Signed-off-by: Fabien Parent Signed-off-by: Val Packett Signed-off-by: Luca Leonardo Scorcia Acked-by: Rob Herring (Arm) Acked-by: Mark Brown --- Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml b/D= ocumentation/devicetree/bindings/mfd/mediatek,mt6397.yaml index c358b2f8059c..bb1456d01ba9 100644 --- a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml @@ -100,6 +100,7 @@ properties: - mediatek,mt6328-regulator - mediatek,mt6358-regulator - mediatek,mt6359-regulator + - mediatek,mt6392-regulator - mediatek,mt6397-regulator - items: - enum: --=20 2.43.0 From nobody Thu Apr 9 18:40:10 2026 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2710838C413 for ; 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charset="utf-8" From: Fabien Parent Add the binding documentation of the mtk-pmic-keys for the MT6392 PMICs. Signed-off-by: Fabien Parent Signed-off-by: Val Packett Signed-off-by: Luca Leonardo Scorcia Acked-by: Dmitry Torokhov Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yam= l b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml index b95435bd6a9b..2d3c4161a7f8 100644 --- a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml +++ b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml @@ -30,6 +30,7 @@ properties: - mediatek,mt6357-keys - mediatek,mt6358-keys - mediatek,mt6359-keys + - mediatek,mt6392-keys - mediatek,mt6397-keys =20 power-off-time-sec: true --=20 2.43.0 From nobody Thu Apr 9 18:40:10 2026 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5169138E12D for ; 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charset="utf-8" From: Fabien Parent Update the MT6397 MFD driver to support the MT6392 PMIC. Signed-off-by: Fabien Parent Signed-off-by: Val Packett Signed-off-by: Luca Leonardo Scorcia --- drivers/mfd/mt6397-core.c | 43 +++ drivers/mfd/mt6397-irq.c | 8 + include/linux/mfd/mt6392/core.h | 42 +++ include/linux/mfd/mt6392/registers.h | 487 +++++++++++++++++++++++++++ include/linux/mfd/mt6397/core.h | 1 + 5 files changed, 581 insertions(+) create mode 100644 include/linux/mfd/mt6392/core.h create mode 100644 include/linux/mfd/mt6392/registers.h diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c index 3e58d0764c7e..c3f9cc89652d 100644 --- a/drivers/mfd/mt6397-core.c +++ b/drivers/mfd/mt6397-core.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -25,6 +26,7 @@ #include #include #include +#include #include =20 #define MT6323_RTC_BASE 0x8000 @@ -39,6 +41,9 @@ #define MT6358_RTC_BASE 0x0588 #define MT6358_RTC_SIZE 0x3c =20 +#define MT6392_RTC_BASE 0x8000 +#define MT6392_RTC_SIZE 0x3e + #define MT6397_RTC_BASE 0xe000 #define MT6397_RTC_SIZE 0x3e =20 @@ -65,6 +70,11 @@ static const struct resource mt6358_rtc_resources[] =3D { DEFINE_RES_IRQ(MT6358_IRQ_RTC), }; =20 +static const struct resource mt6392_rtc_resources[] =3D { + DEFINE_RES_MEM(MT6392_RTC_BASE, MT6392_RTC_SIZE), + DEFINE_RES_IRQ(MT6392_IRQ_RTC), +}; + static const struct resource mt6397_rtc_resources[] =3D { DEFINE_RES_MEM(MT6397_RTC_BASE, MT6397_RTC_SIZE), DEFINE_RES_IRQ(MT6397_IRQ_RTC), @@ -114,6 +124,11 @@ static const struct resource mt6331_keys_resources[] = =3D { DEFINE_RES_IRQ_NAMED(MT6331_IRQ_STATUS_HOMEKEY, "homekey"), }; =20 +static const struct resource mt6392_keys_resources[] =3D { + DEFINE_RES_IRQ_NAMED(MT6392_IRQ_PWRKEY, "powerkey"), + DEFINE_RES_IRQ_NAMED(MT6392_IRQ_FCHRKEY, "homekey"), +}; + static const struct resource mt6397_keys_resources[] =3D { DEFINE_RES_IRQ_NAMED(MT6397_IRQ_PWRKEY, "powerkey"), DEFINE_RES_IRQ_NAMED(MT6397_IRQ_HOMEKEY, "homekey"), @@ -253,6 +268,23 @@ static const struct mfd_cell mt6359_devs[] =3D { }, }; =20 +static const struct mfd_cell mt6392_devs[] =3D { + { + .name =3D "mt6392-rtc", + .num_resources =3D ARRAY_SIZE(mt6392_rtc_resources), + .resources =3D mt6392_rtc_resources, + .of_compatible =3D "mediatek,mt6392-rtc", + }, { + .name =3D "mt6392-regulator", + .of_compatible =3D "mediatek,mt6392-regulator", + }, { + .name =3D "mtk-pmic-keys", + .num_resources =3D ARRAY_SIZE(mt6392_keys_resources), + .resources =3D mt6392_keys_resources, + .of_compatible =3D "mediatek,mt6392-keys" + }, +}; + static const struct mfd_cell mt6397_devs[] =3D { { .name =3D "mt6397-rtc", @@ -335,6 +367,14 @@ static const struct chip_data mt6359_core =3D { .irq_init =3D mt6358_irq_init, }; =20 +static const struct chip_data mt6392_core =3D { + .cid_addr =3D MT6392_CID, + .cid_shift =3D 0, + .cells =3D mt6392_devs, + .cell_size =3D ARRAY_SIZE(mt6392_devs), + .irq_init =3D mt6397_irq_init, +}; + static const struct chip_data mt6397_core =3D { .cid_addr =3D MT6397_CID, .cid_shift =3D 0, @@ -416,6 +456,9 @@ static const struct of_device_id mt6397_of_match[] =3D { }, { .compatible =3D "mediatek,mt6359", .data =3D &mt6359_core, + }, { + .compatible =3D "mediatek,mt6392", + .data =3D &mt6392_core, }, { .compatible =3D "mediatek,mt6397", .data =3D &mt6397_core, diff --git a/drivers/mfd/mt6397-irq.c b/drivers/mfd/mt6397-irq.c index 5d2e5459f744..80ea5b92d232 100644 --- a/drivers/mfd/mt6397-irq.c +++ b/drivers/mfd/mt6397-irq.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include #include #include =20 @@ -203,6 +205,12 @@ int mt6397_irq_init(struct mt6397_chip *chip) chip->int_status[0] =3D MT6397_INT_STATUS0; chip->int_status[1] =3D MT6397_INT_STATUS1; break; + case MT6392_CHIP_ID: + chip->int_con[0] =3D MT6392_INT_CON0; + chip->int_con[1] =3D MT6392_INT_CON1; + chip->int_status[0] =3D MT6392_INT_STATUS0; + chip->int_status[1] =3D MT6392_INT_STATUS1; + break; =20 default: dev_err(chip->dev, "unsupported chip: 0x%x\n", chip->chip_id); diff --git a/include/linux/mfd/mt6392/core.h b/include/linux/mfd/mt6392/cor= e.h new file mode 100644 index 000000000000..4780dab4da92 --- /dev/null +++ b/include/linux/mfd/mt6392/core.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Chen Zhong + */ + +#ifndef __MFD_MT6392_CORE_H__ +#define __MFD_MT6392_CORE_H__ + +enum mt6392_irq_numbers { + MT6392_IRQ_SPKL_AB =3D 0, + MT6392_IRQ_SPKL, + MT6392_IRQ_BAT_L, + MT6392_IRQ_BAT_H, + MT6392_IRQ_WATCHDOG, + MT6392_IRQ_PWRKEY, + MT6392_IRQ_THR_L, + MT6392_IRQ_THR_H, + MT6392_IRQ_VBATON_UNDET, + MT6392_IRQ_BVALID_DET, + MT6392_IRQ_CHRDET, + MT6392_IRQ_OV, + MT6392_IRQ_LDO =3D 16, + MT6392_IRQ_FCHRKEY, + MT6392_IRQ_RELEASE_PWRKEY, + MT6392_IRQ_RELEASE_FCHRKEY, + MT6392_IRQ_RTC, + MT6392_IRQ_VPROC, + MT6392_IRQ_VSYS, + MT6392_IRQ_VCORE, + MT6392_IRQ_TYPE_C_CC, + MT6392_IRQ_TYPEC_H_MAX, + MT6392_IRQ_TYPEC_H_MIN, + MT6392_IRQ_TYPEC_L_MAX, + MT6392_IRQ_TYPEC_L_MIN, + MT6392_IRQ_THR_MAX, + MT6392_IRQ_THR_MIN, + MT6392_IRQ_NAG_C_DLTV, + MT6392_IRQ_NR, +}; + +#endif /* __MFD_MT6392_CORE_H__ */ diff --git a/include/linux/mfd/mt6392/registers.h b/include/linux/mfd/mt639= 2/registers.h new file mode 100644 index 000000000000..4f3a6db830d1 --- /dev/null +++ b/include/linux/mfd/mt6392/registers.h @@ -0,0 +1,487 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Chen Zhong + */ + +#ifndef __MFD_MT6392_REGISTERS_H__ +#define __MFD_MT6392_REGISTERS_H__ + +/* PMIC Registers */ +#define MT6392_CHR_CON0 0x0000 +#define MT6392_CHR_CON1 0x0002 +#define MT6392_CHR_CON2 0x0004 +#define MT6392_CHR_CON3 0x0006 +#define MT6392_CHR_CON4 0x0008 +#define MT6392_CHR_CON5 0x000A +#define MT6392_CHR_CON6 0x000C +#define MT6392_CHR_CON7 0x000E +#define MT6392_CHR_CON8 0x0010 +#define MT6392_CHR_CON9 0x0012 +#define MT6392_CHR_CON10 0x0014 +#define MT6392_CHR_CON11 0x0016 +#define MT6392_CHR_CON12 0x0018 +#define MT6392_CHR_CON13 0x001A +#define MT6392_CHR_CON14 0x001C +#define MT6392_CHR_CON15 0x001E +#define MT6392_CHR_CON16 0x0020 +#define MT6392_CHR_CON17 0x0022 +#define MT6392_CHR_CON18 0x0024 +#define MT6392_CHR_CON19 0x0026 +#define MT6392_CHR_CON20 0x0028 +#define MT6392_CHR_CON21 0x002A +#define MT6392_CHR_CON22 0x002C +#define MT6392_CHR_CON23 0x002E +#define MT6392_CHR_CON24 0x0030 +#define MT6392_CHR_CON25 0x0032 +#define MT6392_CHR_CON26 0x0034 +#define MT6392_CHR_CON27 0x0036 +#define MT6392_CHR_CON28 0x0038 +#define MT6392_CHR_CON29 0x003A +#define MT6392_STRUP_CON0 0x003C +#define MT6392_STRUP_CON2 0x003E +#define MT6392_STRUP_CON3 0x0040 +#define MT6392_STRUP_CON4 0x0042 +#define MT6392_STRUP_CON5 0x0044 +#define MT6392_STRUP_CON6 0x0046 +#define MT6392_STRUP_CON7 0x0048 +#define MT6392_STRUP_CON8 0x004A +#define MT6392_STRUP_CON9 0x004C +#define MT6392_STRUP_CON10 0x004E +#define MT6392_STRUP_CON11 0x0050 +#define MT6392_SPK_CON0 0x0052 +#define MT6392_SPK_CON1 0x0054 +#define MT6392_SPK_CON2 0x0056 +#define MT6392_SPK_CON6 0x005E +#define MT6392_SPK_CON7 0x0060 +#define MT6392_SPK_CON8 0x0062 +#define MT6392_SPK_CON9 0x0064 +#define MT6392_SPK_CON10 0x0066 +#define MT6392_SPK_CON11 0x0068 +#define MT6392_SPK_CON12 0x006A +#define MT6392_STRUP_CON12 0x006E +#define MT6392_STRUP_CON13 0x0070 +#define MT6392_STRUP_CON14 0x0072 +#define MT6392_STRUP_CON15 0x0074 +#define MT6392_STRUP_CON16 0x0076 +#define MT6392_STRUP_CON17 0x0078 +#define MT6392_STRUP_CON18 0x007A +#define MT6392_STRUP_CON19 0x007C +#define MT6392_STRUP_CON20 0x007E +#define MT6392_CID 0x0100 +#define MT6392_TOP_CKPDN0 0x0102 +#define MT6392_TOP_CKPDN0_SET 0x0104 +#define MT6392_TOP_CKPDN0_CLR 0x0106 +#define MT6392_TOP_CKPDN1 0x0108 +#define MT6392_TOP_CKPDN1_SET 0x010A +#define MT6392_TOP_CKPDN1_CLR 0x010C +#define MT6392_TOP_CKPDN2 0x010E +#define MT6392_TOP_CKPDN2_SET 0x0110 +#define MT6392_TOP_CKPDN2_CLR 0x0112 +#define MT6392_TOP_RST_CON 0x0114 +#define MT6392_TOP_RST_CON_SET 0x0116 +#define MT6392_TOP_RST_CON_CLR 0x0118 +#define MT6392_TOP_RST_MISC 0x011A +#define MT6392_TOP_RST_MISC_SET 0x011C +#define MT6392_TOP_RST_MISC_CLR 0x011E +#define MT6392_TOP_CKCON0 0x0120 +#define MT6392_TOP_CKCON0_SET 0x0122 +#define MT6392_TOP_CKCON0_CLR 0x0124 +#define MT6392_TOP_CKCON1 0x0126 +#define MT6392_TOP_CKCON1_SET 0x0128 +#define MT6392_TOP_CKCON1_CLR 0x012A +#define MT6392_TOP_CKTST0 0x012C +#define MT6392_TOP_CKTST1 0x012E +#define MT6392_TOP_CKTST2 0x0130 +#define MT6392_TEST_OUT 0x0132 +#define MT6392_TEST_CON0 0x0134 +#define MT6392_TEST_CON1 0x0136 +#define MT6392_EN_STATUS0 0x0138 +#define MT6392_EN_STATUS1 0x013A +#define MT6392_OCSTATUS0 0x013C +#define MT6392_OCSTATUS1 0x013E +#define MT6392_PGSTATUS 0x0140 +#define MT6392_CHRSTATUS 0x0142 +#define MT6392_TDSEL_CON 0x0144 +#define MT6392_RDSEL_CON 0x0146 +#define MT6392_SMT_CON0 0x0148 +#define MT6392_SMT_CON1 0x014A +#define MT6392_DRV_CON0 0x0152 +#define MT6392_DRV_CON1 0x0154 +#define MT6392_INT_CON0 0x0160 +#define MT6392_INT_CON0_SET 0x0162 +#define MT6392_INT_CON0_CLR 0x0164 +#define MT6392_INT_CON1 0x0166 +#define MT6392_INT_CON1_SET 0x0168 +#define MT6392_INT_CON1_CLR 0x016A +#define MT6392_INT_MISC_CON 0x016C +#define MT6392_INT_MISC_CON_SET 0x016E +#define MT6392_INT_MISC_CON_CLR 0x0170 +#define MT6392_INT_STATUS0 0x0172 +#define MT6392_INT_STATUS1 0x0174 +#define MT6392_OC_GEAR_0 0x0176 +#define MT6392_OC_GEAR_1 0x0178 +#define MT6392_OC_GEAR_2 0x017A +#define MT6392_OC_CTL_VPROC 0x017C +#define MT6392_OC_CTL_VSYS 0x017E +#define MT6392_OC_CTL_VCORE 0x0180 +#define MT6392_FQMTR_CON0 0x0182 +#define MT6392_FQMTR_CON1 0x0184 +#define MT6392_FQMTR_CON2 0x0186 +#define MT6392_RG_SPI_CON 0x0188 +#define MT6392_DEW_DIO_EN 0x018A +#define MT6392_DEW_READ_TEST 0x018C +#define MT6392_DEW_WRITE_TEST 0x018E +#define MT6392_DEW_CRC_SWRST 0x0190 +#define MT6392_DEW_CRC_EN 0x0192 +#define MT6392_DEW_CRC_VAL 0x0194 +#define MT6392_DEW_DBG_MON_SEL 0x0196 +#define MT6392_DEW_CIPHER_KEY_SEL 0x0198 +#define MT6392_DEW_CIPHER_IV_SEL 0x019A +#define MT6392_DEW_CIPHER_EN 0x019C +#define MT6392_DEW_CIPHER_RDY 0x019E +#define MT6392_DEW_CIPHER_MODE 0x01A0 +#define MT6392_DEW_CIPHER_SWRST 0x01A2 +#define MT6392_DEW_RDDMY_NO 0x01A4 +#define MT6392_DEW_RDATA_DLY_SEL 0x01A6 +#define MT6392_CLK_TRIM_CON0 0x01A8 +#define MT6392_BUCK_CON0 0x0200 +#define MT6392_BUCK_CON1 0x0202 +#define MT6392_BUCK_CON2 0x0204 +#define MT6392_BUCK_CON3 0x0206 +#define MT6392_BUCK_CON4 0x0208 +#define MT6392_BUCK_CON5 0x020A +#define MT6392_VPROC_CON0 0x020C +#define MT6392_VPROC_CON1 0x020E +#define MT6392_VPROC_CON2 0x0210 +#define MT6392_VPROC_CON3 0x0212 +#define MT6392_VPROC_CON4 0x0214 +#define MT6392_VPROC_CON5 0x0216 +#define MT6392_VPROC_CON7 0x021A +#define MT6392_VPROC_CON8 0x021C +#define MT6392_VPROC_CON9 0x021E +#define MT6392_VPROC_CON10 0x0220 +#define MT6392_VPROC_CON11 0x0222 +#define MT6392_VPROC_CON12 0x0224 +#define MT6392_VPROC_CON13 0x0226 +#define MT6392_VPROC_CON14 0x0228 +#define MT6392_VPROC_CON15 0x022A +#define MT6392_VPROC_CON18 0x0230 +#define MT6392_VSYS_CON0 0x0232 +#define MT6392_VSYS_CON1 0x0234 +#define MT6392_VSYS_CON2 0x0236 +#define MT6392_VSYS_CON3 0x0238 +#define MT6392_VSYS_CON4 0x023A +#define MT6392_VSYS_CON5 0x023C +#define MT6392_VSYS_CON7 0x0240 +#define MT6392_VSYS_CON8 0x0242 +#define MT6392_VSYS_CON9 0x0244 +#define MT6392_VSYS_CON10 0x0246 +#define MT6392_VSYS_CON11 0x0248 +#define MT6392_VSYS_CON12 0x024A +#define MT6392_VSYS_CON13 0x024C +#define MT6392_VSYS_CON14 0x024E +#define MT6392_VSYS_CON15 0x0250 +#define MT6392_VSYS_CON18 0x0256 +#define MT6392_BUCK_OC_CON0 0x0258 +#define MT6392_BUCK_OC_CON1 0x025A +#define MT6392_BUCK_OC_CON2 0x025C +#define MT6392_BUCK_OC_CON3 0x025E +#define MT6392_BUCK_OC_CON4 0x0260 +#define MT6392_BUCK_OC_VPROC_CON0 0x0262 +#define MT6392_BUCK_OC_VCORE_CON0 0x0264 +#define MT6392_BUCK_OC_VSYS_CON0 0x0266 +#define MT6392_BUCK_ANA_MON_CON0 0x0268 +#define MT6392_BUCK_EFUSE_OC_CON0 0x026A +#define MT6392_VCORE_CON0 0x0300 +#define MT6392_VCORE_CON1 0x0302 +#define MT6392_VCORE_CON2 0x0304 +#define MT6392_VCORE_CON3 0x0306 +#define MT6392_VCORE_CON4 0x0308 +#define MT6392_VCORE_CON5 0x030A +#define MT6392_VCORE_CON7 0x030E +#define MT6392_VCORE_CON8 0x0310 +#define MT6392_VCORE_CON9 0x0312 +#define MT6392_VCORE_CON10 0x0314 +#define MT6392_VCORE_CON11 0x0316 +#define MT6392_VCORE_CON12 0x0318 +#define MT6392_VCORE_CON13 0x031A +#define MT6392_VCORE_CON14 0x031C +#define MT6392_VCORE_CON15 0x031E +#define MT6392_VCORE_CON18 0x0324 +#define MT6392_BUCK_K_CON0 0x032A +#define MT6392_BUCK_K_CON1 0x032C +#define MT6392_BUCK_K_CON2 0x032E +#define MT6392_ANALDO_CON0 0x0400 +#define MT6392_ANALDO_CON1 0x0402 +#define MT6392_ANALDO_CON2 0x0404 +#define MT6392_ANALDO_CON3 0x0406 +#define MT6392_ANALDO_CON4 0x0408 +#define MT6392_ANALDO_CON6 0x040C +#define MT6392_ANALDO_CON7 0x040E +#define MT6392_ANALDO_CON8 0x0410 +#define MT6392_ANALDO_CON10 0x0412 +#define MT6392_ANALDO_CON15 0x0414 +#define MT6392_ANALDO_CON16 0x0416 +#define MT6392_ANALDO_CON17 0x0418 +#define MT6392_ANALDO_CON21 0x0420 +#define MT6392_ANALDO_CON22 0x0422 +#define MT6392_ANALDO_CON23 0x0424 +#define MT6392_ANALDO_CON24 0x0426 +#define MT6392_ANALDO_CON25 0x0428 +#define MT6392_ANALDO_CON26 0x042A +#define MT6392_ANALDO_CON27 0x042C +#define MT6392_ANALDO_CON28 0x042E +#define MT6392_ANALDO_CON29 0x0430 +#define MT6392_DIGLDO_CON0 0x0500 +#define MT6392_DIGLDO_CON2 0x0502 +#define MT6392_DIGLDO_CON3 0x0504 +#define MT6392_DIGLDO_CON5 0x0506 +#define MT6392_DIGLDO_CON6 0x0508 +#define MT6392_DIGLDO_CON7 0x050A +#define MT6392_DIGLDO_CON8 0x050C +#define MT6392_DIGLDO_CON10 0x0510 +#define MT6392_DIGLDO_CON11 0x0512 +#define MT6392_DIGLDO_CON12 0x0514 +#define MT6392_DIGLDO_CON15 0x051A +#define MT6392_DIGLDO_CON20 0x0524 +#define MT6392_DIGLDO_CON21 0x0526 +#define MT6392_DIGLDO_CON23 0x0528 +#define MT6392_DIGLDO_CON24 0x052A +#define MT6392_DIGLDO_CON26 0x052C +#define MT6392_DIGLDO_CON27 0x052E +#define MT6392_DIGLDO_CON28 0x0530 +#define MT6392_DIGLDO_CON29 0x0532 +#define MT6392_DIGLDO_CON30 0x0534 +#define MT6392_DIGLDO_CON31 0x0536 +#define MT6392_DIGLDO_CON32 0x0538 +#define MT6392_DIGLDO_CON33 0x053A +#define MT6392_DIGLDO_CON36 0x0540 +#define MT6392_DIGLDO_CON41 0x0546 +#define MT6392_DIGLDO_CON44 0x054C +#define MT6392_DIGLDO_CON47 0x0552 +#define MT6392_DIGLDO_CON48 0x0554 +#define MT6392_DIGLDO_CON49 0x0556 +#define MT6392_DIGLDO_CON50 0x0558 +#define MT6392_DIGLDO_CON51 0x055A +#define MT6392_DIGLDO_CON52 0x055C +#define MT6392_DIGLDO_CON53 0x055E +#define MT6392_DIGLDO_CON54 0x0560 +#define MT6392_DIGLDO_CON55 0x0562 +#define MT6392_DIGLDO_CON56 0x0564 +#define MT6392_DIGLDO_CON57 0x0566 +#define MT6392_DIGLDO_CON58 0x0568 +#define MT6392_DIGLDO_CON59 0x056A +#define MT6392_DIGLDO_CON60 0x056C +#define MT6392_DIGLDO_CON61 0x056E +#define MT6392_DIGLDO_CON62 0x0570 +#define MT6392_DIGLDO_CON63 0x0572 +#define MT6392_EFUSE_CON0 0x0600 +#define MT6392_EFUSE_CON1 0x0602 +#define MT6392_EFUSE_CON2 0x0604 +#define MT6392_EFUSE_CON3 0x0606 +#define MT6392_EFUSE_CON4 0x0608 +#define MT6392_EFUSE_CON5 0x060A +#define MT6392_EFUSE_CON6 0x060C +#define MT6392_EFUSE_VAL_0_15 0x060E +#define MT6392_EFUSE_VAL_16_31 0x0610 +#define MT6392_EFUSE_VAL_32_47 0x0612 +#define MT6392_EFUSE_VAL_48_63 0x0614 +#define MT6392_EFUSE_VAL_64_79 0x0616 +#define MT6392_EFUSE_VAL_80_95 0x0618 +#define MT6392_EFUSE_VAL_96_111 0x061A +#define MT6392_EFUSE_VAL_112_127 0x061C +#define MT6392_EFUSE_VAL_128_143 0x061E +#define MT6392_EFUSE_VAL_144_159 0x0620 +#define MT6392_EFUSE_VAL_160_175 0x0622 +#define MT6392_EFUSE_VAL_176_191 0x0624 +#define MT6392_EFUSE_VAL_192_207 0x0626 +#define MT6392_EFUSE_VAL_208_223 0x0628 +#define MT6392_EFUSE_VAL_224_239 0x062A +#define MT6392_EFUSE_VAL_240_255 0x062C +#define MT6392_EFUSE_VAL_256_271 0x062E +#define MT6392_EFUSE_VAL_272_287 0x0630 +#define MT6392_EFUSE_VAL_288_303 0x0632 +#define MT6392_EFUSE_VAL_304_319 0x0634 +#define MT6392_EFUSE_VAL_320_335 0x0636 +#define MT6392_EFUSE_VAL_336_351 0x0638 +#define MT6392_EFUSE_VAL_352_367 0x063A +#define MT6392_EFUSE_VAL_368_383 0x063C +#define MT6392_EFUSE_VAL_384_399 0x063E +#define MT6392_EFUSE_VAL_400_415 0x0640 +#define MT6392_EFUSE_VAL_416_431 0x0642 +#define MT6392_RTC_MIX_CON0 0x0644 +#define MT6392_RTC_MIX_CON1 0x0646 +#define MT6392_EFUSE_VAL_432_447 0x0648 +#define MT6392_EFUSE_VAL_448_463 0x064A +#define MT6392_EFUSE_VAL_464_479 0x064C +#define MT6392_EFUSE_VAL_480_495 0x064E +#define MT6392_EFUSE_VAL_496_511 0x0650 +#define MT6392_EFUSE_DOUT_0_15 0x0652 +#define MT6392_EFUSE_DOUT_16_31 0x0654 +#define MT6392_EFUSE_DOUT_32_47 0x0656 +#define MT6392_EFUSE_DOUT_48_63 0x0658 +#define MT6392_EFUSE_DOUT_64_79 0x065A +#define MT6392_EFUSE_DOUT_80_95 0x065C +#define MT6392_EFUSE_DOUT_96_111 0x065E +#define MT6392_EFUSE_DOUT_112_127 0x0660 +#define MT6392_EFUSE_DOUT_128_143 0x0662 +#define MT6392_EFUSE_DOUT_144_159 0x0664 +#define MT6392_EFUSE_DOUT_160_175 0x0666 +#define MT6392_EFUSE_DOUT_176_191 0x0668 +#define MT6392_EFUSE_DOUT_192_207 0x066A +#define MT6392_EFUSE_DOUT_208_223 0x066C +#define MT6392_EFUSE_DOUT_224_239 0x066E +#define MT6392_EFUSE_DOUT_240_255 0x0670 +#define MT6392_EFUSE_DOUT_256_271 0x0672 +#define MT6392_EFUSE_DOUT_272_287 0x0674 +#define MT6392_EFUSE_DOUT_288_303 0x0676 +#define MT6392_EFUSE_DOUT_304_319 0x0678 +#define MT6392_EFUSE_DOUT_320_335 0x067A +#define MT6392_EFUSE_DOUT_336_351 0x067C +#define MT6392_EFUSE_DOUT_352_367 0x067E +#define MT6392_EFUSE_DOUT_368_383 0x0680 +#define MT6392_EFUSE_DOUT_384_399 0x0682 +#define MT6392_EFUSE_DOUT_400_415 0x0684 +#define MT6392_EFUSE_DOUT_416_431 0x0686 +#define MT6392_EFUSE_DOUT_432_447 0x0688 +#define MT6392_EFUSE_DOUT_448_463 0x068A +#define MT6392_EFUSE_DOUT_464_479 0x068C +#define MT6392_EFUSE_DOUT_480_495 0x068E +#define MT6392_EFUSE_DOUT_496_511 0x0690 +#define MT6392_EFUSE_CON7 0x0692 +#define MT6392_EFUSE_CON8 0x0694 +#define MT6392_EFUSE_CON9 0x0696 +#define MT6392_AUXADC_ADC0 0x0700 +#define MT6392_AUXADC_ADC1 0x0702 +#define MT6392_AUXADC_ADC2 0x0704 +#define MT6392_AUXADC_ADC3 0x0706 +#define MT6392_AUXADC_ADC4 0x0708 +#define MT6392_AUXADC_ADC5 0x070A +#define MT6392_AUXADC_ADC6 0x070C +#define MT6392_AUXADC_ADC7 0x070E +#define MT6392_AUXADC_ADC8 0x0710 +#define MT6392_AUXADC_ADC9 0x0712 +#define MT6392_AUXADC_ADC10 0x0714 +#define MT6392_AUXADC_ADC11 0x0716 +#define MT6392_AUXADC_ADC12 0x0718 +#define MT6392_AUXADC_ADC13 0x071A +#define MT6392_AUXADC_ADC14 0x071C +#define MT6392_AUXADC_ADC15 0x071E +#define MT6392_AUXADC_ADC16 0x0720 +#define MT6392_AUXADC_ADC17 0x0722 +#define MT6392_AUXADC_ADC18 0x0724 +#define MT6392_AUXADC_ADC19 0x0726 +#define MT6392_AUXADC_ADC20 0x0728 +#define MT6392_AUXADC_ADC21 0x072A +#define MT6392_AUXADC_ADC22 0x072C +#define MT6392_AUXADC_STA0 0x072E +#define MT6392_AUXADC_STA1 0x0730 +#define MT6392_AUXADC_RQST0 0x0732 +#define MT6392_AUXADC_RQST0_SET 0x0734 +#define MT6392_AUXADC_RQST0_CLR 0x0736 +#define MT6392_AUXADC_CON0 0x0738 +#define MT6392_AUXADC_CON0_SET 0x073A +#define MT6392_AUXADC_CON0_CLR 0x073C +#define MT6392_AUXADC_CON1 0x073E +#define MT6392_AUXADC_CON2 0x0740 +#define MT6392_AUXADC_CON3 0x0742 +#define MT6392_AUXADC_CON4 0x0744 +#define MT6392_AUXADC_CON5 0x0746 +#define MT6392_AUXADC_CON6 0x0748 +#define MT6392_AUXADC_CON7 0x074A +#define MT6392_AUXADC_CON8 0x074C +#define MT6392_AUXADC_CON9 0x074E +#define MT6392_AUXADC_CON10 0x0750 +#define MT6392_AUXADC_CON11 0x0752 +#define MT6392_AUXADC_CON12 0x0754 +#define MT6392_AUXADC_CON13 0x0756 +#define MT6392_AUXADC_CON14 0x0758 +#define MT6392_AUXADC_CON15 0x075A +#define MT6392_AUXADC_CON16 0x075C +#define MT6392_AUXADC_AUTORPT0 0x075E +#define MT6392_AUXADC_LBAT0 0x0760 +#define MT6392_AUXADC_LBAT1 0x0762 +#define MT6392_AUXADC_LBAT2 0x0764 +#define MT6392_AUXADC_LBAT3 0x0766 +#define MT6392_AUXADC_LBAT4 0x0768 +#define MT6392_AUXADC_LBAT5 0x076A +#define MT6392_AUXADC_LBAT6 0x076C +#define MT6392_AUXADC_THR0 0x076E +#define MT6392_AUXADC_THR1 0x0770 +#define MT6392_AUXADC_THR2 0x0772 +#define MT6392_AUXADC_THR3 0x0774 +#define MT6392_AUXADC_THR4 0x0776 +#define MT6392_AUXADC_THR5 0x0778 +#define MT6392_AUXADC_THR6 0x077A +#define MT6392_AUXADC_EFUSE0 0x077C +#define MT6392_AUXADC_EFUSE1 0x077E +#define MT6392_AUXADC_EFUSE2 0x0780 +#define MT6392_AUXADC_EFUSE3 0x0782 +#define MT6392_AUXADC_EFUSE4 0x0784 +#define MT6392_AUXADC_EFUSE5 0x0786 +#define MT6392_AUXADC_NAG_0 0x0788 +#define MT6392_AUXADC_NAG_1 0x078A +#define MT6392_AUXADC_NAG_2 0x078C +#define MT6392_AUXADC_NAG_3 0x078E +#define MT6392_AUXADC_NAG_4 0x0790 +#define MT6392_AUXADC_NAG_5 0x0792 +#define MT6392_AUXADC_NAG_6 0x0794 +#define MT6392_AUXADC_NAG_7 0x0796 +#define MT6392_AUXADC_NAG_8 0x0798 +#define MT6392_AUXADC_TYPEC_H_1 0x079A +#define MT6392_AUXADC_TYPEC_H_2 0x079C +#define MT6392_AUXADC_TYPEC_H_3 0x079E +#define MT6392_AUXADC_TYPEC_H_4 0x07A0 +#define MT6392_AUXADC_TYPEC_H_5 0x07A2 +#define MT6392_AUXADC_TYPEC_H_6 0x07A4 +#define MT6392_AUXADC_TYPEC_H_7 0x07A6 +#define MT6392_AUXADC_TYPEC_L_1 0x07A8 +#define MT6392_AUXADC_TYPEC_L_2 0x07AA +#define MT6392_AUXADC_TYPEC_L_3 0x07AC +#define MT6392_AUXADC_TYPEC_L_4 0x07AE +#define MT6392_AUXADC_TYPEC_L_5 0x07B0 +#define MT6392_AUXADC_TYPEC_L_6 0x07B2 +#define MT6392_AUXADC_TYPEC_L_7 0x07B4 +#define MT6392_AUXADC_NAG_9 0x07B6 +#define MT6392_TYPE_C_PHY_RG_0 0x0800 +#define MT6392_TYPE_C_PHY_RG_CC_RESERVE_CSR 0x0802 +#define MT6392_TYPE_C_VCMP_CTRL 0x0804 +#define MT6392_TYPE_C_CTRL 0x0806 +#define MT6392_TYPE_C_CC_SW_CTRL 0x080a +#define MT6392_TYPE_C_CC_VOL_PERIODIC_MEAS_VAL 0x080c +#define MT6392_TYPE_C_CC_VOL_DEBOUNCE_CNT_VAL 0x080e +#define MT6392_TYPE_C_DRP_SRC_CNT_VAL_0 0x0810 +#define MT6392_TYPE_C_DRP_SNK_CNT_VAL_0 0x0814 +#define MT6392_TYPE_C_DRP_TRY_CNT_VAL_0 0x0818 +#define MT6392_TYPE_C_CC_SRC_DEFAULT_DAC_VAL 0x0820 +#define MT6392_TYPE_C_CC_SRC_15_DAC_VAL 0x0822 +#define MT6392_TYPE_C_CC_SRC_30_DAC_VAL 0x0824 +#define MT6392_TYPE_C_CC_SNK_DAC_VAL_0 0x0828 +#define MT6392_TYPE_C_CC_SNK_DAC_VAL_1 0x082a +#define MT6392_TYPE_C_INTR_EN_0 0x0830 +#define MT6392_TYPE_C_INTR_EN_2 0x0834 +#define MT6392_TYPE_C_INTR_0 0x0838 +#define MT6392_TYPE_C_INTR_2 0x083C +#define MT6392_TYPE_C_CC_STATUS 0x0840 +#define MT6392_TYPE_C_PWR_STATUS 0x0842 +#define MT6392_TYPE_C_PHY_RG_CC1_RESISTENCE_0 0x0844 +#define MT6392_TYPE_C_PHY_RG_CC1_RESISTENCE_1 0x0846 +#define MT6392_TYPE_C_PHY_RG_CC2_RESISTENCE_0 0x0848 +#define MT6392_TYPE_C_PHY_RG_CC2_RESISTENCE_1 0x084a +#define MT6392_TYPE_C_CC_SW_FORCE_MODE_ENABLE_0 0x0860 +#define MT6392_TYPE_C_CC_SW_FORCE_MODE_VAL_0 0x0864 +#define MT6392_TYPE_C_CC_SW_FORCE_MODE_VAL_1 0x0866 +#define MT6392_TYPE_C_CC_SW_FORCE_MODE_ENABLE_1 0x0868 +#define MT6392_TYPE_C_CC_SW_FORCE_MODE_VAL_2 0x086c +#define MT6392_TYPE_C_CC_DAC_CALI_CTRL 0x0870 +#define MT6392_TYPE_C_CC_DAC_CALI_RESULT 0x0872 +#define MT6392_TYPE_C_DEBUG_PORT_SELECT_0 0x0880 +#define MT6392_TYPE_C_DEBUG_PORT_SELECT_1 0x0882 +#define MT6392_TYPE_C_DEBUG_MODE_SELECT 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Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Fabien Parent , Val Packett , Luca Leonardo Scorcia , Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , AngeloGioacchino Del Regno , Liam Girdwood , Mark Brown , Louis-Alexis Eyraud , Julien Massot , Gary Bisson , Chen Zhong , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 5/7] regulator: mt6392: Add support for MT6392 regulator Date: Fri, 6 Mar 2026 12:03:09 +0000 Message-ID: <20260306120521.163654-6-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260306120521.163654-1-l.scorcia@gmail.com> References: <20260306120521.163654-1-l.scorcia@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fabien Parent The MT6392 is a regulator found on boards based on the MediaTek MT8167, MT8516, and probably other SoCs. It is a so called PMIC and connects as a slave to a SoC using SPI, wrapped inside PWRAP. Signed-off-by: Fabien Parent Co-developed-by: Val Packett Signed-off-by: Val Packett Signed-off-by: Luca Leonardo Scorcia --- drivers/regulator/Kconfig | 9 + drivers/regulator/Makefile | 1 + drivers/regulator/mt6392-regulator.c | 491 +++++++++++++++++++++ include/linux/regulator/mt6392-regulator.h | 40 ++ 4 files changed, 541 insertions(+) create mode 100644 drivers/regulator/mt6392-regulator.c create mode 100644 include/linux/regulator/mt6392-regulator.h diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index d2335276cce5..66876d730807 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -991,6 +991,15 @@ config REGULATOR_MT6380 This driver supports the control of different power rails of device through regulator interface. =20 +config REGULATOR_MT6392 + tristate "MediaTek MT6392 PMIC" + depends on MFD_MT6397 + help + Say y here to select this option to enable the power regulator of + MediaTek MT6392 PMIC. + This driver supports the control of different power rails of device + through regulator interface. + config REGULATOR_MT6397 tristate "MediaTek MT6397 PMIC" depends on MFD_MT6397 diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 1beba1493241..db5145cfcf36 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -117,6 +117,7 @@ obj-$(CONFIG_REGULATOR_MT6360) +=3D mt6360-regulator.o obj-$(CONFIG_REGULATOR_MT6363) +=3D mt6363-regulator.o obj-$(CONFIG_REGULATOR_MT6370) +=3D mt6370-regulator.o obj-$(CONFIG_REGULATOR_MT6380) +=3D mt6380-regulator.o +obj-$(CONFIG_REGULATOR_MT6392) +=3D mt6392-regulator.o obj-$(CONFIG_REGULATOR_MT6397) +=3D mt6397-regulator.o obj-$(CONFIG_REGULATOR_MTK_DVFSRC) +=3D mtk-dvfsrc-regulator.o obj-$(CONFIG_REGULATOR_QCOM_LABIBB) +=3D qcom-labibb-regulator.o diff --git a/drivers/regulator/mt6392-regulator.c b/drivers/regulator/mt639= 2-regulator.c new file mode 100644 index 000000000000..1c0e9bccfe86 --- /dev/null +++ b/drivers/regulator/mt6392-regulator.c @@ -0,0 +1,491 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. +// Copyright (c) 2020 BayLibre, SAS. +// Author: Chen Zhong +// Author: Fabien Parent +// +// Based on mt6397-regulator.c + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MT6392_BUCK_MODE_AUTO 0 +#define MT6392_BUCK_MODE_FORCE_PWM 1 +#define MT6392_LDO_MODE_NORMAL 0 +#define MT6392_LDO_MODE_LP 1 + +/* + * MT6392 regulators' information + * + * @desc: standard fields of regulator description. + * @qi: Mask for query enable signal status of regulators + * @vselon_reg: Register sections for hardware control mode of bucks + * @vselctrl_reg: Register for controlling the buck control mode. + * @vselctrl_mask: Mask for query buck's voltage control mode. + */ +struct mt6392_regulator_info { + struct regulator_desc desc; + u32 qi; + u32 vselon_reg; + u32 vselctrl_reg; + u32 vselctrl_mask; + u32 modeset_reg; + u32 modeset_mask; +}; + +#define MT6392_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \ + vosel, vosel_mask, voselon, vosel_ctrl, \ + _modeset_reg, _modeset_mask, rampdelay) \ +[MT6392_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6392_volt_range_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6392_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D (max - min)/step + 1, \ + .linear_ranges =3D volt_ranges, \ + .n_linear_ranges =3D ARRAY_SIZE(volt_ranges), \ + .vsel_reg =3D vosel, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(0), \ + .ramp_delay =3D rampdelay, \ + }, \ + .qi =3D BIT(13), \ + .vselon_reg =3D voselon, \ + .vselctrl_reg =3D vosel_ctrl, \ + .vselctrl_mask =3D BIT(1), \ + .modeset_reg =3D _modeset_reg, \ + .modeset_mask =3D _modeset_mask, \ +} + +#define MT6392_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ + vosel_mask, _modeset_reg, _modeset_mask, entime) \ +[MT6392_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6392_volt_table_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6392_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D ARRAY_SIZE(ldo_volt_table), \ + .volt_table =3D ldo_volt_table, \ + .vsel_reg =3D vosel, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + .enable_time =3D entime, \ + }, \ + .qi =3D BIT(15), \ + .modeset_reg =3D _modeset_reg, \ + .modeset_mask =3D _modeset_mask, \ +} + +#define MT6392_LDO_LINEAR(match, vreg, min, max, step, volt_ranges, \ + enreg, enbit, vosel, vosel_mask, _modeset_reg, \ + _modeset_mask, entime) \ +[MT6392_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6392_volt_ldo_range_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6392_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D (max - min)/step + 1, \ + .linear_ranges =3D volt_ranges, \ + .n_linear_ranges =3D ARRAY_SIZE(volt_ranges), \ + .vsel_reg =3D vosel, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + .enable_time =3D entime, \ + }, \ + .qi =3D BIT(15), \ + .modeset_reg =3D _modeset_reg, \ + .modeset_mask =3D _modeset_mask, \ +} + +#define MT6392_REG_FIXED(match, vreg, enreg, enbit, volt, \ + _modeset_reg, _modeset_mask, entime) \ +[MT6392_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6392_volt_fixed_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6392_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D 1, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + .enable_time =3D entime, \ + .min_uV =3D volt, \ + }, \ + .qi =3D BIT(15), \ + .modeset_reg =3D _modeset_reg, \ + .modeset_mask =3D _modeset_mask, \ +} + +#define MT6392_REG_FIXED_NO_MODE(match, vreg, enreg, enbit, volt, \ + entime) \ +[MT6392_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6392_volt_fixed_no_mode_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6392_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D 1, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + .enable_time =3D entime, \ + .min_uV =3D volt, \ + }, \ + .qi =3D BIT(15), \ +} + +static const struct linear_range buck_volt_range1[] =3D { + REGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250), +}; + +static const struct linear_range buck_volt_range2[] =3D { + REGULATOR_LINEAR_RANGE(1400000, 0, 0x7f, 12500), +}; + +static const u32 ldo_volt_table1[] =3D { + 1800000, 1900000, 2000000, 2200000, +}; + +static const struct linear_range ldo_volt_range2[] =3D { + REGULATOR_LINEAR_RANGE(3300000, 0, 3, 100000), +}; + +static const u32 ldo_volt_table3[] =3D { + 1800000, 3300000, +}; + +static const u32 ldo_volt_table4[] =3D { + 3000000, 3300000, +}; + +static const u32 ldo_volt_table5[] =3D { + 1200000, 1300000, 1500000, 1800000, 2000000, 2800000, 3000000, 3300000, +}; + +static const u32 ldo_volt_table6[] =3D { + 1240000, 1390000, +}; + +static const u32 ldo_volt_table7[] =3D { + 1200000, 1300000, 1500000, 1800000, +}; + +static const u32 ldo_volt_table8[] =3D { + 1800000, 2000000, +}; + +static int mt6392_buck_set_mode(struct regulator_dev *rdev, unsigned int m= ode) +{ + int ret, val =3D 0; + struct mt6392_regulator_info *info =3D rdev_get_drvdata(rdev); + + switch (mode) { + case REGULATOR_MODE_FAST: + val =3D MT6392_BUCK_MODE_FORCE_PWM; + break; + case REGULATOR_MODE_NORMAL: + val =3D MT6392_BUCK_MODE_AUTO; + break; + default: + return -EINVAL; + } + + val <<=3D ffs(info->modeset_mask) - 1; + + ret =3D regmap_update_bits(rdev->regmap, info->modeset_reg, + info->modeset_mask, val); + + return ret; +} + +static unsigned int mt6392_buck_get_mode(struct regulator_dev *rdev) +{ + unsigned int val; + unsigned int mode; + int ret; + struct mt6392_regulator_info *info =3D rdev_get_drvdata(rdev); + + ret =3D regmap_read(rdev->regmap, info->modeset_reg, &val); + if (ret < 0) + return ret; + + val &=3D info->modeset_mask; + val >>=3D ffs(info->modeset_mask) - 1; + + if (val & 0x1) + mode =3D REGULATOR_MODE_FAST; + else + mode =3D REGULATOR_MODE_NORMAL; + + return mode; +} + +static int mt6392_ldo_set_mode(struct regulator_dev *rdev, unsigned int mo= de) +{ + int ret, val =3D 0; + struct mt6392_regulator_info *info =3D rdev_get_drvdata(rdev); + + switch (mode) { + case REGULATOR_MODE_STANDBY: + val =3D MT6392_LDO_MODE_LP; + break; + case REGULATOR_MODE_NORMAL: + val =3D MT6392_LDO_MODE_NORMAL; + break; + default: + return -EINVAL; + } + + val <<=3D ffs(info->modeset_mask) - 1; + + ret =3D regmap_update_bits(rdev->regmap, info->modeset_reg, + info->modeset_mask, val); + + return ret; +} + +static unsigned int mt6392_ldo_get_mode(struct regulator_dev *rdev) +{ + unsigned int val; + unsigned int mode; + int ret; + struct mt6392_regulator_info *info =3D rdev_get_drvdata(rdev); + + ret =3D regmap_read(rdev->regmap, info->modeset_reg, &val); + if (ret < 0) + return ret; + + val &=3D info->modeset_mask; + val >>=3D ffs(info->modeset_mask) - 1; + + if (val & 0x1) + mode =3D REGULATOR_MODE_STANDBY; + else + mode =3D REGULATOR_MODE_NORMAL; + + return mode; +} + +static const struct regulator_ops mt6392_volt_range_ops =3D { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .set_mode =3D mt6392_buck_set_mode, + .get_mode =3D mt6392_buck_get_mode, +}; + +static const struct regulator_ops mt6392_volt_table_ops =3D { + .list_voltage =3D regulator_list_voltage_table, + .map_voltage =3D regulator_map_voltage_iterate, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .set_mode =3D mt6392_ldo_set_mode, + .get_mode =3D mt6392_ldo_get_mode, +}; + +static const struct regulator_ops mt6392_volt_ldo_range_ops =3D { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .set_mode =3D mt6392_ldo_set_mode, + .get_mode =3D mt6392_ldo_get_mode, +}; + +static const struct regulator_ops mt6392_volt_fixed_ops =3D { + .list_voltage =3D regulator_list_voltage_linear, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .set_mode =3D mt6392_ldo_set_mode, + .get_mode =3D mt6392_ldo_get_mode, +}; + +static const struct regulator_ops mt6392_volt_fixed_no_mode_ops =3D { + .list_voltage =3D regulator_list_voltage_linear, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, +}; + +/* The array is indexed by id(MT6392_ID_XXX) */ +static struct mt6392_regulator_info mt6392_regulators[] =3D { + MT6392_BUCK("buck_vproc", VPROC, 700000, 1493750, 6250, + buck_volt_range1, MT6392_VPROC_CON7, MT6392_VPROC_CON9, 0x7f, + MT6392_VPROC_CON10, MT6392_VPROC_CON5, MT6392_VPROC_CON2, + 0x100, 12500), + MT6392_BUCK("buck_vsys", VSYS, 1400000, 2987500, 12500, + buck_volt_range2, MT6392_VSYS_CON7, MT6392_VSYS_CON9, 0x7f, + MT6392_VSYS_CON10, MT6392_VSYS_CON5, MT6392_VSYS_CON2, 0x100, + 25000), + MT6392_BUCK("buck_vcore", VCORE, 700000, 1493750, 6250, + buck_volt_range1, MT6392_VCORE_CON7, MT6392_VCORE_CON9, 0x7f, + MT6392_VCORE_CON10, MT6392_VCORE_CON5, MT6392_VCORE_CON2, + 0x100, 12500), + MT6392_REG_FIXED("ldo_vxo22", VXO22, MT6392_ANALDO_CON1, 10, 2200000, + MT6392_ANALDO_CON1, 0x2, 110), + MT6392_LDO("ldo_vaud22", VAUD22, ldo_volt_table1, + MT6392_ANALDO_CON2, 14, MT6392_ANALDO_CON8, 0x60, + MT6392_ANALDO_CON2, 0x2, 264), + MT6392_REG_FIXED_NO_MODE("ldo_vcama", VCAMA, MT6392_ANALDO_CON4, 15, + 2800000, 264), + MT6392_REG_FIXED("ldo_vaud28", VAUD28, MT6392_ANALDO_CON23, 14, 2800000, + MT6392_ANALDO_CON23, 0x2, 264), + MT6392_REG_FIXED("ldo_vadc18", VADC18, MT6392_ANALDO_CON25, 14, 1800000, + MT6392_ANALDO_CON25, 0x2, 264), + MT6392_LDO_LINEAR("ldo_vcn35", VCN35, 3300000, 3600000, 100000, + ldo_volt_range2, MT6392_ANALDO_CON21, 12, MT6392_ANALDO_CON16, + 0xC, MT6392_ANALDO_CON21, 0x2, 264), + MT6392_REG_FIXED("ldo_vio28", VIO28, MT6392_DIGLDO_CON0, 14, 2800000, + MT6392_DIGLDO_CON0, 0x2, 264), + MT6392_REG_FIXED("ldo_vusb", VUSB, MT6392_DIGLDO_CON2, 14, 3300000, + MT6392_DIGLDO_CON2, 0x2, 264), + MT6392_LDO("ldo_vmc", VMC, ldo_volt_table3, + MT6392_DIGLDO_CON3, 12, MT6392_DIGLDO_CON24, 0x10, + MT6392_DIGLDO_CON3, 0x2, 264), + MT6392_LDO("ldo_vmch", VMCH, ldo_volt_table4, + MT6392_DIGLDO_CON5, 14, MT6392_DIGLDO_CON26, 0x80, + MT6392_DIGLDO_CON5, 0x2, 264), + MT6392_LDO("ldo_vemc3v3", VEMC3V3, ldo_volt_table4, + MT6392_DIGLDO_CON6, 14, MT6392_DIGLDO_CON27, 0x80, + MT6392_DIGLDO_CON6, 0x2, 264), + MT6392_LDO("ldo_vgp1", VGP1, ldo_volt_table5, + MT6392_DIGLDO_CON7, 15, MT6392_DIGLDO_CON28, 0xE0, + MT6392_DIGLDO_CON7, 0x2, 264), + MT6392_LDO("ldo_vgp2", VGP2, ldo_volt_table5, + MT6392_DIGLDO_CON8, 15, MT6392_DIGLDO_CON29, 0xE0, + MT6392_DIGLDO_CON8, 0x2, 264), + MT6392_REG_FIXED("ldo_vcn18", VCN18, MT6392_DIGLDO_CON11, 14, 1800000, + MT6392_DIGLDO_CON11, 0x2, 264), + MT6392_LDO("ldo_vcamaf", VCAMAF, ldo_volt_table5, + MT6392_DIGLDO_CON31, 15, MT6392_DIGLDO_CON32, 0xE0, + MT6392_DIGLDO_CON31, 0x2, 264), + MT6392_LDO("ldo_vm", VM, ldo_volt_table6, + MT6392_DIGLDO_CON47, 14, MT6392_DIGLDO_CON48, 0x30, + MT6392_DIGLDO_CON47, 0x2, 264), + MT6392_REG_FIXED("ldo_vio18", VIO18, MT6392_DIGLDO_CON49, 14, 1800000, + MT6392_DIGLDO_CON49, 0x2, 264), + MT6392_LDO("ldo_vcamd", VCAMD, ldo_volt_table7, + MT6392_DIGLDO_CON51, 14, MT6392_DIGLDO_CON52, 0x60, + MT6392_DIGLDO_CON51, 0x2, 264), + MT6392_REG_FIXED("ldo_vcamio", VCAMIO, MT6392_DIGLDO_CON53, 14, 1800000, + MT6392_DIGLDO_CON53, 0x2, 264), + MT6392_REG_FIXED("ldo_vm25", VM25, MT6392_DIGLDO_CON55, 14, 2500000, + MT6392_DIGLDO_CON55, 0x2, 264), + MT6392_LDO("ldo_vefuse", VEFUSE, ldo_volt_table8, + MT6392_DIGLDO_CON57, 14, MT6392_DIGLDO_CON58, 0x10, + MT6392_DIGLDO_CON57, 0x2, 264), +}; + +static int mt6392_set_buck_vosel_reg(struct platform_device *pdev) +{ + struct mt6397_chip *mt6392 =3D dev_get_drvdata(pdev->dev.parent); + int i; + u32 regval; + + for (i =3D 0; i < MT6392_MAX_REGULATOR; i++) { + if (mt6392_regulators[i].vselctrl_reg) { + if (regmap_read(mt6392->regmap, + mt6392_regulators[i].vselctrl_reg, + ®val) < 0) { + dev_err(&pdev->dev, + "Failed to read buck ctrl\n"); + return -EIO; + } + + if (regval & mt6392_regulators[i].vselctrl_mask) { + mt6392_regulators[i].desc.vsel_reg =3D + mt6392_regulators[i].vselon_reg; + } + } + } + + return 0; +} + +static int mt6392_regulator_probe(struct platform_device *pdev) +{ + struct mt6397_chip *mt6392 =3D dev_get_drvdata(pdev->dev.parent); + struct regulator_config config =3D {}; + struct regulator_dev *rdev; + int i; + + /* Query buck controller to select activated voltage register part */ + if (mt6392_set_buck_vosel_reg(pdev)) + return -EIO; + + for (i =3D 0; i < MT6392_MAX_REGULATOR; i++) { + config.dev =3D &pdev->dev; + config.driver_data =3D &mt6392_regulators[i]; + config.regmap =3D mt6392->regmap; + + rdev =3D devm_regulator_register(&pdev->dev, + &mt6392_regulators[i].desc, + &config); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register %s\n", + mt6392_regulators[i].desc.name); + return PTR_ERR(rdev); + } + } + + return 0; +} + +static const struct platform_device_id mt6392_platform_ids[] =3D { + {"mt6392-regulator", 0}, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(platform, mt6392_platform_ids); + +static struct platform_driver mt6392_regulator_driver =3D { + .driver =3D { + .name =3D "mt6392-regulator", + }, + .probe =3D mt6392_regulator_probe, + .id_table =3D mt6392_platform_ids, +}; + +module_platform_driver(mt6392_regulator_driver); + +MODULE_AUTHOR("Chen Zhong "); +MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6392 PMIC"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/regulator/mt6392-regulator.h b/include/linux/reg= ulator/mt6392-regulator.h new file mode 100644 index 000000000000..dfcbcacb5ad4 --- /dev/null +++ b/include/linux/regulator/mt6392-regulator.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Chen Zhong + */ + +#ifndef __LINUX_REGULATOR_MT6392_H +#define __LINUX_REGULATOR_MT6392_H + +enum { + MT6392_ID_VPROC =3D 0, + MT6392_ID_VSYS, + MT6392_ID_VCORE, + MT6392_ID_VXO22, + MT6392_ID_VAUD22, + MT6392_ID_VCAMA, + MT6392_ID_VAUD28, + MT6392_ID_VADC18, + MT6392_ID_VCN35, + MT6392_ID_VIO28, + MT6392_ID_VUSB =3D 10, + MT6392_ID_VMC, + MT6392_ID_VMCH, + MT6392_ID_VEMC3V3, + MT6392_ID_VGP1, + MT6392_ID_VGP2, + MT6392_ID_VCN18, + MT6392_ID_VCAMAF, + MT6392_ID_VM, + MT6392_ID_VIO18, + MT6392_ID_VCAMD, + MT6392_ID_VCAMIO, + MT6392_ID_VM25, + MT6392_ID_VEFUSE, + MT6392_ID_RG_MAX, +}; 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Fri, 06 Mar 2026 04:06:56 -0800 (PST) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Val Packett , Luca Leonardo Scorcia , Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , AngeloGioacchino Del Regno , Liam Girdwood , Mark Brown , Louis-Alexis Eyraud , Gary Bisson , Julien Massot , Fabien Parent , Chen Zhong , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 6/7] input: keyboard: mtk-pmic-keys: add MT6392 support Date: Fri, 6 Mar 2026 12:03:10 +0000 Message-ID: <20260306120521.163654-7-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260306120521.163654-1-l.scorcia@gmail.com> References: <20260306120521.163654-1-l.scorcia@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Val Packett Add support for the MT6392 PMIC to the keys driver. Signed-off-by: Val Packett Signed-off-by: Luca Leonardo Scorcia Acked-by: Dmitry Torokhov --- drivers/input/keyboard/mtk-pmic-keys.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/input/keyboard/mtk-pmic-keys.c b/drivers/input/keyboar= d/mtk-pmic-keys.c index c78d9f6d97c4..3b9a5b6bc470 100644 --- a/drivers/input/keyboard/mtk-pmic-keys.c +++ b/drivers/input/keyboard/mtk-pmic-keys.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -69,6 +70,17 @@ static const struct mtk_pmic_regs mt6397_regs =3D { .rst_lprst_mask =3D MTK_PMIC_RST_DU_MASK, }; =20 +static const struct mtk_pmic_regs mt6392_regs =3D { + .keys_regs[MTK_PMIC_PWRKEY_INDEX] =3D + MTK_PMIC_KEYS_REGS(MT6392_CHRSTATUS, + 0x2, MT6392_INT_MISC_CON, 0x10, MTK_PMIC_PWRKEY_RST), + .keys_regs[MTK_PMIC_HOMEKEY_INDEX] =3D + MTK_PMIC_KEYS_REGS(MT6392_CHRSTATUS, + 0x4, MT6392_INT_MISC_CON, 0x8, MTK_PMIC_HOMEKEY_RST), + .pmic_rst_reg =3D MT6392_TOP_RST_MISC, + .rst_lprst_mask =3D MTK_PMIC_RST_DU_MASK, +}; + static const struct mtk_pmic_regs mt6323_regs =3D { .keys_regs[MTK_PMIC_PWRKEY_INDEX] =3D MTK_PMIC_KEYS_REGS(MT6323_CHRSTATUS, @@ -301,6 +313,9 @@ static const struct of_device_id of_mtk_pmic_keys_match= _tbl[] =3D { { .compatible =3D "mediatek,mt6397-keys", .data =3D &mt6397_regs, + }, { + .compatible =3D "mediatek,mt6392-keys", + .data =3D &mt6392_regs, }, { .compatible =3D "mediatek,mt6323-keys", .data =3D &mt6323_regs, --=20 2.43.0 From nobody Thu Apr 9 18:40:10 2026 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC46438E5C9 for ; Fri, 6 Mar 2026 12:07:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772798831; cv=none; b=HcduqtOlCUer2no7JklncF2LP04ObYPI8LqEL7mc/ZM3t6W/hrC9eVwrts2U2wPhk83z+BRzUbjLUB/1aWxQL+x+h8cFEQX8bUI+ojazp6fSZePcoVWCDcb81PWLaQvV4Vhob7F1eqxqX5EaxgK/Q/3/TeHyU8Pt2iKbamNGajI= ARC-Message-Signature: i=1; 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Fri, 06 Mar 2026 04:07:07 -0800 (PST) Received: from luca-vm.lan ([154.61.61.58]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439dae2b9d8sm3457225f8f.21.2026.03.06.04.07.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 04:07:07 -0800 (PST) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Val Packett , Luca Leonardo Scorcia , Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , AngeloGioacchino Del Regno , Liam Girdwood , Mark Brown , Louis-Alexis Eyraud , Julien Massot , Gary Bisson , Fabien Parent , Chen Zhong , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 7/7] arm64: dts: mt6392: add mt6392 PMIC dtsi Date: Fri, 6 Mar 2026 12:03:11 +0000 Message-ID: <20260306120521.163654-8-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260306120521.163654-1-l.scorcia@gmail.com> References: <20260306120521.163654-1-l.scorcia@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Val Packett Add the dts to be included by all boards using the MT6392 PMIC. Signed-off-by: Val Packett Signed-off-by: Luca Leonardo Scorcia --- arch/arm64/boot/dts/mediatek/mt6392.dtsi | 134 +++++++++++++++++++++++ 1 file changed, 134 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6392.dtsi diff --git a/arch/arm64/boot/dts/mediatek/mt6392.dtsi b/arch/arm64/boot/dts= /mediatek/mt6392.dtsi new file mode 100644 index 000000000000..c7e54c30bc3a --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6392.dtsi @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 MediaTek Inc. + * Copyright (c) 2024 Val Packett + */ + +#include + +&pwrap { + pmic: pmic { + compatible =3D "mediatek,mt6392", "mediatek,mt6323"; + interrupt-controller; + #interrupt-cells =3D <2>; + + regulators { + compatible =3D "mediatek,mt6392-regulator"; + + mt6392_vproc_reg: buck_vproc { + regulator-name =3D "vproc"; + }; + + mt6392_vsys_reg: buck_vsys { + regulator-name =3D "vsys"; + }; + + mt6392_vcore_reg: buck_vcore { + regulator-name =3D "vcore"; + }; + + mt6392_vxo22_reg: ldo_vxo22 { + regulator-name =3D "vxo22"; + }; + + mt6392_vaud22_reg: ldo_vaud22 { + regulator-name =3D "vaud22"; + }; + + mt6392_vcama_reg: ldo_vcama { + regulator-name =3D "vcama"; + }; + + mt6392_vaud28_reg: ldo_vaud28 { + regulator-name =3D "vaud28"; + }; + + mt6392_vadc18_reg: ldo_vadc18 { + regulator-name =3D "vadc18"; + }; + + mt6392_vcn35_reg: ldo_vcn35 { + regulator-name =3D "vcn35"; + }; + + mt6392_vio28_reg: ldo_vio28 { + regulator-name =3D "vio28"; + }; + + mt6392_vusb_reg: ldo_vusb { + regulator-name =3D "vusb"; + }; + + mt6392_vmc_reg: ldo_vmc { + regulator-name =3D "vmc"; + }; + + mt6392_vmch_reg: ldo_vmch { + regulator-name =3D "vmch"; + }; + + mt6392_vemc3v3_reg: ldo_vemc3v3 { + regulator-name =3D "vemc3v3"; + }; + + mt6392_vgp1_reg: ldo_vgp1 { + regulator-name =3D "vgp1"; + }; + + mt6392_vgp2_reg: ldo_vgp2 { + regulator-name =3D "vgp2"; + }; + + mt6392_vcn18_reg: ldo_vcn18 { + regulator-name =3D "vcn18"; + }; + + mt6392_vcamaf_reg: ldo_vcamaf { + regulator-name =3D "vcamaf"; + }; + + mt6392_vm_reg: ldo_vm { + regulator-name =3D "vm"; + }; + + mt6392_vio18_reg: ldo_vio18 { + regulator-name =3D "vio18"; + }; + + mt6392_vcamd_reg: ldo_vcamd { + regulator-name =3D "vcamd"; + }; + + mt6392_vcamio_reg: ldo_vcamio { + regulator-name =3D "vcamio"; + }; + + mt6392_vm25_reg: ldo_vm25 { + regulator-name =3D "vm25"; + }; + + mt6392_vefuse_reg: ldo_vefuse { + regulator-name =3D "vefuse"; + }; + }; + + rtc { + compatible =3D "mediatek,mt6392-rtc", + "mediatek,mt6397-rtc"; + }; + + keys { + compatible =3D "mediatek,mt6392-keys"; + + key-power { + linux,keycodes =3D ; + wakeup-source; + }; + + key-home { + linux,keycodes =3D ; + wakeup-source; + }; + }; + }; +}; --=20 2.43.0