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charset="utf-8" Add device tree nodes for QPIC SPI NAND flash controller support on IPQ5424 SoC. The IPQ5424 SoC includes a QPIC controller that supports SPI NAND flash devices with hardware ECC capabilities and DMA support through BAM (Bus Access Manager). Reviewed-by: Konrad Dybcio Signed-off-by: Md Sadre Alam --- Change in [v6] * No change Change in [v5] * No change Change in [v4] * No change Change in [v3] * Reformatted clocks, clock-names, dmas, and dma-names properties to one entry per line Change in [v2] * No change Change in [v1] * Added qpic_bam node to describe BAM DMA controller * Added spi nand support for IPQ5424 arch/arm64/boot/dts/qcom/ipq5424.dtsi | 33 +++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qc= om/ipq5424.dtsi index eb393f3fd728..f20cda429094 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -572,6 +572,39 @@ sdhc: mmc@7804000 { status =3D "disabled"; }; =20 + qpic_bam: dma-controller@7984000 { + compatible =3D "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg =3D <0x0 0x07984000 0x0 0x1c000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QPIC_AHB_CLK>; + clock-names =3D "bam_clk"; + #dma-cells =3D <1>; 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charset="utf-8" Add device tree nodes for QPIC SPI NAND flash controller support on IPQ5332 SoC. The IPQ5332 SoC includes a QPIC controller that supports SPI NAND flash devices with hardware ECC capabilities and DMA support through BAM (Bus Access Manager). Signed-off-by: Md Sadre Alam Reviewed-by: Konrad Dybcio --- Change in [v6] * No change Change in [v5] * No change Change in [v4] * No change Change in [v3] * Reformatted clocks, clock-names, dmas, and dma-names properties to one entry per line Change in [v2] * No change Change in [v1] * Added qpic_bam node to describe BAM DMA controller * Added spi nand support for IPQ5332 arch/arm64/boot/dts/qcom/ipq5332.dtsi | 33 +++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qc= om/ipq5332.dtsi index 45fc512a3bab..e227730d99a6 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -423,6 +423,39 @@ blsp1_spi2: spi@78b7000 { status =3D "disabled"; }; =20 + qpic_bam: dma-controller@7984000 { + compatible =3D "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg =3D <0x07984000 0x1c000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QPIC_AHB_CLK>; + clock-names =3D "bam_clk"; + #dma-cells =3D <1>; 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charset="utf-8" Enable QPIC SPI NAND flash controller support on the IPQ5424 RDP466 reference design platform. The RDP466 board features a SPI NAND flash device connected to the QPIC controller for primary storage. This patch enables the QPIC BAM DMA controller and SPI NAND interface of QPIC, and configures the necessary pin control settings for proper operation. Reviewed-by: Konrad Dybcio Signed-off-by: Md Sadre Alam --- Change in [v6] * Squash the eMMC removal changes Change in [v5] * No Change Change in [v4] * No Change Change in [v3] * No Change Change in [v2] * Added Reviewed-by tag * Added \n before status in qpic_nand node Change in [v1] * Enable bam and spi nand for ipq5424 arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 44 ++++++++++++++------- 1 file changed, 29 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/= dts/qcom/ipq5424-rdp466.dts index 738618551203..de71b72ae6dc 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -124,13 +124,6 @@ &qusb_phy_1 { status =3D "okay"; }; =20 -&sdhc { - pinctrl-0 =3D <&sdc_default_state>; - pinctrl-names =3D "default"; - - status =3D "okay"; -}; - &sleep_clk { clock-frequency =3D <32000>; }; @@ -201,26 +194,26 @@ mosi-pins { }; }; =20 - sdc_default_state: sdc-default-state { - clk-pins { + qpic_snand_default_state: qpic-snand-default-state { + clock-pins { pins =3D "gpio5"; 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charset="utf-8" Enable QPIC SPI NAND flash controller support on the IPQ5332 reference design platform. Reviewed-by: Konrad Dybcio Signed-off-by: Md Sadre Alam --- Change in [v6] * Squash the eMMC removal changes Change in [v5] * No change Change in [v4] * No change Change in [v3] * Added Reviewed-by tag Change in [v2] * No change Change in [v1] .../boot/dts/qcom/ipq5332-rdp-common.dtsi | 44 +++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts | 34 -------------- 2 files changed, 44 insertions(+), 34 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi b/arch/arm64/= boot/dts/qcom/ipq5332-rdp-common.dtsi index b37ae7749083..8967861be5fd 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi @@ -78,4 +78,48 @@ gpio_leds_default: gpio-leds-default-state { drive-strength =3D <8>; bias-pull-down; }; + + qpic_snand_default_state: qpic-snand-default-state { + clock-pins { + pins =3D "gpio13"; + function =3D "qspi_clk"; + drive-strength =3D <8>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio12"; + function =3D "qspi_cs"; + drive-strength =3D <8>; + bias-disable; + }; + + data-pins { + pins =3D "gpio8", "gpio9", "gpio10", "gpio11"; + function =3D "qspi_data"; + drive-strength =3D <8>; + bias-disable; + }; + }; +}; + +&qpic_bam { + status =3D "okay"; +}; + +&qpic_nand { + pinctrl-0 =3D <&qpic_snand_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; + + flash@0 { + compatible =3D "spi-nand"; + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + nand-ecc-engine =3D <&qpic_nand>; + nand-ecc-strength =3D <4>; + nand-ecc-step-size =3D <512>; + }; }; diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts b/arch/arm64/boot/= dts/qcom/ipq5332-rdp442.dts index ed8a54eb95c0..6e2abde9ed89 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts @@ -35,17 +35,6 @@ flash@0 { }; }; =20 -&sdhc { - bus-width =3D <4>; - max-frequency =3D <192000000>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - pinctrl-0 =3D <&sdc_default_state>; - pinctrl-names =3D "default"; - status =3D "okay"; -}; - &tlmm { i2c_1_pins: i2c-1-state { pins =3D "gpio29", "gpio30"; @@ -54,29 +43,6 @@ i2c_1_pins: i2c-1-state { bias-pull-up; }; =20 - sdc_default_state: sdc-default-state { - clk-pins { - pins =3D "gpio13"; - function =3D "sdc_clk"; - drive-strength =3D <8>; - bias-disable; - }; - - cmd-pins { - pins =3D "gpio12"; - function =3D "sdc_cmd"; - drive-strength =3D <8>; - bias-pull-up; - }; - - data-pins { - pins =3D "gpio8", "gpio9", "gpio10", "gpio11"; - function =3D "sdc_data"; - drive-strength =3D <8>; - bias-pull-up; - }; - }; - spi_0_data_clk_pins: spi-0-data-clk-state { pins =3D "gpio14", "gpio15", "gpio16"; function =3D "blsp0_spi"; --=20 2.34.1