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Shenoy" To: Mario Limonciello , "Rafael J . Wysocki" , Viresh Kumar , K Prateek Nayak CC: , , "Gautham R. Shenoy" Subject: [PATCH 6/9] amd-pstate: Add sysfs support for floor_freq and floor_count Date: Fri, 6 Mar 2026 15:27:50 +0530 Message-ID: <20260306095753.17155-7-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260306095753.17155-1-gautham.shenoy@amd.com> References: <20260306095753.17155-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A2:EE_|DS7PR12MB5886:EE_ X-MS-Office365-Filtering-Correlation-Id: 0c1f4b25-ea95-4154-9e7c-08de7b66edb3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|376014|1800799024; X-Microsoft-Antispam-Message-Info: nQ/gpO0LETwLqlG8XBiq42b0Tl+j2/XZsSWxqRtyhiEXvFrmB0iZVS6T/ux7Zi8+NfvEuHMkGG3ewOEaox02BHx2yadv8cwB4aU5W2+IrHnmRLr+/6AWwI145/QXQ5mtWj9oHyW8ubzyY5MoKYiczTFGrrZB2MCyOWbM6jtmyg7BDMiIvAgwvkCvnFLd85hsLqNv28pV5EmNSBxAYGQe0RLFtCtBTic/bXpJJ25lEtVJXzQiMkEOjrOPbX4njfC8vbzZz0sj5Ny65gPHEBkDiRwZMc6Hz6PfTdZxdPzUYXV/iOx0RtmFJSoHNLKQfPXWHTrMIMMeu12oXzl8H0VhAnNK1M9NEg2mMK/1x3Gss+Gsf0rRNGpcuVzJMKr7KdwE8r/cS0zEDsUudjx4jO0pglIhXtR5lohXsJX+IN8EzvnvnEJo+9CIpeF0dsW2KzH4o6s0q+8EZi+pAPbtN7izOPyA+xhNcOXYs/w8lUqcIWNo6G0ibzpPl0/Nl0tA6NsyL/Fspgrfwm0ACLVNvyQYIRGa7eIXOTbE69ckzXvu9opbkatJz9PZPE1ax+JwuIjjgaj4zi6NijOJRJtdRDWB2g5BpZQu0z9mrxtezG7Fr2FvoiRDgm285L+asRnZc96MYRi7P0avSxhv0O8loKLfIYbMSoddFc6UFvGq7kgYHZx3xUysDMX68mAoFTzlZAM0bKiFnXW+524Yug3NL1FK/s3pH++OljhPkBrxl1VHKlSRYhsuUAwqrpr5RSNbPaDlOP1e3dWJU6RptPXchhpsbA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: tDEoUsP+AboVvxEe7ec8PFVmK6U94GocRgo0tZQrJBbBwpYzbntEMQoXaM1liWHr5eC5DT//nqRhEg3amUa1DpUteU0QNVQABMrCsYBU+Sa4EVXMRUdF+F3hWRN2xyC4+lLZXG2j6Bds+uRL7T2aG9VQERrwhPpjnSb5CBDONPZ9Dxgbv3aq6ZTPqq9NXeX2te33rRLplxoqJtLynQGBAzBceZ7lFQcDdAHyQAi8bSNVuvOSkYOGtkmjDtblPiHG018k3CGbK5obvrGfoajmfC+HYw04o8WA/NtXopKDQWQe8aoULU7Kj0r1M4IC2Aqo/xyHUuU/QbajHE6q3b0pvsHWMduFZ3DtarIjyqJUX1X5Vi1FEMh+CfaLp5fMN1XlAGP8UGRnHE0wTbD40XoK1oI5e17qMixb8azkdQg6T4aomcF3cihqu6zF2b7+rofK X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2026 09:58:33.7598 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0c1f4b25-ea95-4154-9e7c-08de7b66edb3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5886 Content-Type: text/plain; charset="utf-8" When Floor Performance feature is supported by the platform, expose two sysfs files: * amd_pstate_floor_freq to allow userspace to request the floor frequency for each CPU. * amd_pstate_floor_count which advertises the number of distinct levels of floor frequencies supported on this platform. Signed-off-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 52 ++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index fdc1c102a873c..a0bc80a7d3f15 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1295,6 +1295,48 @@ static ssize_t show_energy_performance_preference( return sysfs_emit(buf, "%s\n", energy_perf_strings[preference]); } =20 +static ssize_t store_amd_pstate_floor_freq(struct cpufreq_policy *policy, + const char *buf, size_t count) +{ + struct amd_cpudata *cpudata =3D policy->driver_data; + union perf_cached perf =3D READ_ONCE(cpudata->perf); + unsigned int freq; + u8 floor_perf; + int ret; + + ret =3D kstrtouint(buf, 0, &freq); + if (ret) + return ret; + + floor_perf =3D freq_to_perf(perf, cpudata->nominal_freq, freq); + ret =3D amd_pstate_set_floor_perf(policy, floor_perf); + + return ret ?: count; +} + +static ssize_t show_amd_pstate_floor_freq(struct cpufreq_policy *policy, c= har *buf) +{ + struct amd_cpudata *cpudata =3D policy->driver_data; + union perf_cached perf =3D READ_ONCE(cpudata->perf); + u64 cppc_req2 =3D READ_ONCE(cpudata->cppc_req2_cached); + unsigned int freq; + u8 floor_perf; + + floor_perf =3D FIELD_GET(AMD_CPPC_FLOOR_PERF_MASK, cppc_req2); + freq =3D perf_to_freq(perf, cpudata->nominal_freq, floor_perf); + + return sysfs_emit(buf, "%u\n", freq); +} + + +static ssize_t show_amd_pstate_floor_count(struct cpufreq_policy *policy, = char *buf) +{ + struct amd_cpudata *cpudata =3D policy->driver_data; + u8 count =3D cpudata->floor_perf_cnt; + + return sysfs_emit(buf, "%u\n", count); +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); =20 @@ -1303,6 +1345,8 @@ cpufreq_freq_attr_ro(amd_pstate_prefcore_ranking); cpufreq_freq_attr_ro(amd_pstate_hw_prefcore); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); +cpufreq_freq_attr_rw(amd_pstate_floor_freq); +cpufreq_freq_attr_ro(amd_pstate_floor_count); =20 struct freq_attr_visibility { struct freq_attr *attr; @@ -1327,6 +1371,12 @@ static bool epp_visibility(void) return cppc_state =3D=3D AMD_PSTATE_ACTIVE; } =20 +/* Determines whether amd_pstate_floor_freq related attributes should be v= isible */ +static bool floor_freq_visibility(void) +{ + return cpu_feature_enabled(X86_FEATURE_CPPC_PERF_PRIO); +} + static struct freq_attr_visibility amd_pstate_attr_visibility[] =3D { {&amd_pstate_max_freq, always_visible}, {&amd_pstate_lowest_nonlinear_freq, always_visible}, @@ -1335,6 +1385,8 @@ static struct freq_attr_visibility amd_pstate_attr_vi= sibility[] =3D { {&amd_pstate_hw_prefcore, prefcore_visibility}, {&energy_performance_preference, epp_visibility}, {&energy_performance_available_preferences, epp_visibility}, + {&amd_pstate_floor_freq, floor_freq_visibility}, + {&amd_pstate_floor_count, floor_freq_visibility}, }; =20 static struct freq_attr **get_freq_attrs(void) --=20 2.34.1