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Shenoy" To: Mario Limonciello , "Rafael J . Wysocki" , Viresh Kumar , K Prateek Nayak CC: , , "Gautham R. Shenoy" Subject: [PATCH 1/9] amd-pstate: Fix memory leak in amd_pstate_epp_cpu_init() Date: Fri, 6 Mar 2026 15:27:45 +0530 Message-ID: <20260306095753.17155-2-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260306095753.17155-1-gautham.shenoy@amd.com> References: <20260306095753.17155-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A4:EE_|IA1PR12MB6044:EE_ X-MS-Office365-Filtering-Correlation-Id: 4b55f00e-d5a9-4edc-8063-08de7b66e62d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|376014|13003099007; X-Microsoft-Antispam-Message-Info: Inzh72+nNGsnytlQoFTkEbP+MZXBXaAwx4F9NlbRkEM52y0R5vY1rMTHP1etV0qzwEjWWAvJyYuaXMt/ou02BOSjSZjlZ6dxq4GZh2D2ct7d5ccUHMYbY63GZl4Me8Zac33NptzvaKeVEBqaUhldq8w04FnTvP95N3hhjH7BftA7CWqxT352AcWbpcvzvamSO3jI+qA3ZyCjWz2HNnj/nU0jcj/ZqZFkh6Hd2sUnV2AlQF3dEbtKZRIeprkrNaRMJyWHH9GlmLDt6lme0vRNwEtef+QtWkI1C90CefMZajpw/oisDTP9wm6O95dQdxgecindR8n8Fgt94DMRZmFGOD7C9HEd4XdEjGaXqcyNesB3L1saVwK4j7bcTGRQCqBvyX6R1zktH6Kzd1qi21JhrwHQ4wkoGL4ZPFwPuZqzGxlzqcKLJUO06JHI8gQcyTLCKKxvuG3MRkFLXnIKWZyK16HNnUmzcOGUZF98VKdsbmH8Gzcc36zBZDqGNI1FyhDDjkTsh8b5oy05rqI3CYfukxoEjvqZxcsGmsj1p7MJMyUCP35JHjFHwfEvgvi2hgxUPKVj8a/+sJNcTbRE5S1MumG5vL3yiZzDJZEB1+EGUhTHAINpL5z8tnZKiJ5ep7iGkfmqiSKLV2TTTZN+M0lv91iy+BaTTVzclFr2yiqAI9FiDEHzfLYCAOTOgdlkXlEW7eerkU49olwmaC7lHJvJJqQHrX/Ato2b7xDycr/iJuxVysQPn30rmQ32PaSgha7iqxhdhXcqCRlySEEmyCRx8Q== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(376014)(13003099007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Zy9b05qViGfu2jmD7n+V6leKDn7WNrQYkg2WIdsbpgBMO6toJPRFUc0fy2s+HssbXN9jQAKKvfYSjz6kW8aUyDO5AC9MLOVqH1fxkvRoeNHLeZiqhCmQIATC8pMk7dpTrpgt++aMi/5Msua9ZCR5uvPPcLZ2AAorFxSFpUttNgPs4PIidoeiB5u2xHfDn+8AOl/lI+CprkMCKOYABYJitNyCwyf9uRgbbi/5lGVa17LfsdG6BZC019t1KFQR/tuOsPRgO7CDAxhV1wR2ixujmoG1suoRRh8nBtXUMgJ1wVOmqKzGUx9aoSZyZ5AEAVLEk5AEhgwXuU5D+eq0jE1u/1XAQIyMw1D/Un9xWzLVAQzyPsg9tCvT9eQZ1E7MHub5kWrFRPpKE39I+J91ds0d+OWyBTmaBHd4E/gROyfBpuxQIbwUBhJQ6ceeu5NdF3zm X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2026 09:58:21.1384 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b55f00e-d5a9-4edc-8063-08de7b66e62d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6044 Content-Type: text/plain; charset="utf-8" On failure to set the epp, the function amd_pstate_epp_cpu_init() returns with an error code without freeing the cpudata object that was allocated at the beginning of the function. Ensure that the cpudata object is freed before returning from the function. This memory leak was discovered by Claude Opus 4.6 with the aid of Chris Mason's AI review-prompts (https://github.com/masoncl/review-prompts/tree/main/kernel). Assisted-by: Claude:claude-opus-4.6 review-prompts/linux Fixes: f9a378ff6443 ("cpufreq/amd-pstate: Set different default EPP policy = for Epyc and Ryzen") Signed-off-by: Gautham R. Shenoy Reviewed-by: K Prateek Nayak Reviewed-by: Mario Limonciello (AMD) --- drivers/cpufreq/amd-pstate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 5aa9fcd80cf51..d57969c72c9dc 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1533,7 +1533,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_pol= icy *policy) =20 ret =3D amd_pstate_set_epp(policy, cpudata->epp_default); if (ret) - return ret; + goto free_cpudata1; =20 current_pstate_driver->adjust_perf =3D NULL; =20 --=20 2.34.1 From nobody Thu Apr 9 17:10:07 2026 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011060.outbound.protection.outlook.com [40.93.194.60]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F4ED33D4EE; Fri, 6 Mar 2026 09:58:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 6 Mar 2026 03:58:20 -0600 From: "Gautham R. Shenoy" To: Mario Limonciello , "Rafael J . Wysocki" , Viresh Kumar , K Prateek Nayak CC: , , "Gautham R. Shenoy" Subject: [PATCH 2/9] amd-pstate: Update cppc_req_cached in fast_switch case Date: Fri, 6 Mar 2026 15:27:46 +0530 Message-ID: <20260306095753.17155-3-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260306095753.17155-1-gautham.shenoy@amd.com> References: <20260306095753.17155-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A4:EE_|MN0PR12MB6127:EE_ X-MS-Office365-Filtering-Correlation-Id: 9f7e6641-ef17-4016-dfed-08de7b66e79b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|82310400026|376014|13003099007; X-Microsoft-Antispam-Message-Info: YfVKj8fsAqXxGnjjg0BadkTNT3PckL3Lg3pddlOA3OBI4G3lYtouWGg0yMZiA8OJz28ej3SS5i2pG9swXyoBzQ1RGkyiCp6zZpzU8SSe+2TNlZ/pon8LbcwqZGWTQEkqV7zkgEDj34TZbCNElZXnxgOQ1WVTgqpBidLA8xEz1fhznyYHbjTOjPugq0bRcMAyAz6mu5zseCMVm9zB7x76zohO/VFNqsU8TRA2W7jWOoJRXYR0u3b+BqzFsHyb53113gW146YWgg4SUFdHIVpRtq4SWIk83gvrYRYw1ecFuN6NY2Lb1RcT39YK2dQdLeys4SdU9hgoXVaSivXK59ngejHazMuuJywE7F1Vhi6pKj/BnojV9lodspsvzhEN6WObmZdOQn+7bQlE0lNXDEqdjxPi87qNJbsL1L9IsoqT8ezTP8r506dBkA+Y/0VAGV0aGonLu+mqMg4IZT2THW6/QnKopI8AT5TAp1rX+yEBaqorj3cgzv1I4wcRznEIkRO4JeoxhqrRMRjjzGRakvoW59oBZX9Htur+RbWJamfKuARg/iZ+JEuyIOC0QS3AaYEdKVBVTMK3/4jUUSJWh/Q4bFOLUP7Fb9ifTQJI4khKMaB6A3ZDEoqZ2Ne/5QCYeyS08Rz/Vu8dUIpZOxDjVvjzWVa4RSzpK6O2uhxAI0dH859zexrPIvhMiUgh5f4qY/XbcGma0b3nCpxVgfoCoLF+W3l9B7S9jDE3MpOnH5O9NwcCqdY/Q9InHZ+W0pSauw8bduIR+R65dpeNqBRUoZDf1g== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(82310400026)(376014)(13003099007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: eP+wUdqFRFLDN72U8q5gsA+aMnxjw7k99rVpbSGFxaVFGm1NkB77BoWeLyQAbdLejUXnRdlPET8XLqTk14vsrS6haKOWT8etOQGsMQtkxJCoCqb9007jOcpcl5iUtP4c98s/J8E1oahT2XC0F5JPQaiIrQTUAQX+2ybFEzOXU4UylsBX3vQUqxmrOPlF+c4UHGMHJ7BZjE58vaWOGSm83czO5EVSqvHiKu80iYcKCUUwLrZ/33VzEm/VlSENAag+THZBWeYi6sxBS+et9N/d+dp+NCHskw8L+vvFBfkMCkaGFy/mXzrA9SX7Sqty8UP3e1Ln2UDvrKSqWbrvDFz1pVl+SbyphZyYBD6Ibuau71DOwWeYFybEIPjRGe7kqnvhvQ3DL58GEYI0ynpjbXrZX1MMLFSN3OBZEE6D5yZRsMw4gUU5hEG+ezJPxQxVAzMU X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2026 09:58:23.5393 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f7e6641-ef17-4016-dfed-08de7b66e79b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6127 Content-Type: text/plain; charset="utf-8" The function msr_update_perf() does not cache the new value that is written to MSR_AMD_CPPC_REQ into the variable cpudata->cppc_req_cached when the update is happening from the fast path. Fix that by caching the value everytime the MSR_AMD_CPPC_REQ gets updated. This issue was discovered by Claude Opus 4.6 with the aid of Chris Mason's AI review-prompts (https://github.com/masoncl/review-prompts/tree/main/kernel). Assisted-by: Claude:claude-opus-4.6 review-prompts/linux Fixes: fff395796917 ("cpufreq/amd-pstate: Always write EPP value when updat= ing perf") Signed-off-by: Gautham R. Shenoy Reviewed-by: K Prateek Nayak --- drivers/cpufreq/amd-pstate.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index d57969c72c9dc..24cdeffbcd40e 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -261,7 +261,6 @@ static int msr_update_perf(struct cpufreq_policy *polic= y, u8 min_perf, =20 if (fast_switch) { wrmsrq(MSR_AMD_CPPC_REQ, value); - return 0; } else { int ret =3D wrmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); =20 --=20 2.34.1 From nobody Thu Apr 9 17:10:07 2026 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011047.outbound.protection.outlook.com [40.93.194.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 195D434DB71; Fri, 6 Mar 2026 09:58:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.194.47 ARC-Seal: i=2; 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Fri, 6 Mar 2026 09:58:24 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BN2PEPF000044A1.mail.protection.outlook.com (10.167.243.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9678.18 via Frontend Transport; Fri, 6 Mar 2026 09:58:25 +0000 Received: from BLRRASHENOY1.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Fri, 6 Mar 2026 03:58:23 -0600 From: "Gautham R. Shenoy" To: Mario Limonciello , "Rafael J . Wysocki" , Viresh Kumar , K Prateek Nayak CC: , , "Gautham R. Shenoy" Subject: [PATCH 3/9] amd-pstate: Make certain freq_attrs conditionally visible Date: Fri, 6 Mar 2026 15:27:47 +0530 Message-ID: <20260306095753.17155-4-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260306095753.17155-1-gautham.shenoy@amd.com> References: <20260306095753.17155-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A1:EE_|SA1PR12MB9545:EE_ X-MS-Office365-Filtering-Correlation-Id: e890b786-a6b4-418e-6774-08de7b66e8c2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: 4IKcUJgIuTGUEG/OkoaxoCUVzDKHGRZ2cAFMda1zCvtuZ4Ej73MFiyH7r+I74XS9z6ohbHA6jkTl7TBUNG38BVW/lFo+6Kg2Pt7wI/og157NhYxYnLgpEeyxMwHWjZKJxuaqwZKdJ3FeTKTX/LJLyYsQkmxU2/O8/yDkdjP0MCdlvN+Yxissf9QzE7xYR6aCFQy3p+PnkJ6bs/R941cOS7o9K2AiQ2eZ1qydXBzkFHOaEnsWqHpPHbKK/3naoYl1MYfENFT1qaTffQX48Xe0OcPW7ZbZZB/Dj38u4bTXKU7BNk3KUefLYmSQJPVCbbokf2POv+Tn08uBaUNa5Hx/K2Dk0iMOhR01fgxHAtIVoTjnA+JdeiOXZmU2sFQRNJ0PP+lMrryQGw4gr/r9Av9Bt9JXi+MoBL7dl8hmd9WrZRNxfD2xrLBJqZ+qYRar81uR+7NfW2y300qoYthdevRBXdzivlvjl4aAnlGHtoCji9y3cCPyTGBKHBIwMLauwn2zIWmKPljDFfwvNoU+69iKEUB+vRhs7z8Kvy9hU06PBeJId/5zmfbo7nJ7oCCII7XZfJqztzD1VdGU17rD+Ad0xgpYFEJk9Fzjm4zuXwusKgWlOkb27kW43ODgm5S4TvV1T0JHJXo9epHUaNckqdVOJpVyRNCxidkZriZNbDud+elwoxm2gbnrUuBODL8El4hCea9PZQ/xbyknF3tQuXSJMLcuqeuFWBLiHpB//ypnj3SBKKyN1n9t5YHgh7gD+wkpbpsa2lpedaHw9WLRZU4fMw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sLz6CXIWSoby8u8srVVSOHNvdq37aVoorzzrg348m++g5qdSZTAHuVZepG6NwkhYHlYb+3ywx/H03Wfa+RjOQM8cPLkP9rNg39Z0EpqlSWA9E21CnPZ2IbCZhRnWSEcVaHdhiJB41FlyuFUNVyws7TN/b5FH712dv8KLAKyG15U8vGBFzJldZJLkMzLGnl9Nhs3Yro4aizPZOh6hh711+RJsO034QNcLD7h5dexjrDO3kfIWXhWnFyj/fNG8MaGz7ooAj1TKz8FObr3VIe3YCnzmLVCWEmASR3UoVlz9IQVHZTLc5VxVnv+e9lNBRkgTTAuxRgMPIdz1I99LQgLEzyCekcNXCKvu2voc/xc3zn/UR/08Pt4EMmbhmNtNoIoU2XX//Zm23QK77LtIOXrmZfve2kTzBq+NAWSt07YBQSLyjNopPbyoMRI3GYjQzZgy X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2026 09:58:25.4693 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e890b786-a6b4-418e-6774-08de7b66e8c2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A1.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB9545 Content-Type: text/plain; charset="utf-8" Certain amd_pstate freq_attrs such as amd_pstate_hw_prefcore and amd_pstate_prefcore_ranking are enabled even when preferred core is not supported on the platform. Similarly there are common freq_attrs between the amd-pstate and the amd-pstate-epp drivers (eg: amd_pstate_max_freq, amd_pstate_lowest_non_linear_freq, etc.) but are duplicated in two different freq_attr structs. Unify all the attributes in a single place and associate each of them with a visibility function that determines whether the attribute should be visible based on the underlying platform support and the current amd_pstate mode. Signed-off-by: Gautham R. Shenoy Reviewed-by: K Prateek Nayak --- drivers/cpufreq/amd-pstate.c | 123 ++++++++++++++++++++++++++--------- 1 file changed, 92 insertions(+), 31 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 24cdeffbcd40e..fb5d7bb320c15 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1220,12 +1220,86 @@ static ssize_t show_energy_performance_preference( return sysfs_emit(buf, "%s\n", energy_perf_strings[preference]); } =20 +cpufreq_freq_attr_ro(amd_pstate_max_freq); +cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); + +cpufreq_freq_attr_ro(amd_pstate_highest_perf); +cpufreq_freq_attr_ro(amd_pstate_prefcore_ranking); +cpufreq_freq_attr_ro(amd_pstate_hw_prefcore); +cpufreq_freq_attr_rw(energy_performance_preference); +cpufreq_freq_attr_ro(energy_performance_available_preferences); + +struct freq_attr_visibility { + struct freq_attr *attr; + bool (*visibility_fn)(void); +}; + +/* For attributes which are always visible */ +static bool always_visible(void) +{ + return true; +} + +/* Determines whether prefcore related attributes should be visible */ +static bool prefcore_visibility(void) +{ + return amd_pstate_prefcore; +} + +/* Determines whether energy performance preference should be visible */ +static bool epp_visibility(void) +{ + return cppc_state =3D=3D AMD_PSTATE_ACTIVE; +} + +static struct freq_attr_visibility amd_pstate_attr_visibility[] =3D { + {&amd_pstate_max_freq, always_visible}, + {&amd_pstate_lowest_nonlinear_freq, always_visible}, + {&amd_pstate_highest_perf, always_visible}, + {&amd_pstate_prefcore_ranking, prefcore_visibility}, + {&amd_pstate_hw_prefcore, prefcore_visibility}, + {&energy_performance_preference, epp_visibility}, + {&energy_performance_available_preferences, epp_visibility}, +}; + +static struct freq_attr **get_freq_attrs(void) +{ + bool attr_visible[ARRAY_SIZE(amd_pstate_attr_visibility)]; + struct freq_attr **attrs; + int i, j, count; + + for (i =3D 0, count =3D 0; i < ARRAY_SIZE(amd_pstate_attr_visibility); i+= +) { + struct freq_attr_visibility *v =3D &amd_pstate_attr_visibility[i]; + + attr_visible[i] =3D v->visibility_fn(); + if (attr_visible[i]) + count++; + } + + /* amd_pstate_{max_freq, lowest_nonlinear_freq, highest_freq} should alwa= ys be visible */ + BUG_ON(!count); + + attrs =3D kcalloc(count + 1, sizeof(struct freq_attr *), GFP_KERNEL); + if (!attrs) + return ERR_PTR(-ENOMEM); + + for (i =3D 0, j =3D 0; i < ARRAY_SIZE(amd_pstate_attr_visibility); i++) { + if (!attr_visible[i]) + continue; + + attrs[j++] =3D amd_pstate_attr_visibility[i].attr; + } + + return attrs; +} + static void amd_pstate_driver_cleanup(void) { if (amd_pstate_prefcore) sched_clear_itmt_support(); =20 cppc_state =3D AMD_PSTATE_DISABLE; + kfree(current_pstate_driver->attr); current_pstate_driver =3D NULL; } =20 @@ -1250,6 +1324,7 @@ static int amd_pstate_set_driver(int mode_idx) =20 static int amd_pstate_register_driver(int mode) { + struct freq_attr **attr =3D NULL; int ret; =20 ret =3D amd_pstate_set_driver(mode); @@ -1258,6 +1333,22 @@ static int amd_pstate_register_driver(int mode) =20 cppc_state =3D mode; =20 + /* + * Note: It is important to compute the attrs _after_ + * re-initializing the cppc_state. Some attributes become + * visible only when cppc_state is AMD_PSTATE_ACTIVE. + */ + attr =3D get_freq_attrs(); + if (IS_ERR(attr)) { + ret =3D (int) PTR_ERR(attr); + pr_err("Couldn't compute freq_attrs for current mode %s [%d]\n", + amd_pstate_get_mode_string(cppc_state), ret); + amd_pstate_driver_cleanup(); + return ret; + } + + current_pstate_driver->attr =3D attr; + /* at least one CPU supports CPB */ current_pstate_driver->boost_enabled =3D cpu_feature_enabled(X86_FEATURE_= CPB); =20 @@ -1399,37 +1490,9 @@ static ssize_t prefcore_show(struct device *dev, return sysfs_emit(buf, "%s\n", str_enabled_disabled(amd_pstate_prefcore)); } =20 -cpufreq_freq_attr_ro(amd_pstate_max_freq); -cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); - -cpufreq_freq_attr_ro(amd_pstate_highest_perf); -cpufreq_freq_attr_ro(amd_pstate_prefcore_ranking); -cpufreq_freq_attr_ro(amd_pstate_hw_prefcore); -cpufreq_freq_attr_rw(energy_performance_preference); -cpufreq_freq_attr_ro(energy_performance_available_preferences); static DEVICE_ATTR_RW(status); static DEVICE_ATTR_RO(prefcore); =20 -static struct freq_attr *amd_pstate_attr[] =3D { - &amd_pstate_max_freq, - &amd_pstate_lowest_nonlinear_freq, - &amd_pstate_highest_perf, - &amd_pstate_prefcore_ranking, - &amd_pstate_hw_prefcore, - NULL, -}; - -static struct freq_attr *amd_pstate_epp_attr[] =3D { - &amd_pstate_max_freq, - &amd_pstate_lowest_nonlinear_freq, - &amd_pstate_highest_perf, - &amd_pstate_prefcore_ranking, - &amd_pstate_hw_prefcore, - &energy_performance_preference, - &energy_performance_available_preferences, - NULL, -}; - static struct attribute *pstate_global_attributes[] =3D { &dev_attr_status.attr, &dev_attr_prefcore.attr, @@ -1696,7 +1759,6 @@ static struct cpufreq_driver amd_pstate_driver =3D { .set_boost =3D amd_pstate_set_boost, .update_limits =3D amd_pstate_update_limits, .name =3D "amd-pstate", - .attr =3D amd_pstate_attr, }; =20 static struct cpufreq_driver amd_pstate_epp_driver =3D { @@ -1712,7 +1774,6 @@ static struct cpufreq_driver amd_pstate_epp_driver = =3D { .update_limits =3D amd_pstate_update_limits, .set_boost =3D amd_pstate_set_boost, .name =3D "amd-pstate-epp", - .attr =3D amd_pstate_epp_attr, }; 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Shenoy" To: Mario Limonciello , "Rafael J . Wysocki" , Viresh Kumar , K Prateek Nayak CC: , , "Gautham R. Shenoy" , "H. Peter Anvin" , "Borislav Petkov" , Dave Hansen , "Thomas Gleixner" , Ingo Molnar , Subject: [PATCH 4/9] x86/cpufeatures: Add AMD CPPC Performance Priority feature. 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The platform firmware takes these different floor performance levels into consideration while throttling the CPUs under power/thermal constraints. The presence of this feature is indicated by bit 16 of the EDX register for CPUID leaf 0x80000007. More details can be found in AMD Publication titled "AMD64 Collaborative Processor Performance Control (CPPC) Performance Priority" Revision 1.10. Define a new feature bit named X86_FEATURE_CPPC_PERF_PRIO to map to CPUID 0x80000007.EDX[16]. Signed-off-by: Gautham R. Shenoy Reviewed-by: Borislav Petkov (AMD) Reviewed-by: K Prateek Nayak --- Link to AMD publication describing this feature: https://docs.amd.com/v/u/e= n-US/69206_1.10_AMD64_CPPC_PUB arch/x86/include/asm/cpufeatures.h | 2 +- arch/x86/kernel/cpu/scattered.c | 1 + tools/arch/x86/include/asm/cpufeatures.h | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index dbe104df339b8..86d17b195e794 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -415,7 +415,7 @@ */ #define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* "overflow_recov" MCA over= flow recovery support */ #define X86_FEATURE_SUCCOR (17*32+ 1) /* "succor" Uncorrectable error con= tainment and recovery */ - +#define X86_FEATURE_CPPC_PERF_PRIO (17*32+ 2) /* CPPC Floor Perf support */ #define X86_FEATURE_SMCA (17*32+ 3) /* "smca" Scalable MCA */ =20 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index 42c7eac0c387b..837d6a4b0c282 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -52,6 +52,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, { X86_FEATURE_AMD_FAST_CPPC, CPUID_EDX, 15, 0x80000007, 0 }, + { X86_FEATURE_CPPC_PERF_PRIO, CPUID_EDX, 16, 0x80000007, 0 }, { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_X2AVIC_EXT, CPUID_ECX, 6, 0x8000000a, 0 }, { X86_FEATURE_COHERENCY_SFW_NO, CPUID_EBX, 31, 0x8000001f, 0 }, diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/incl= ude/asm/cpufeatures.h index c3b53beb13007..1f1aeeb151337 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -414,7 +414,7 @@ */ #define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* "overflow_recov" MCA over= flow recovery support */ #define X86_FEATURE_SUCCOR (17*32+ 1) /* "succor" Uncorrectable error con= tainment and recovery */ - +#define X86_FEATURE_CPPC_PERF_PRIO (17*32+ 2) /* CPPC Floor Perf support */ #define X86_FEATURE_SMCA (17*32+ 3) /* "smca" Scalable MCA */ =20 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ --=20 2.34.1 From nobody Thu Apr 9 17:10:07 2026 Received: from CH5PR02CU005.outbound.protection.outlook.com (mail-northcentralusazon11012040.outbound.protection.outlook.com [40.107.200.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE46E34D4EA; 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Shenoy" To: Mario Limonciello , "Rafael J . Wysocki" , Viresh Kumar , K Prateek Nayak CC: , , "Gautham R. Shenoy" Subject: [PATCH 5/9] amd-pstate: Add support for CPPC_REQ2 and FLOOR_PERF Date: Fri, 6 Mar 2026 15:27:49 +0530 Message-ID: <20260306095753.17155-6-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260306095753.17155-1-gautham.shenoy@amd.com> References: <20260306095753.17155-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A4:EE_|BY5PR12MB4258:EE_ X-MS-Office365-Filtering-Correlation-Id: 4b09c043-c218-4c68-ae3e-08de7b66ec5d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700016|376014|13003099007; X-Microsoft-Antispam-Message-Info: URjGGezuC3ghq5RTvOGEoLFpyrpfXMzpM+L9xqkz25Qh/BKUH+Wm6gnGoNyUeAyTn13ow6/SxJGtpNo8r8b5L91UBMFkQjcZemYpHDGPQarGe8rxD3IJig5bEdn37iv2HcmU5KrPFMNZwvuTSl3Iijq/5rnSPmv7t+A4G62V138+5zaW6TsEcU853rZtLmf+GLKb1WFgF8EIQXKsguoi9IDqpLq18isMb2zmk86ROXQXiz/1UqwIGeOc+oFwyothjMCa09PoN6HzULUYMQZ0tTckCvKEaQhBn2WUvY6AWHttidkk8wnXHZSe76WHBgT0tVnYdyF6RpKdFnjvtD6PqT6DxP+Tpm/hl85MJxDptyUpZ7iVch38D0I0hERMkW5F4wKSNICfWGrWpRRHgeFS0zpSIPhQ3U6AbDBsXYId50zvOlcbwe6fsqNtAaRNbJS7IPG/UIBp8HE86YduoiecvGDxarlQvI8GAVPhGNCdpB6Fs9srjA8Vg7dgoVvxuH83pT/hXC5zm276/bp6mi+ZtFrVeKqGiiVAWecbOz3s5jNNi0l5Pu6VvnSUbnXc33HIZDVCm2nQEagUIz+q/5rEK3T1IpHx14riOR1SttR9UG+bnv12MBzIMYKmqgTdeyG4zPzx4HOk6x7YZjGQcWWeGl7cGv85owhYKRZfcRCycCQ+vIjlMof74twgjko3nKPlstfz+BBGlILNpBfvGZrNHSCp4EmkRo1jmptE5MeoPNcGAAn0YxSBHYCvlWQV0eIwvYryG4QWFlIVrsYWBicn4Q== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700016)(376014)(13003099007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: b4w4W0bIVzujojeVZjsdVXVfmt+LUmGPzCwZdRtYVGiYlqOMhchkenokXkQFDewJXLP35FTtCW9lqtLl/7QjuesdbMzO/kcNRFuanj/H/PsOIqOcpb9nH3EFWPnQDH/UVFYtOvGZRhzbbvZ5FZaxUME7+WN+I3zP+MTqW5XFd+eSJiNT4PQBfPq7NGOtaYzw464aZ7EsbYAPs1HOC5dojoPUY7+Ial0zQZGpwkZCdHbX2uGrqd8gkY9yYfs+A3oSlsjING3z+l/y1THnNnkzGulWnZ1Ft5II4gwDruMAtTIYkd17um7W4IIX3Txl0AsnDk1IeXa2+zePGUX0s+FoJlV2SvFdcmVmhvgVmny20P/xJO/gQ2i2iQTTC9pzmxNd7ezVgNJLqWYyQc8EMmzBrfy6ojI4SCZfJMfArnJBqnbDn42kPifiPt0Z5tpldVUK X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2026 09:58:31.5205 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b09c043-c218-4c68-ae3e-08de7b66ec5d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4258 Content-Type: text/plain; charset="utf-8" Some future AMD processors have feature named "CPPC Performance Priority" which lets userspace specify different floor performance levels for different CPUs. The platform firmware takes these different floor performance levels into consideration while throttling the CPUs under power/thermal constraints. The presence of this feature is indicated by bit 16 of the EDX register for CPUID leaf 0x80000007. More details can be found in AMD Publication titled "AMD64 Collaborative Processor Performance Control (CPPC) Performance Priority" Revision 1.10. The number of distinct floor performance levels supported on the platform will be advertised through the bits 32:39 of the MSR_AMD_CPPC_CAP1. Bits 0:7 of a new MSR MSR_AMD_CPPC_REQ2 (0xc00102b5) will be used to specify the desired floor performance level for that CPU. Add support for the aforementioned MSR_AMD_CPPC_REQ2, and macros for parsing and updating the relevant bits from MSR_AMD_CPPC_CAP1 and MSR_AMD_CPPC_REQ2. On boot if the default value of the MSR_AMD_CPPC_REQ2[7:0] (Floor Perf) is lower than CPPC.lowest_perf, and thus invalid, initialize it to MSR_AMD_CPPC_CAP1.nominal_perf which is a sane default value. Signed-off-by: Gautham R. Shenoy Reviewed-by: K Prateek Nayak --- Link to AMD publication describing this feature: https://docs.amd.com/v/u/e= n-US/69206_1.10_AMD64_CPPC_PUB arch/x86/include/asm/msr-index.h | 5 ++ drivers/cpufreq/amd-pstate.c | 81 ++++++++++++++++++++++++++++++++ drivers/cpufreq/amd-pstate.h | 5 ++ 3 files changed, 91 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index da5275d8eda63..60547dcf47d0f 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -762,12 +762,14 @@ #define MSR_AMD_CPPC_CAP2 0xc00102b2 #define MSR_AMD_CPPC_REQ 0xc00102b3 #define MSR_AMD_CPPC_STATUS 0xc00102b4 +#define MSR_AMD_CPPC_REQ2 0xc00102b5 =20 /* Masks for use with MSR_AMD_CPPC_CAP1 */ #define AMD_CPPC_LOWEST_PERF_MASK GENMASK(7, 0) #define AMD_CPPC_LOWNONLIN_PERF_MASK GENMASK(15, 8) #define AMD_CPPC_NOMINAL_PERF_MASK GENMASK(23, 16) #define AMD_CPPC_HIGHEST_PERF_MASK GENMASK(31, 24) +#define AMD_CPPC_FLOOR_PERF_CNT_MASK GENMASK(39, 32) =20 /* Masks for use with MSR_AMD_CPPC_REQ */ #define AMD_CPPC_MAX_PERF_MASK GENMASK(7, 0) @@ -775,6 +777,9 @@ #define AMD_CPPC_DES_PERF_MASK GENMASK(23, 16) #define AMD_CPPC_EPP_PERF_MASK GENMASK(31, 24) =20 +/* Masks for use with MSR_AMD_CPPC_REQ2 */ +#define AMD_CPPC_FLOOR_PERF_MASK GENMASK(7, 0) + /* AMD Performance Counter Global Status and Control MSRs */ #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index fb5d7bb320c15..fdc1c102a873c 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -329,6 +329,74 @@ static inline int amd_pstate_set_epp(struct cpufreq_po= licy *policy, u8 epp) return static_call(amd_pstate_set_epp)(policy, epp); } =20 +static int amd_pstate_set_floor_perf(struct cpufreq_policy *policy, u8 per= f) +{ + struct amd_cpudata *cpudata =3D policy->driver_data; + u64 value, prev; + int ret; + + if (!cpu_feature_enabled(X86_FEATURE_CPPC_PERF_PRIO)) + return 0; + + value =3D prev =3D READ_ONCE(cpudata->cppc_req2_cached); + FIELD_MODIFY(AMD_CPPC_FLOOR_PERF_MASK, &value, perf); + + if (value =3D=3D prev) + return 0; + + ret =3D wrmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ2, value); + if (ret) { + pr_err("failed to set CPPC REQ2 value. Error (%d)\n", ret); + return ret; + } + + WRITE_ONCE(cpudata->cppc_req2_cached, value); + + return ret; +} + +static int amd_pstate_cache_cppc_req2(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata =3D policy->driver_data; + u64 value; + int ret; + + if (!cpu_feature_enabled(X86_FEATURE_CPPC_PERF_PRIO)) + return 0; + + ret =3D rdmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ2, &value); + if (ret) { + pr_err("failed to read CPPC REQ2 value. Error (%d)\n", ret); + return ret; + } + + WRITE_ONCE(cpudata->cppc_req2_cached, value); + return 0; +} + +static int amd_pstate_init_floor_perf(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata =3D policy->driver_data; + u8 floor_perf; + int ret; + + if (!cpu_feature_enabled(X86_FEATURE_CPPC_PERF_PRIO)) + return 0; + + ret =3D amd_pstate_cache_cppc_req2(policy); + if (ret) + return ret; + + floor_perf =3D FIELD_GET(AMD_CPPC_FLOOR_PERF_MASK, + cpudata->cppc_req2_cached); + + /* Don't overwrite a sane value initialized by the platform firmware */ + if (floor_perf > cpudata->perf.lowest_perf) + return 0; + + return amd_pstate_set_floor_perf(policy, cpudata->perf.nominal_perf); +} + static int shmem_set_epp(struct cpufreq_policy *policy, u8 epp) { struct amd_cpudata *cpudata =3D policy->driver_data; @@ -426,6 +494,7 @@ static int msr_init_perf(struct amd_cpudata *cpudata) perf.lowest_perf =3D FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1); WRITE_ONCE(cpudata->perf, perf); WRITE_ONCE(cpudata->prefcore_ranking, FIELD_GET(AMD_CPPC_HIGHEST_PERF_MAS= K, cap1)); + WRITE_ONCE(cpudata->floor_perf_cnt, FIELD_GET(AMD_CPPC_FLOOR_PERF_CNT_MAS= K, cap1)); =20 return 0; } @@ -1036,6 +1105,12 @@ static int amd_pstate_cpu_init(struct cpufreq_policy= *policy) if (cpu_feature_enabled(X86_FEATURE_CPPC)) policy->fast_switch_possible =3D true; =20 + ret =3D amd_pstate_init_floor_perf(policy); + if (ret) { + dev_err(dev, "Failed to initialize Floor Perf (%d)\n", ret); + goto free_cpudata1; + } + ret =3D freq_qos_add_request(&policy->constraints, &cpudata->req[0], FREQ_QOS_MIN, FREQ_QOS_MIN_DEFAULT_VALUE); if (ret < 0) { @@ -1597,6 +1672,12 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_po= licy *policy) if (ret) goto free_cpudata1; =20 + ret =3D amd_pstate_init_floor_perf(policy); + if (ret) { + dev_err(dev, "Failed to initialize Floor Perf (%d)\n", ret); + goto free_cpudata1; + } + current_pstate_driver->adjust_perf =3D NULL; =20 return 0; diff --git a/drivers/cpufreq/amd-pstate.h b/drivers/cpufreq/amd-pstate.h index cb45fdca27a6c..0c587ca200199 100644 --- a/drivers/cpufreq/amd-pstate.h +++ b/drivers/cpufreq/amd-pstate.h @@ -62,9 +62,12 @@ struct amd_aperf_mperf { * @cpu: CPU number * @req: constraint request to apply * @cppc_req_cached: cached performance request hints + * @cppc_req2_cached: cached value of MSR_AMD_CPPC_REQ2 * @perf: cached performance-related data * @prefcore_ranking: the preferred core ranking, the higher value indicat= es a higher * priority. + * @floor_perf_cnt: Cached value of the number of distinct floor + * performance levels supported * @min_limit_freq: Cached value of policy->min (in khz) * @max_limit_freq: Cached value of policy->max (in khz) * @nominal_freq: the frequency (in khz) that mapped to nominal_perf @@ -87,10 +90,12 @@ struct amd_cpudata { =20 struct freq_qos_request req[2]; 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Shenoy" Subject: [PATCH 6/9] amd-pstate: Add sysfs support for floor_freq and floor_count Date: Fri, 6 Mar 2026 15:27:50 +0530 Message-ID: <20260306095753.17155-7-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260306095753.17155-1-gautham.shenoy@amd.com> References: <20260306095753.17155-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A2:EE_|DS7PR12MB5886:EE_ X-MS-Office365-Filtering-Correlation-Id: 0c1f4b25-ea95-4154-9e7c-08de7b66edb3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|376014|1800799024; X-Microsoft-Antispam-Message-Info: nQ/gpO0LETwLqlG8XBiq42b0Tl+j2/XZsSWxqRtyhiEXvFrmB0iZVS6T/ux7Zi8+NfvEuHMkGG3ewOEaox02BHx2yadv8cwB4aU5W2+IrHnmRLr+/6AWwI145/QXQ5mtWj9oHyW8ubzyY5MoKYiczTFGrrZB2MCyOWbM6jtmyg7BDMiIvAgwvkCvnFLd85hsLqNv28pV5EmNSBxAYGQe0RLFtCtBTic/bXpJJ25lEtVJXzQiMkEOjrOPbX4njfC8vbzZz0sj5Ny65gPHEBkDiRwZMc6Hz6PfTdZxdPzUYXV/iOx0RtmFJSoHNLKQfPXWHTrMIMMeu12oXzl8H0VhAnNK1M9NEg2mMK/1x3Gss+Gsf0rRNGpcuVzJMKr7KdwE8r/cS0zEDsUudjx4jO0pglIhXtR5lohXsJX+IN8EzvnvnEJo+9CIpeF0dsW2KzH4o6s0q+8EZi+pAPbtN7izOPyA+xhNcOXYs/w8lUqcIWNo6G0ibzpPl0/Nl0tA6NsyL/Fspgrfwm0ACLVNvyQYIRGa7eIXOTbE69ckzXvu9opbkatJz9PZPE1ax+JwuIjjgaj4zi6NijOJRJtdRDWB2g5BpZQu0z9mrxtezG7Fr2FvoiRDgm285L+asRnZc96MYRi7P0avSxhv0O8loKLfIYbMSoddFc6UFvGq7kgYHZx3xUysDMX68mAoFTzlZAM0bKiFnXW+524Yug3NL1FK/s3pH++OljhPkBrxl1VHKlSRYhsuUAwqrpr5RSNbPaDlOP1e3dWJU6RptPXchhpsbA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: tDEoUsP+AboVvxEe7ec8PFVmK6U94GocRgo0tZQrJBbBwpYzbntEMQoXaM1liWHr5eC5DT//nqRhEg3amUa1DpUteU0QNVQABMrCsYBU+Sa4EVXMRUdF+F3hWRN2xyC4+lLZXG2j6Bds+uRL7T2aG9VQERrwhPpjnSb5CBDONPZ9Dxgbv3aq6ZTPqq9NXeX2te33rRLplxoqJtLynQGBAzBceZ7lFQcDdAHyQAi8bSNVuvOSkYOGtkmjDtblPiHG018k3CGbK5obvrGfoajmfC+HYw04o8WA/NtXopKDQWQe8aoULU7Kj0r1M4IC2Aqo/xyHUuU/QbajHE6q3b0pvsHWMduFZ3DtarIjyqJUX1X5Vi1FEMh+CfaLp5fMN1XlAGP8UGRnHE0wTbD40XoK1oI5e17qMixb8azkdQg6T4aomcF3cihqu6zF2b7+rofK X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2026 09:58:33.7598 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0c1f4b25-ea95-4154-9e7c-08de7b66edb3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5886 Content-Type: text/plain; charset="utf-8" When Floor Performance feature is supported by the platform, expose two sysfs files: * amd_pstate_floor_freq to allow userspace to request the floor frequency for each CPU. * amd_pstate_floor_count which advertises the number of distinct levels of floor frequencies supported on this platform. Signed-off-by: Gautham R. Shenoy Reviewed-by: K Prateek Nayak --- drivers/cpufreq/amd-pstate.c | 52 ++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index fdc1c102a873c..a0bc80a7d3f15 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1295,6 +1295,48 @@ static ssize_t show_energy_performance_preference( return sysfs_emit(buf, "%s\n", energy_perf_strings[preference]); } =20 +static ssize_t store_amd_pstate_floor_freq(struct cpufreq_policy *policy, + const char *buf, size_t count) +{ + struct amd_cpudata *cpudata =3D policy->driver_data; + union perf_cached perf =3D READ_ONCE(cpudata->perf); + unsigned int freq; + u8 floor_perf; + int ret; + + ret =3D kstrtouint(buf, 0, &freq); + if (ret) + return ret; + + floor_perf =3D freq_to_perf(perf, cpudata->nominal_freq, freq); + ret =3D amd_pstate_set_floor_perf(policy, floor_perf); + + return ret ?: count; +} + +static ssize_t show_amd_pstate_floor_freq(struct cpufreq_policy *policy, c= har *buf) +{ + struct amd_cpudata *cpudata =3D policy->driver_data; + union perf_cached perf =3D READ_ONCE(cpudata->perf); + u64 cppc_req2 =3D READ_ONCE(cpudata->cppc_req2_cached); + unsigned int freq; + u8 floor_perf; + + floor_perf =3D FIELD_GET(AMD_CPPC_FLOOR_PERF_MASK, cppc_req2); + freq =3D perf_to_freq(perf, cpudata->nominal_freq, floor_perf); + + return sysfs_emit(buf, "%u\n", freq); +} + + +static ssize_t show_amd_pstate_floor_count(struct cpufreq_policy *policy, = char *buf) +{ + struct amd_cpudata *cpudata =3D policy->driver_data; + u8 count =3D cpudata->floor_perf_cnt; + + return sysfs_emit(buf, "%u\n", count); +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); =20 @@ -1303,6 +1345,8 @@ cpufreq_freq_attr_ro(amd_pstate_prefcore_ranking); cpufreq_freq_attr_ro(amd_pstate_hw_prefcore); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); +cpufreq_freq_attr_rw(amd_pstate_floor_freq); +cpufreq_freq_attr_ro(amd_pstate_floor_count); =20 struct freq_attr_visibility { struct freq_attr *attr; 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Fri, 6 Mar 2026 03:58:33 -0600 From: "Gautham R. Shenoy" To: Mario Limonciello , "Rafael J . Wysocki" , Viresh Kumar , K Prateek Nayak CC: , , "Gautham R. Shenoy" Subject: [PATCH 7/9] amd-pstate: Introduce a tracepoint trace_amd_pstate_cppc_req2() Date: Fri, 6 Mar 2026 15:27:51 +0530 Message-ID: <20260306095753.17155-8-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260306095753.17155-1-gautham.shenoy@amd.com> References: <20260306095753.17155-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000449F:EE_|DS7PR12MB8289:EE_ X-MS-Office365-Filtering-Correlation-Id: a78c5ebe-67e7-468f-1cf8-08de7b66ef5b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700016; X-Microsoft-Antispam-Message-Info: cYstSXAyb4fgdNTCh/J9ELw9bH7zGR8UM3KGEZ8tn5krhjRCzdxKxDx6Zpkf0Ht4Cb3m5X1hDLsJYiT5ecRkR1oRDq9fZI2zghYuaL71HsG3SM1TTfJ98uaIPyNvcWX4bbL/cTDMuFS2Y58ozAcBdRkvrtnba2XO6ycisiMa3j3QFH/8NFBWthYD4gcllXOSBuMP/K+58vbRDe+NFxmcJXoM9G9xeH24q5sFmGnGKtG4iyka8icalMizK5DKld+ZroMxUyiEFQf6dTT9l623ZLjE1cuqDafBsTP57Uc0MrbEAacZ4HMZi0OyE5GNp3lBMyib9woBHQsoA2/FQ5SkBD2leF1nBFR28qyhl0wCv5Bm1uOKO3lKeH/VJDWFAWmoAAVOEiBUVENi0WGhpN+b6Mi8tdyGChmH+vXmTPp0WTHXGSDJY7WFFu1YoGOsLVQ3triUsbdn+T3nNgIj9Snhyyw2ZBfYPxPJMuKUeuN1hjVg9pE57SvXkfCqhFGVMrqNXp7QfkXpbpVe7x6mB5UDY9eJc0IDSP13RAjk7ZGkSSJjsyR5ww4yKCM/lzVxzmPh3Xi2lwuQ3RK3DMMd/QmPq/+sZz77akEAsFCxAwSbxJHG3j1jAJMSTqpDkeks3W0gUi0gtgGav0bmV3Ac+yFbcPxBlZxSvtqoX1qDZngkmyRcsjvqnFDRUN5OtZ+/qy1dG4BgQDefKd6EPi203TD7guesSfKfuQ29LyGLXaMOirGzRr9P/ungqHM6TyBu528ZC1oNvL9npTLGr4WGL83x0Q== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700016);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 8+wbcdMZoTKO9ZulYTxNBG/sR+meg9x2r3NxVENaXA4zFMMBAHz+H8CcV29WOl1GEF7t+XcXnqXboVjBe6hA2F5sLgOG6A+uE422V1xmFNY263dXEuBtGqQkkr633L9vDOwIuqM+nmGK+WkH3GwaQ5js2WC2WLRM3I8Ge/9QLGfCjp8SV+fFQkotMuk6za/Lq3XD1+GNWcFPbWy82Qj7wrLUfSBe1TfHWjJUQJMeA5XQBAhRh0Vq0KB/ZBVmHdp3JzO7LYOjJ4FLt0Cb466HNVYxccZb+6dY+7xKyMWngg3SCniCSW6fM8uOjehJDQUnIWuHtbpKWJzyQQeCSk1Hv1uYI/07zdZQNjvgPCc5S02U3g9cGpCgXQ4MWC+OWY+RLozfoga0mRsGjBoE1z8y+Dd41hJ3pu//bzfIM3K9erZz5Yp5uoDXOjdOPxfwnylO X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2026 09:58:36.5371 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a78c5ebe-67e7-468f-1cf8-08de7b66ef5b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000449F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8289 Content-Type: text/plain; charset="utf-8" Introduce a new tracepoint trace_amd_pstate_cppc_req2() to track updates to MSR_AMD_CPPC_REQ2. Invoke this while changing the Floor Perf. Reviewed-by: Mario Limonciello Signed-off-by: Gautham R. Shenoy Reviewed-by: K Prateek Nayak --- drivers/cpufreq/amd-pstate-trace.h | 35 ++++++++++++++++++++++++++++++ drivers/cpufreq/amd-pstate.c | 14 +++++++++--- 2 files changed, 46 insertions(+), 3 deletions(-) diff --git a/drivers/cpufreq/amd-pstate-trace.h b/drivers/cpufreq/amd-pstat= e-trace.h index 32e1bdc588c52..91fa073b2be48 100644 --- a/drivers/cpufreq/amd-pstate-trace.h +++ b/drivers/cpufreq/amd-pstate-trace.h @@ -133,6 +133,41 @@ TRACE_EVENT(amd_pstate_epp_perf, ) ); =20 +TRACE_EVENT(amd_pstate_cppc_req2, + + TP_PROTO(unsigned int cpu_id, + u8 floor_perf, + bool changed, + int err_code + ), + + TP_ARGS(cpu_id, + floor_perf, + changed, + err_code), + + TP_STRUCT__entry( + __field(unsigned int, cpu_id) + __field(u8, floor_perf) + __field(bool, changed) + __field(int, err_code) + ), + + TP_fast_assign( + __entry->cpu_id =3D cpu_id; + __entry->floor_perf =3D floor_perf; + __entry->changed =3D changed; + __entry->err_code =3D err_code; + ), + + TP_printk("cpu%u: floor_perf=3D%u, changed=3D%u (error =3D %d)", + __entry->cpu_id, + __entry->floor_perf, + __entry->changed, + __entry->err_code + ) +); + #endif /* _AMD_PSTATE_TRACE_H */ =20 /* This part must be outside protection */ diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index a0bc80a7d3f15..632e87b700b14 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -333,6 +333,7 @@ static int amd_pstate_set_floor_perf(struct cpufreq_pol= icy *policy, u8 perf) { struct amd_cpudata *cpudata =3D policy->driver_data; u64 value, prev; + bool changed; int ret; =20 if (!cpu_feature_enabled(X86_FEATURE_CPPC_PERF_PRIO)) @@ -341,17 +342,24 @@ static int amd_pstate_set_floor_perf(struct cpufreq_p= olicy *policy, u8 perf) value =3D prev =3D READ_ONCE(cpudata->cppc_req2_cached); FIELD_MODIFY(AMD_CPPC_FLOOR_PERF_MASK, &value, perf); =20 - if (value =3D=3D prev) - return 0; + changed =3D value !=3D prev; + if (!changed) { + ret =3D 0; + goto out_trace; + } =20 ret =3D wrmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ2, value); if (ret) { + changed =3D false; pr_err("failed to set CPPC REQ2 value. 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Shenoy" , Jonathan Corbet , "Shuah Khan" Subject: [PATCH 8/9] Documentation/amd-pstate: List prefcore related sysfs files Date: Fri, 6 Mar 2026 15:27:52 +0530 Message-ID: <20260306095753.17155-9-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260306095753.17155-1-gautham.shenoy@amd.com> References: <20260306095753.17155-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A4:EE_|IA1PR12MB9531:EE_ X-MS-Office365-Filtering-Correlation-Id: 5f0e62c6-df25-4935-61df-08de7b66f0ce X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700016; X-Microsoft-Antispam-Message-Info: CJYx1k9GEF5peKRE3o3M2nS761zaxq261EYQf1CrQi6om3EOCrVJgOrtFYL+SIHzjyuVto3L0zfO8ZV0SKvv2PFlQsOUFaIC6/qC9uqu4Z7t8yVH7NCZuA3guv8txmwvjIpkSIIqCVBlrR/WTuN8cUiezLi6xXNGM6UQzfrLdT5Wi4sgdsaf13kXR9JO6qDVowCfoVJycV8GBUoOdg1hZheq+cc1Fae2kVSlB5GXqBnQ/XmPywV1E8CmGYnFF5H6DrX/BHViTEUjPqRvP3OLp/4gd67UqN8FdOpfxEz2QfIpVSdVmpauGBfpO0CyiVHYM6zUoUfdArt0jrn2yu3Pb4pkkFI/JSVlVzbhOJHz78LiDBTTlf8Fy7cC/ihsmlC1tlOjELkozwi8f6KgDy1OveFgH/z70GAtO6QB+JjJ8Z3XFVkA7ESUW0d0VZBsfKwv4cEd+GfgrjPzh/TGsKhuRhXewTPKPlODHoickPF7mFwU1AeEKztajDHqMh2xkd+0AR/+ix78wDVGi6OOPmQDcZFW2IXriVBYpSJ/y1iOKgZU5dOxduLcgM2fnuiDDKGXDiqCVELnTCZ4oiy9TvR2VGEyU5IE/gOyHS2ms9loolZjBJv4mHEp4y2ElQDX3tjAnjSuBmvSuAmtDljYzy5Rrdefef2VChzsi1Z3/bTm0Dur5ctUhDBCuNCm9U3krHWB+3qAjwhVBDTsxBHLIYGMdbkM8UIG7Jqaz7seUz3VvCGuc3l+PiFdJ97yxgHDRKsAnR0hTo0Kor/7WQNQQE2Hfw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700016);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: eMGXYcZELVeGAAg6zX0SG0NMJcehJUjW4hqyR686+hW/92WmgBAB2GRrUyzSqd5KUP21NkQ4nCsI1tOu/yyVDcX4QwTqlU/T7xoDg7+xl0GWjcBPMYNkPklPN7Xclg13DAhgKKavXB8two0yTDopB/UgwmKlGBhlA1k3FFRond9FmmabsMpe0wuNDdIcOlxqt5pb9K+ZOtNqO+xsV8KLfHp8K4SnEvMAmHepxPKvlGOT5LQdIXshzEOMdPtGPsDrBB5T02JcZGI9Pk4rAbZeD9aR55oDzsJbbvGrpbMNtFE4lhQfTkzriCznDjwP6mp5sfDPz4Sn0GnvJ4zDKOkTzVMKn9x+oyF9XfDl5CIn/9/ukUObwhjXr4ikac5Fh7YklCpjvWA1c8XWuck84w6m0zkLgSY9pskO2aSF5q6EIPrJQCNKjfwP3WR+aQ3pKS6D X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2026 09:58:38.9690 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5f0e62c6-df25-4935-61df-08de7b66f0ce X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A4.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB9531 Content-Type: text/plain; charset="utf-8" Add the missing amd_pstate_hw_prefcore and amd_pstate_prefcore_ranking filenames in the sysfs listing example leading to the descriptions of these parameters. Signed-off-by: Gautham R. Shenoy Reviewed-by: K Prateek Nayak --- Documentation/admin-guide/pm/amd-pstate.rst | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/ad= min-guide/pm/amd-pstate.rst index e1771f2225d5f..f566fea6613e6 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -239,8 +239,10 @@ control its functionality at the system level. They ar= e located in the =20 root@hr-test1:/home/ray# ls /sys/devices/system/cpu/cpufreq/policy0/*amd* /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_highest_perf + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_hw_prefcore /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_lowest_nonlinear_freq /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_max_freq + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_prefcore_ranking =20 =20 ``amd_pstate_highest_perf / amd_pstate_max_freq`` @@ -264,14 +266,17 @@ This attribute is read-only. =20 ``amd_pstate_hw_prefcore`` =20 -Whether the platform supports the preferred core feature and it has been -enabled. This attribute is read-only. +Whether the platform supports the preferred core feature and it has +been enabled. This attribute is read-only. This file is only visible +on platforms which support the preferred core feature. =20 ``amd_pstate_prefcore_ranking`` =20 -The performance ranking of the core. This number doesn't have any unit, but -larger numbers are preferred at the time of reading. This can change at -runtime based on platform conditions. This attribute is read-only. +The performance ranking of the core. This number doesn't have any +unit, but larger numbers are preferred at the time of reading. This +can change at runtime based on platform conditions. This attribute is +read-only. This file is only visible on platforms which support the +preferred core feature. =20 ``energy_performance_available_preferences`` =20 --=20 2.34.1 From nobody Thu Apr 9 17:10:07 2026 Received: from DM1PR04CU001.outbound.protection.outlook.com (mail-centralusazon11010009.outbound.protection.outlook.com [52.101.61.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57DB534D4DF; Fri, 6 Mar 2026 09:58:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.61.9 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772791128; cv=fail; b=m9oyAl+Il93fh1v45BnPv4GVlfatDgW/422DKTi6RiVaMk0FJJHxrb3+Li0hwGQ296dQp6iNCsbwSDesp1EUkNBQV1Lz9KozoykeC/qzm9fjf3GHeXI2j5VItcbQIgJhF9rwB0/0SJu+5pbnNfzbAXjiuFgDwgtoEbgDeuq7PdQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772791128; c=relaxed/simple; bh=eXJTKR8Nb9eX4QEH9d0mCZ0lAH2TIwNGOJ/dtCvfWM0=; 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Shenoy" To: Mario Limonciello , "Rafael J . Wysocki" , Viresh Kumar , K Prateek Nayak CC: , , "Gautham R. Shenoy" , Jonathan Corbet , "Shuah Khan" Subject: [PATCH 9/9] Documentation/amd-pstate: Add documentation for amd_pstate_floor_{freq,count} Date: Fri, 6 Mar 2026 15:27:53 +0530 Message-ID: <20260306095753.17155-10-gautham.shenoy@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260306095753.17155-1-gautham.shenoy@amd.com> References: <20260306095753.17155-1-gautham.shenoy@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A1:EE_|IA0PR12MB7674:EE_ X-MS-Office365-Filtering-Correlation-Id: c0484825-48cb-4c1d-c713-08de7b66f276 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700016; X-Microsoft-Antispam-Message-Info: 43C7WcejKenrlW8kiCWP3vkPZulAOZWl90eMueIag13vgpR9OCiJgjS9JZ88XGVBhkpgavdZp0EkaOwqUFpa8sCevrL2aRX3II+UYWMPkQFjaNGVuUU+MoH+4sRDe9F931lYcMrrbNPAifVhPI4yOg728fbwQL8elHrjTNTOQdhP1pnLhhU4beKWjXSQcJTkakbWksjQzJlOTxWGEJ2OxqeimsXgKdlQe/USpaSV4t1i3yIzvEZJEkzWc1OBnFqBIx9xHV++fl5iqfx8Fqr/DheSUkELhtBTZYY9Ug/kYpfphTU1x2M7hVIQxvhYN4iq7ZSAFoNwlYumDkUNtYsWQDHEcpfuO3Z3ZAqBr6dnKTIvVjtkkRUe/f++bvn7Y5e5gkM0uolEgExaTw5fv6v+VM2gfnMKQdkTNyjirMQSJiHR8VlTP03uocUu+oVpj3yqYH61nY7CqBllqMJKSxBOe4MKom95KhPubQ7siQQjcjqemm2t+Ch2iUI1h6FgJF4SZmoYDWrUCu1zsM2kRAVVFIEjRK8x/pCIs11nzG7+0PzMBdE8jnM69nrh4DTdiCZpD/+o2qUBlFufs35Ki76vElcBRlzhb7KDb3WPokTTfZDXTCrzcs8oMkJyaNUWjd+CD4azGOHYHAB6/nuM7/aKfyQdrbsUL+8wPciBjUay0UaR293+e1Q3rPyD9Y3OqxR1kGA+0zol8xt7f8AgFcmfTY8BfV4Vn+2W7dEXIkx91apuAHBhzFqyg7MWv3TFq4zba0mo85j7fY5b20XTa6JdEw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(36860700016);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: mW71fTaeiUPerimY26TPzWuqSboZrjLHX0Fn+Cy01b50aROPdIcGtY8tBtpdmVhuRBXZzp61y/XH5+J7CYgbuxWN65QFEpgmtGLRJWpHWaDougQz7c6lG/9As0z71xvozftzowxx+w9KP8kGWcahL2BJh8/Y3kfuH6tRtzwnZjMXNByzril5gOABbVORecNA+XA6rpzoOyF+oN+iWwKUxJILTKW8LeQtBRDMGqIhCKDlC/TdWR6KugI6CvhPzj588CDxVAtD/Tz6S2FJ0bdwFUnV1uyqzkLl7fKxy567EdRzYcBhLujQdX3DhTvFbWomItyACwPE8p6eee7X9BNjHDplM8tcrFwh05mdw+8EIOcdZy+z72Fv8Ni0fxtY2h7n1X4CzSqZSr98aar6hTzvUi1CSSBxrE4TwIZRjQUs4t5eA7Ed56Xg4RABGo88nbSt X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2026 09:58:41.7551 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c0484825-48cb-4c1d-c713-08de7b66f276 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A1.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7674 Content-Type: text/plain; charset="utf-8" Add documentation for the sysfs files /sys/devices/system/cpu/cpufreq/policy*/amd_pstate_floor_freq and /sys/devices/system/cpu/cpufreq/policy*/amd_pstate_floor_count. Signed-off-by: Gautham R. Shenoy Reviewed-by: K Prateek Nayak --- Documentation/admin-guide/pm/amd-pstate.rst | 32 +++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/ad= min-guide/pm/amd-pstate.rst index f566fea6613e6..5fd2a36f8a4b8 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -242,6 +242,8 @@ control its functionality at the system level. They are= located in the /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_hw_prefcore /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_lowest_nonlinear_freq /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_max_freq + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_floor_freq + /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_floor_count /sys/devices/system/cpu/cpufreq/policy0/amd_pstate_prefcore_ranking =20 =20 @@ -278,6 +280,36 @@ can change at runtime based on platform conditions. Th= is attribute is read-only. This file is only visible on platforms which support the preferred core feature. =20 +``amd_pstate_floor_freq`` + +The floor frequency associated with each CPU. Userspace can write any +value between ``cpuinfo_min_freq`` and ``scaling_max_freq`` into this +file. When the system is under power or thermal constraints, the +platform firmware will attempt to throttle the CPU frequency to the +value specified in ``amd_pstate_floor_freq`` before throttling it +further. This allows userspace to specify different floor frequencies +to different CPUs. For optimal results, threads of the same core +should have the same floor frequency value. This file is only visible +on platforms that support the CPPC Performance Priority feature. + + +``amd_pstate_floor_count`` + +The number of distinct Floor Performance levels supported by the +platform. For example, if this value is 2, then the number of unique +values obtained from the command ``cat +/sys/devices/system/cpu/cpufreq/policy*/amd_pstate_floor_freq | +sort -n | uniq`` should be at most this number for the behavior +described in ``amd_pstate_floor_freq`` to take effect. A zero value +implies that the platform supports unlimited floor performance levels. +This file is only visible on platforms that support the CPPC +Performance Priority feature. + +**Note**: When ``amd_pstate_floor_count`` is non-zero, the frequency to +which the CPU is throttled under power or thermal constraints is +undefined when the number of unique values of ``amd_pstate_floor_freq`` +across all CPUs in the system exceeds ``amd_pstate_floor_count``. + ``energy_performance_available_preferences`` =20 A list of all the supported EPP preferences that could be used for --=20 2.34.1