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charset="utf-8" Starting with sc7280(kodiak), the ICE will have its own device-tree node. So add the qcom,ice property to reference it. To avoid double-modeling, when qcom,ice is present, disallow an embedded ICE register region in the SDHCI node. Older SoCs without ICE remain valid as no additional requirement is imposed. Co-developed-by: Abel Vesa Signed-off-by: Abel Vesa Co-developed-by: Abhinaba Rakshit Signed-off-by: Abhinaba Rakshit Signed-off-by: Neeraj Soni Reviewed-by: Krzysztof Kozlowski --- Some initial work is done by Abel here: https://lore.kernel.org/all/ba3da82d-999b-b040-5230-36e60293e0fd@linaro.org/ and by Abhinaba here: https://lore.kernel.org/all/20251009-add-separate-ice-ufs-and-emmc-device-n= odes-for-qcs615-platform-v1-1-2a34d8d03c72@oss.qualcomm.com/ This patch adds the purpose and usage for phandle in the description and en= codes it properly in the schema. --- .../devicetree/bindings/mmc/sdhci-msm.yaml | 95 +++++++++++++------ 1 file changed, 67 insertions(+), 28 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documen= tation/devicetree/bindings/mmc/sdhci-msm.yaml index 938be8228d66..cc9f7724bdf0 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -140,6 +140,11 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: platform specific settings for DLL_CONFIG reg. =20 + qcom,ice: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the Inline Crypto Engine (ICE) hardware block for this co= ntroller. + iommus: minItems: 1 maxItems: 8 @@ -193,35 +198,69 @@ allOf: enum: - qcom,sdhci-msm-v4 then: - properties: - reg: - minItems: 2 - items: - - description: Host controller register map - - description: SD Core register map - - description: CQE register map - - description: Inline Crypto Engine register map - reg-names: - minItems: 2 - items: - - const: hc - - const: core - - const: cqhci - - const: ice + if: + required: + - qcom,ice + then: + properties: + reg: + minItems: 2 + items: + - description: Host controller register map + - description: SD Core register map + - description: CQE register map + reg-names: + minItems: 2 + items: + - const: hc + - const: core + - const: cqhci + else: + properties: + reg: + minItems: 2 + items: + - description: Host controller register map + - description: SD Core register map + - description: CQE register map + - description: Inline Crypto Engine register map + reg-names: + minItems: 2 + items: + - const: hc + - const: core + - const: cqhci + - const: ice else: - properties: - reg: - minItems: 1 - items: - - description: Host controller register map - - description: CQE register map - - description: Inline Crypto Engine register map - reg-names: - minItems: 1 - items: - - const: hc - - const: cqhci - - const: ice + if: + required: + - qcom,ice + then: + properties: + reg: + minItems: 1 + items: + - description: Host controller register map + - description: CQE register map + reg-names: + minItems: 1 + items: + - const: hc + - const: cqhci + else: + properties: + reg: + minItems: 1 + items: + - description: Host controller register map + - description: CQE register map + - description: Inline Crypto Engine register map + reg-names: + minItems: 1 + items: + - const: hc + - const: cqhci + - const: ice =20 unevaluatedProperties: false =20 --=20 2.34.1 From nobody Sat Apr 11 10:48:25 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1583D3451D7 for ; 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charset="utf-8" Add an ICE node to kodiak SoC description and enable it by adding a phandle to the SDHC node. Signed-off-by: Neeraj Soni --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qco= m/kodiak.dtsi index c2ccbb67f800..de01a6669522 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -1045,6 +1045,8 @@ sdhc_1: mmc@7c4000 { qcom,dll-config =3D <0x0007642c>; qcom,ddr-config =3D <0x80040868>; =20 + qcom,ice =3D <&sdhc_ice>; + mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; @@ -1071,6 +1073,13 @@ opp-384000000 { }; }; =20 + sdhc_ice: crypto@7c8000 { + compatible =3D "qcom,sc7280-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg =3D <0x0 0x007c8000 0x0 0x18000>; + clocks =3D <&gcc GCC_SDCC1_ICE_CORE_CLK>; + }; + gpi_dma0: dma-controller@900000 { #dma-cells =3D <3>; compatible =3D "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; --=20 2.34.1 From nobody Sat Apr 11 10:48:25 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0058346A1F for ; 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charset="utf-8" Add an ICE node to monaco SoC description and enable it by adding a phandle to the SDHC node. --- arch/arm64/boot/dts/qcom/monaco.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qco= m/monaco.dtsi index 816fa2af8a9a..365af78b01ae 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -4202,6 +4202,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, supports-cqe; dma-coherent; =20 + qcom,ice =3D <&sdhc_ice>; + status =3D "disabled"; =20 sdhc1_opp_table: opp-table { @@ -4229,6 +4231,13 @@ opp-384000000 { }; }; =20 + sdhc_ice: crypto@87c8000 { + compatible =3D "qcom,qcs8300-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg =3D <0x0 0x087c8000 0x0 0x18000>; + clocks =3D <&gcc GCC_SDCC1_ICE_CORE_CLK>; + }; + usb_1_hsphy: phy@8904000 { compatible =3D "qcom,qcs8300-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; --=20 2.34.1