From nobody Wed Apr 1 22:34:16 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 869552750ED; Fri, 6 Mar 2026 08:53:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772787238; cv=none; b=neNayMBkOtCqLCL2p+g7eegUT4HVJR5Wc5kPKqzZPK5BTLHfJiEvIsJU6auRlvoV/8PlLyRzPPrEQv+RAj5lO7sWc1D1c9NLtCxQngbKBuBwioZMFc/nmj42sRn1EfOqABgkElPqq9CjtSbkBW9VWxEJF6ik8rEoXASf1ncw3s8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772787238; c=relaxed/simple; bh=oy/99Kw5MyaWysrU7BhOImMVNi2DTO3ASdtXxX9OzTE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WtLinPewhUL7VHrsL5LtT60GN7iStYSRIWJPhGciT/9PG40oQ3W0LOqPtjoDj4IK1/VJt0dMGTwp1tuPd2HmpOEOSgFVKE4dM8HYKSilwrnmNRSKtdT7K7FZTvrP0bRuboeF0770ERWHHfsoVoTkLNhafDpKvlo1wTvLFtVs8pA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=BTlc0rxE; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="BTlc0rxE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772787235; x=1804323235; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oy/99Kw5MyaWysrU7BhOImMVNi2DTO3ASdtXxX9OzTE=; b=BTlc0rxE1Vp0s04iWskm+Bdf7Hn2OQiNAW2Jc0+JIuBdOU6E6n6cWRu5 yLCvbPeR0Y5aA/5vl5kxVNALzx+qdTGNUBg23Z13Q5HMXMC4T19IIGgEZ 1uH2X4bTM7nUhE04D1KXd5wNjnXxQhzjS83vuLHoC79Zwsl1rmhkR3pv0 gqmJtFaotWfnQx5am1IwOahXc348UlweNzIhZgwe+YtL3Kbfsj/oLpb0l 4o6F2Enf7LkY5BHyk+5VypYhuPSkx+SQTplAsEdlxTFjcqYR/kQzio29o lboqKRxPH44riPWDy15s6LhFezrymYjW8dHQcpGalHzn6B9KYcgEjYiG2 Q==; X-CSE-ConnectionGUID: zCdrw9DDSDCsSIPcIrjeEw== X-CSE-MsgGUID: KI8IRdHaTi+RMqtUkv8T3g== X-IronPort-AV: E=McAfee;i="6800,10657,11720"; a="91467214" X-IronPort-AV: E=Sophos;i="6.23,104,1770624000"; d="scan'208";a="91467214" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2026 00:53:54 -0800 X-CSE-ConnectionGUID: mj2sFsy5TFOicqVCkKu/zg== X-CSE-MsgGUID: wzbbj62tShK3Vr/vBYr05A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,104,1770624000"; d="scan'208";a="223641473" Received: from dhhellew-desk2.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.171]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2026 00:53:52 -0800 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, rafael@kernel.org, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH V5 1/5] i3c: mipi-i3c-hci-pci: Set d3hot_delay to 0 for Intel controllers Date: Fri, 6 Mar 2026 10:53:34 +0200 Message-ID: <20260306085338.62955-2-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260306085338.62955-1-adrian.hunter@intel.com> References: <20260306085338.62955-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Set d3hot_delay to 0 for Intel controllers because a delay is not needed. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V3 and V4 and V5: None Changes in V2: Add Frank's Rev'd-by drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c b/drivers/i= 3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c index 30302e4d08e2..26298d80a3fa 100644 --- a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c +++ b/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c @@ -164,6 +164,7 @@ static int intel_i3c_init(struct mipi_i3c_hci_pci *hci) dma_set_mask_and_coherent(&hci->pci->dev, DMA_BIT_MASK(64)); =20 hci->pci->d3cold_delay =3D 0; + hci->pci->d3hot_delay =3D 0; =20 hci->private =3D host; host->priv =3D priv; --=20 2.51.0 From nobody Wed Apr 1 22:34:16 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2F4A23D7FF; Fri, 6 Mar 2026 08:53:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772787241; cv=none; b=uaQ9bWs1Kdxdor/hSA9LXxodNgmdJBVQzWHecPYrnRzB6lPC7jA3U1jhkyv0OwsE6oL5dBI7YssR2kG8ws1rokYlP/g1G/KOpdewJYWfT8MuxHHWiKTKHWGXaJ4J2mK9jgM3tsBC6DXPl2Q9+qPq2/D3Cm15ALBXJZy3ioljTKU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772787241; c=relaxed/simple; bh=qwDmbRV1xi7au7cFclTiYrS/8ARsycp12Je+jrPCUPM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LkdEZCgC3Ce558IsDNXihpWVBiHXNac6fSuzb2yF6kztZWvcS2PX0WWydpoXnpE7XTj6E03ayzyokGx7s5Pzi3Oaoudvv94XQWcpDd9g7312iOdtDduYw9oSzEi8xHajcqqn7685jfos3ykq7UtL4dSAKZkU9dBU9rP3ZZPjKOI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XejZQ8yC; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XejZQ8yC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772787238; x=1804323238; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qwDmbRV1xi7au7cFclTiYrS/8ARsycp12Je+jrPCUPM=; b=XejZQ8yCJzsBBpoEBvPb1ak80+xKkdn1+VT8jqaJOYLvqIoLHhbTSL1p iZMqPlyN28nMUcM1A8ilijrI4evAylbqdhTuOJUQ4OgmkG1RIkuo3/gKd e7GRb30K1n5HIuvfAF1ubp8D20l92NBX9X+Q5nJXWFxvGY78sd99qFg4Y SwY8ExjopeOeS/LL0/nSavabqdXW/IIp77O6N2ADY8z9IIibREEi++u+v BleUY5xnMhKdnPNA63lICcJzqO+6co1cUPLjCjMkcHzX89r65GZMDnBtR IjjrTxoQNUW4AQubM3r7cCPeJdcKzjyEwhU5dFY6+yJM4Ofnqa6xeVZbg Q==; X-CSE-ConnectionGUID: RDrtjYyKSqKpE6Qitwksfg== X-CSE-MsgGUID: m+wfKzJvSKukq4Dj9mjt9A== X-IronPort-AV: E=McAfee;i="6800,10657,11720"; a="91467227" X-IronPort-AV: E=Sophos;i="6.23,104,1770624000"; d="scan'208";a="91467227" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2026 00:53:56 -0800 X-CSE-ConnectionGUID: aoJ3nbkBSd2dUGyoZQnc+g== X-CSE-MsgGUID: C/Le+UoHQDeLLnnOnrqBrQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,104,1770624000"; d="scan'208";a="223641479" Received: from dhhellew-desk2.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.171]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2026 00:53:54 -0800 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, rafael@kernel.org, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH V5 2/5] i3c: mipi-i3c-hci: Add quirk to allow IBI while runtime suspended Date: Fri, 6 Mar 2026 10:53:35 +0200 Message-ID: <20260306085338.62955-3-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260306085338.62955-1-adrian.hunter@intel.com> References: <20260306085338.62955-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some I3C controllers can be automatically runtime-resumed in order to handle in-band interrupts (IBIs), meaning that runtime suspend does not need to be blocked when IBIs are enabled. For example, a PCI-attached controller in a low-power state may generate a Power Management Event (PME) when the SDA line is pulled low to signal the START condition of an IBI. The PCI subsystem will then runtime-resume the device, allowing the IBI to be received without requiring the controller to remain active. Introduce a new quirk, HCI_QUIRK_RPM_IBI_ALLOWED, so that drivers can opt-in to this capability via driver data. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V4 and V5: None Changes in V3: Add Frank's Rev'd-by Changes in V2: None drivers/i3c/master/mipi-i3c-hci/core.c | 3 +++ drivers/i3c/master/mipi-i3c-hci/hci.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 284f3ed7af8c..54d5492545ef 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -996,6 +996,9 @@ static int i3c_hci_probe(struct platform_device *pdev) if (hci->quirks & HCI_QUIRK_RPM_ALLOWED) i3c_hci_rpm_enable(&pdev->dev); =20 + if (hci->quirks & HCI_QUIRK_RPM_IBI_ALLOWED) + hci->master.rpm_ibi_allowed =3D true; + return i3c_master_register(&hci->master, &pdev->dev, &i3c_hci_ops, false); } =20 diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index 9ac9d0e342f4..02cab3b3bc6f 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -150,6 +150,7 @@ struct i3c_hci_dev_data { #define HCI_QUIRK_OD_PP_TIMING BIT(3) /* Set OD and PP timings for AMD p= latforms */ #define HCI_QUIRK_RESP_BUF_THLD BIT(4) /* Set resp buf thld to 0 for AMD= platforms */ #define HCI_QUIRK_RPM_ALLOWED BIT(5) /* Runtime PM allowed */ +#define HCI_QUIRK_RPM_IBI_ALLOWED BIT(6) /* IBI and Hot-Join allowed whil= e runtime suspended */ =20 /* global functions */ void mipi_i3c_hci_resume(struct i3c_hci *hci); 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X-CSE-ConnectionGUID: SljFq5DZRhu2hv/rM5CSiA== X-CSE-MsgGUID: BSCEtlxeT+WWNwKZjxPkjA== X-IronPort-AV: E=McAfee;i="6800,10657,11720"; a="91467239" X-IronPort-AV: E=Sophos;i="6.23,104,1770624000"; d="scan'208";a="91467239" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2026 00:53:59 -0800 X-CSE-ConnectionGUID: +YdkYsyYS9+S3ZC37ipvuQ== X-CSE-MsgGUID: n1dEhomqT1aSyH9FFhWP+g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,104,1770624000"; d="scan'208";a="223641487" Received: from dhhellew-desk2.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.171]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2026 00:53:57 -0800 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, rafael@kernel.org, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH V5 3/5] i3c: mipi-i3c-hci: Allow parent to manage runtime PM Date: Fri, 6 Mar 2026 10:53:36 +0200 Message-ID: <20260306085338.62955-4-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260306085338.62955-1-adrian.hunter@intel.com> References: <20260306085338.62955-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some platforms implement the MIPI I3C HCI Multi-Bus Instance capability, where a single parent device hosts multiple I3C controller instances. In such designs, the parent - not the individual child instances - may need to coordinate runtime PM so that all controllers runtime PM callbacks are invoked in a controlled and synchronized manner. For example, if the parent enables IBI-wakeup when transitioning into a low-power state, every bus instance must remain able to receive IBIs up until that point. This requires deferring the individual controllers' runtime suspend callbacks (which disable bus activity) until the parent decides it is safe for all instances to suspend together. To support this usage model: * Export the low-level runtime PM suspend and resume helpers so that the parent can explicitly invoke them. * Add a new quirk, HCI_QUIRK_RPM_PARENT_MANAGED, allowing platforms to bypass per-instance runtime PM callbacks and delegate control to the parent device. * Move DEFAULT_AUTOSUSPEND_DELAY_MS into the header so it can be shared by parent-managed PM implementations. The new quirk allows platforms with multi-bus parent-managed PM infrastructure to correctly coordinate runtime PM across all I3C HCI instances. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V5: Re-base on top of v7.0 fixes series: https://lore.kernel.org/linux-i3c/20260306072451.11131-1-adrian.hunter@in= tel.com/T Changes in V4: Add Frank's Rev'd-by Changes in V3: None Changes in V2: For HCI_QUIRK_RPM_PARENT_MANAGED case, change from disabling runtime PM to instead causing the runtime PM callbacks to do nothing drivers/i3c/master/mipi-i3c-hci/core.c | 28 ++++++++++++++++++++++---- drivers/i3c/master/mipi-i3c-hci/hci.h | 6 ++++++ 2 files changed, 30 insertions(+), 4 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 54d5492545ef..d803c0b7a64e 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -759,7 +759,7 @@ static int i3c_hci_reset_and_init(struct i3c_hci *hci) return 0; } =20 -static int i3c_hci_runtime_suspend(struct device *dev) +int i3c_hci_rpm_suspend(struct device *dev) { struct i3c_hci *hci =3D dev_get_drvdata(dev); int ret; @@ -776,8 +776,9 @@ static int i3c_hci_runtime_suspend(struct device *dev) =20 return 0; } +EXPORT_SYMBOL_GPL(i3c_hci_rpm_suspend); =20 -static int i3c_hci_runtime_resume(struct device *dev) +int i3c_hci_rpm_resume(struct device *dev) { struct i3c_hci *hci =3D dev_get_drvdata(dev); int ret; @@ -800,6 +801,27 @@ static int i3c_hci_runtime_resume(struct device *dev) =20 return 0; } +EXPORT_SYMBOL_GPL(i3c_hci_rpm_resume); + +static int i3c_hci_runtime_suspend(struct device *dev) +{ + struct i3c_hci *hci =3D dev_get_drvdata(dev); + + if (hci->quirks & HCI_QUIRK_RPM_PARENT_MANAGED) + return 0; + + return i3c_hci_rpm_suspend(dev); +} + +static int i3c_hci_runtime_resume(struct device *dev) +{ + struct i3c_hci *hci =3D dev_get_drvdata(dev); + + if (hci->quirks & HCI_QUIRK_RPM_PARENT_MANAGED) + return 0; + + return i3c_hci_rpm_resume(dev); +} =20 static int i3c_hci_suspend(struct device *dev) { @@ -844,8 +866,6 @@ static int i3c_hci_restore(struct device *dev) return i3c_hci_resume_common(dev, true); } =20 -#define DEFAULT_AUTOSUSPEND_DELAY_MS 1000 - static void i3c_hci_rpm_enable(struct device *dev) { struct i3c_hci *hci =3D dev_get_drvdata(dev); diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index 02cab3b3bc6f..f17f43494c1b 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -151,6 +151,7 @@ struct i3c_hci_dev_data { #define HCI_QUIRK_RESP_BUF_THLD BIT(4) /* Set resp buf thld to 0 for AMD= platforms */ #define HCI_QUIRK_RPM_ALLOWED BIT(5) /* Runtime PM allowed */ #define HCI_QUIRK_RPM_IBI_ALLOWED BIT(6) /* IBI and Hot-Join allowed whil= e runtime suspended */ +#define HCI_QUIRK_RPM_PARENT_MANAGED BIT(7) /* Runtime PM managed by pare= nt device */ =20 /* global functions */ void mipi_i3c_hci_resume(struct i3c_hci *hci); @@ -161,4 +162,9 @@ void amd_set_resp_buf_thld(struct i3c_hci *hci); void i3c_hci_sync_irq_inactive(struct i3c_hci *hci); int i3c_hci_process_xfer(struct i3c_hci *hci, struct hci_xfer *xfer, int n= ); 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06 Mar 2026 00:53:59 -0800 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, rafael@kernel.org, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH V5 4/5] i3c: mipi-i3c-hci-pci: Add optional ability to manage child runtime PM Date: Fri, 6 Mar 2026 10:53:37 +0200 Message-ID: <20260306085338.62955-5-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260306085338.62955-1-adrian.hunter@intel.com> References: <20260306085338.62955-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some platforms implement the MIPI I3C HCI Multi-Bus Instance capability, where a single parent device hosts multiple I3C controller instances. In such designs, the parent - not the individual child instances - may need to coordinate runtime PM so that all controllers runtime PM callbacks are invoked in a controlled and synchronized manner. For example, if the parent enables IBI-wakeup when transitioning into a low-power state, every bus instance must remain able to receive IBIs up until that point. This requires deferring the individual controllers' runtime suspend callbacks (which disable bus activity) until the parent decides it is safe for all instances to suspend together. To support this usage model: * Add runtime PM and system PM callbacks in the PCI driver to invoke the mipi-i3c-hci driver's runtime PM callbacks for each instance. * Introduce a driver-data flag, control_instance_pm, which opts into the new parent-managed PM behaviour. * Ensure the callbacks are only used when the corresponding instance is operational at suspend time. This is reliable because the operational state cannot change while the parent device is undergoing a PM transition, and PCI always performs a runtime resume before system suspend on current configurations, so that suspend and resume alternate irrespective of whether it is runtime or system PM. By that means, parent-managed runtime PM coordination for multi-instance MIPI I3C HCI PCI devices is provided without altering existing behaviour on platforms that do not require it. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V5: None Changes in V4: Add Frank's Rev'd-by Changes in V3: Remove unnecessary pm_runtime_mark_last_busy() Changes in V2: Do not enable autosuspend. Callbacks for parent-managed invocation were renamed from i3c_hci_runtime_suspend to i3c_hci_rpm_suspend and from i3c_hci_runtime_resume to i3c_hci_rpm_resume. Amend commit message slightly. .../master/mipi-i3c-hci/mipi-i3c-hci-pci.c | 131 ++++++++++++++++++ 1 file changed, 131 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c b/drivers/i= 3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c index 26298d80a3fa..17f30706eb48 100644 --- a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c +++ b/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -20,16 +21,24 @@ #include #include =20 +#include "hci.h" + /* * There can up to 15 instances, but implementations have at most 2 at this * time. */ #define INST_MAX 2 =20 +struct mipi_i3c_hci_pci_instance { + struct device *dev; + bool operational; +}; + struct mipi_i3c_hci_pci { struct pci_dev *pci; void __iomem *base; const struct mipi_i3c_hci_pci_info *info; + struct mipi_i3c_hci_pci_instance instance[INST_MAX]; void *private; }; =20 @@ -40,6 +49,7 @@ struct mipi_i3c_hci_pci_info { int id[INST_MAX]; u32 instance_offset[INST_MAX]; int instance_count; + bool control_instance_pm; }; =20 #define INTEL_PRIV_OFFSET 0x2b0 @@ -210,6 +220,125 @@ static const struct mipi_i3c_hci_pci_info intel_si_2_= info =3D { .instance_count =3D 1, }; =20 +static int mipi_i3c_hci_pci_find_instance(struct mipi_i3c_hci_pci *hci, st= ruct device *dev) +{ + for (int i =3D 0; i < INST_MAX; i++) { + if (!hci->instance[i].dev) + hci->instance[i].dev =3D dev; + if (hci->instance[i].dev =3D=3D dev) + return i; + } + + return -1; +} + +#define HC_CONTROL 0x04 +#define HC_CONTROL_BUS_ENABLE BIT(31) + +static bool __mipi_i3c_hci_pci_is_operational(struct device *dev) +{ + const struct mipi_i3c_hci_platform_data *pdata =3D dev->platform_data; + u32 hc_control =3D readl(pdata->base_regs + HC_CONTROL); + + return hc_control & HC_CONTROL_BUS_ENABLE; +} + +static bool mipi_i3c_hci_pci_is_operational(struct device *dev, bool updat= e) +{ + struct mipi_i3c_hci_pci *hci =3D dev_get_drvdata(dev->parent); + int pos =3D mipi_i3c_hci_pci_find_instance(hci, dev); + + if (pos < 0) { + dev_err(dev, "%s: I3C instance not found\n", __func__); + return false; + } + + if (update) + hci->instance[pos].operational =3D __mipi_i3c_hci_pci_is_operational(dev= ); + + return hci->instance[pos].operational; +} + +struct mipi_i3c_hci_pci_pm_data { + struct device *dev[INST_MAX]; + int dev_cnt; +}; + +static bool mipi_i3c_hci_pci_is_mfd(struct device *dev) +{ + return dev_is_platform(dev) && mfd_get_cell(to_platform_device(dev)); +} + +static int mipi_i3c_hci_pci_suspend_instance(struct device *dev, void *dat= a) +{ + struct mipi_i3c_hci_pci_pm_data *pm_data =3D data; + int ret; + + if (!mipi_i3c_hci_pci_is_mfd(dev) || + !mipi_i3c_hci_pci_is_operational(dev, true)) + return 0; + + ret =3D i3c_hci_rpm_suspend(dev); + if (ret) + return ret; + + pm_data->dev[pm_data->dev_cnt++] =3D dev; + + return 0; +} + +static int mipi_i3c_hci_pci_resume_instance(struct device *dev, void *data) +{ + struct mipi_i3c_hci_pci_pm_data *pm_data =3D data; + int ret; + + if (!mipi_i3c_hci_pci_is_mfd(dev) || + !mipi_i3c_hci_pci_is_operational(dev, false)) + return 0; + + ret =3D i3c_hci_rpm_resume(dev); + if (ret) + return ret; + + pm_data->dev[pm_data->dev_cnt++] =3D dev; + + return 0; +} + +static int mipi_i3c_hci_pci_suspend(struct device *dev) +{ + struct mipi_i3c_hci_pci *hci =3D dev_get_drvdata(dev); + struct mipi_i3c_hci_pci_pm_data pm_data =3D {}; + int ret; + + if (!hci->info->control_instance_pm) + return 0; + + ret =3D device_for_each_child_reverse(dev, &pm_data, mipi_i3c_hci_pci_sus= pend_instance); + if (ret) + for (int i =3D 0; i < pm_data.dev_cnt; i++) + i3c_hci_rpm_resume(pm_data.dev[i]); + + return ret; +} + +static int mipi_i3c_hci_pci_resume(struct device *dev) +{ + struct mipi_i3c_hci_pci *hci =3D dev_get_drvdata(dev); + struct mipi_i3c_hci_pci_pm_data pm_data =3D {}; + int ret; + + if (!hci->info->control_instance_pm) + return 0; + + ret =3D device_for_each_child(dev, &pm_data, mipi_i3c_hci_pci_resume_inst= ance); + if (ret) + for (int i =3D 0; i < pm_data.dev_cnt; i++) + i3c_hci_rpm_suspend(pm_data.dev[i]); + + return ret; +} + static void mipi_i3c_hci_pci_rpm_allow(struct device *dev) { pm_runtime_put(dev); @@ -323,6 +452,8 @@ static void mipi_i3c_hci_pci_remove(struct pci_dev *pci) =20 /* PM ops must exist for PCI to put a device to a low power state */ static const struct dev_pm_ops mipi_i3c_hci_pci_pm_ops =3D { + RUNTIME_PM_OPS(mipi_i3c_hci_pci_suspend, mipi_i3c_hci_pci_resume, NULL) + SYSTEM_SLEEP_PM_OPS(mipi_i3c_hci_pci_suspend, mipi_i3c_hci_pci_resume) }; =20 static const struct pci_device_id mipi_i3c_hci_pci_devices[] =3D { --=20 2.51.0 From nobody Wed Apr 1 22:34:16 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BAFDE2DF132; Fri, 6 Mar 2026 08:54:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772787248; cv=none; b=q4wjDFETtQiam11rIczi71azLneCsg/InEQY1A45O6gdS/gN5gg3v9UP2UYeCQ0ZKX+KUHfEJV7E3dT7EVhZYjsVZn9FqAqJqI7TBbAjzG1a0FuGTlZtleT/qkQ2LnWOgmOm04rp5ONGWuBbp5b1h6a4QG5SHFqQuFnAXu/2Bhc= ARC-Message-Signature: i=1; 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d="scan'208";a="223641505" Received: from dhhellew-desk2.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.171]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2026 00:54:01 -0800 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, rafael@kernel.org, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH V5 5/5] i3c: mipi-i3c-hci-pci: Enable IBI while runtime suspended for Intel controllers Date: Fri, 6 Mar 2026 10:53:38 +0200 Message-ID: <20260306085338.62955-6-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260306085338.62955-1-adrian.hunter@intel.com> References: <20260306085338.62955-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Intel LPSS I3C controllers can wake from runtime suspend to receive in-band interrupts (IBIs), and they also implement the MIPI I3C HCI Multi-Bus Instance capability. When multiple I3C bus instances share the same PCI wakeup, the PCI parent must coordinate runtime PM so that all instances suspend together and their mipi-i3c-hci runtime suspend callbacks are invoked in a consistent manner. Enable IBI-based wakeup by setting HCI_QUIRK_RPM_IBI_ALLOWED for the intel-lpss-i3c platform device. Also set HCI_QUIRK_RPM_PARENT_MANAGED so that the mipi-i3c-hci core driver expects runtime PM to be controlled by the PCI parent rather than by individual instances. For all Intel HCI PCI configurations, enable the corresponding control_instance_pm flag in the PCI driver. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V4 and V5: None Changes in V3: Add Frank's Rev'd-by Changes in V2: Retain HCI_QUIRK_RPM_ALLOWED Amend commit message accordingly drivers/i3c/master/mipi-i3c-hci/core.c | 4 +++- drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c | 3 +++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index d803c0b7a64e..b781dbed2165 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -1042,7 +1042,9 @@ static const struct acpi_device_id i3c_hci_acpi_match= [] =3D { MODULE_DEVICE_TABLE(acpi, i3c_hci_acpi_match); =20 static const struct platform_device_id i3c_hci_driver_ids[] =3D { - { .name =3D "intel-lpss-i3c", HCI_QUIRK_RPM_ALLOWED }, + { .name =3D "intel-lpss-i3c", HCI_QUIRK_RPM_ALLOWED | + HCI_QUIRK_RPM_IBI_ALLOWED | + HCI_QUIRK_RPM_PARENT_MANAGED }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(platform, i3c_hci_driver_ids); diff --git a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c b/drivers/i= 3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c index 17f30706eb48..d6bbc3f8cd2a 100644 --- a/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c +++ b/drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c @@ -200,6 +200,7 @@ static const struct mipi_i3c_hci_pci_info intel_mi_1_in= fo =3D { .id =3D {0, 1}, .instance_offset =3D {0, 0x400}, .instance_count =3D 2, + .control_instance_pm =3D true, }; =20 static const struct mipi_i3c_hci_pci_info intel_mi_2_info =3D { @@ -209,6 +210,7 @@ static const struct mipi_i3c_hci_pci_info intel_mi_2_in= fo =3D { .id =3D {2, 3}, .instance_offset =3D {0, 0x400}, .instance_count =3D 2, + .control_instance_pm =3D true, }; =20 static const struct mipi_i3c_hci_pci_info intel_si_2_info =3D { @@ -218,6 +220,7 @@ static const struct mipi_i3c_hci_pci_info intel_si_2_in= fo =3D { .id =3D {2}, .instance_offset =3D {0}, .instance_count =3D 1, + .control_instance_pm =3D true, }; =20 static int mipi_i3c_hci_pci_find_instance(struct mipi_i3c_hci_pci *hci, st= ruct device *dev) --=20 2.51.0