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Fri, 6 Mar 2026 00:00:48 -0800 From: To: , , , , , , , CC: , , , , , , , , , , , , , , "Srirangan Madhavan" Subject: [PATCH 3/5] PCI: Add virtual extended cap save buffer for CXL state Date: Fri, 6 Mar 2026 08:00:17 +0000 Message-ID: <20260306080026.116789-4-smadhavan@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260306080026.116789-1-smadhavan@nvidia.com> References: <20260306080026.116789-1-smadhavan@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B078:EE_|BL1PR12MB5706:EE_ X-MS-Office365-Filtering-Correlation-Id: afc25db9-655d-48d1-033d-08de7b568592 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|1800799024|7416014|82310400026; X-Microsoft-Antispam-Message-Info: HNrV41fduHGqEd39g+xNgxiBFTe+1WuAKfea2iMgJmpbbZgD8BkT5uRYoy3RmixXsSP4t3qukZ5ltABNNvM5mlaVQg+xJQlwsg4Vg3w6/794xUThIZtw6y/4xvEPGE7NkqyZhXAeMuz9Kyt1wqcH48BxP3vrs25lnvJ7u/mgw+LO3IxohuU551rTsShyZa3sLiG8QWHMYlarFq607pQ9mQwOKwphSE6GAopp9Zzgud6kvJcJm4EaUN4/mRD1gcCMxAr4/N5gw2bclq9fWIf0IksHzIqqHfa2bYK/KbZjZKtbVAxTj1OLKmjhUGiKtgEqBTUh6aem9/fhygiYUKErRw+92kYH1sNPg+nOZ3plzEkrefafvA1y5BrAPnjFlh0Sjhh1bKHc72ITWj+nkItTaMN5/VVuStyevMTMAp6YpLe466pkmRt5a5ImJjCSEU6bvyy8Fg2dN5ZrRFlomozFWcqCSjx8dJfY3ErHQd/9FbLiGjjRjPD+a+NnhoVWxA0STm6GNnkDemw6r5GJqB9ZyZMe0xDLgUrdWwXaw1ZeEiyqELuL7Bti+oAWFkC5b4K6SkOsukmXwkXLFdwKLLeuZLbYnNidfJ1K7KIWVyPbDxPs0Ea1xKGdjp0/arYqHlnjcWzKLQZAbXLihtXzRsSX8tLKoLcWNtImeeCuUaJJLWF7gwjlWtqagLkqCSImesBU2Yo4N42fsg1oxie/8PI7TzvdAIc4P/HNVmyBkNeZauWIHFAyZUWdfiS4e35y1p5UAnll1pvSG1yWHkVIN0Qtrg== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700016)(1800799024)(7416014)(82310400026);DIR:OUT;SFP:1101; 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charset="utf-8" From: Srirangan Madhavan Add pci_add_virtual_ext_cap_save_buffer() to allocate save buffers using virtual cap IDs (above PCI_EXT_CAP_ID_MAX) that don't require a real capability in config space. The existing pci_add_ext_cap_save_buffer() cannot be used for CXL DVSEC state because it calls pci_find_saved_ext_cap() which searches for a matching capability in PCI config space. The CXL state saved here is a synthetic snapshot (DVSEC+HDM) and should not be tied to a real extended-cap instance. A virtual extended-cap save buffer API (cap IDs above PCI_EXT_CAP_ID_MAX) allows PCI to track this state without a backing config space capability. Signed-off-by: Srirangan Madhavan --- drivers/pci/pci.c | 20 ++++++++++++++++++++ drivers/pci/pci.h | 18 ++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 8479c2e1f74f..dc8181f13864 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3446,6 +3446,26 @@ int pci_add_ext_cap_save_buffer(struct pci_dev *dev,= u16 cap, unsigned int size) return _pci_add_cap_save_buffer(dev, cap, true, size); } +int pci_add_virtual_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, + unsigned int size) +{ + struct pci_cap_saved_state *save_state; + + if (cap <=3D PCI_EXT_CAP_ID_MAX) + return -EINVAL; + + save_state =3D kzalloc(sizeof(*save_state) + size, GFP_KERNEL); + if (!save_state) + return -ENOMEM; + + save_state->cap.cap_nr =3D cap; + save_state->cap.cap_extended =3D true; + save_state->cap.size =3D size; + pci_add_saved_cap(dev, save_state); + + return 0; +} + /** * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities * @dev: the PCI device diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 13d998fbacce..05c57f1e4701 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -245,15 +245,33 @@ struct pci_cap_saved_state { struct pci_cap_saved_data cap; }; +/* + * Virtual extended cap ID for CXL DVSEC state in the cap save chain. + */ +#define PCI_EXT_CAP_ID_CXL_DVSEC_VIRTUAL 0xFFFF +static_assert(PCI_EXT_CAP_ID_MAX < PCI_EXT_CAP_ID_CXL_DVSEC_VIRTUAL); + void pci_allocate_cap_save_buffers(struct pci_dev *dev); void pci_free_cap_save_buffers(struct pci_dev *dev); int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int si= ze); int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size); +int pci_add_virtual_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, + unsigned int size); struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char c= ap); struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap); +#ifdef CONFIG_PCI_CXL +void pci_allocate_cxl_save_buffer(struct pci_dev *dev); +void pci_save_cxl_state(struct pci_dev *dev); +void pci_restore_cxl_state(struct pci_dev *dev); +#else +static inline void pci_allocate_cxl_save_buffer(struct pci_dev *dev) { } +static inline void pci_save_cxl_state(struct pci_dev *dev) { } +static inline void pci_restore_cxl_state(struct pci_dev *dev) { } +#endif + #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ #define PCI_PM_D3HOT_WAIT 10 /* msec */ #define PCI_PM_D3COLD_WAIT 100 /* msec */ -- 2.43.0