From nobody Thu Apr 9 18:03:03 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A8DA842F57C for ; Fri, 6 Mar 2026 16:47:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772815671; cv=none; b=MzYtuo6Z+RM5Z/UhXQqy426P1TudPTyyZR0HA5Zc3nNbcEhM4Nzsf+1mc9do3PhRA3I2csHCTI0A2rGg0/bR1eqOkaE2dRNgXgPlt+BmYR4uhWhcCRl8qeZC1KkYybzEI+h7vBX8MbktgigSiDdV9q25uTVvaLGUjG3h6Xfy76M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772815671; c=relaxed/simple; bh=I5lnRHVGhO47eC0F1oaZyDm7ZkFRRSTBKLhGEMk45GY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JHooU8fkKlHa9sj3PACyFP4eksiewYThOFUGtbHevNsQbk+VsG9DuUL6CmjyLg2NF3WCytsRTB3XqCB1v6J34gdaWPjMECuU3thPtUu8lTNqea7GGLPbyc15lILSsxXmT7RB0e4vs7pHFcyz5ZTXtTXEL3/W50+n36kGrlH1bVw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=PDBxg8JD; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=MXmojc+l; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="PDBxg8JD"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="MXmojc+l" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 626Fr99N550299 for ; Fri, 6 Mar 2026 16:47:46 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 8B2fY2szI51s2UktTG+lS/Bhx/xmTLE0O8Z2hjeZB3M=; b=PDBxg8JDCSiA3WVR enTPdP5d9XO9pAernapCAeIqryYtByS7W/S+OP3dCE1qp4zXuBhbtyPoKJ31jMSi rhliyrfKI93sRZ2kQ8+eYSzqrOUwJUmP9kb53KgcIVprxyvTA5NiF0/CoJ2tW9Bh Fc518ERGOumHD4cXKFr6QsASPvKhGn60bMs9LsdpvuUSIfw1ngNZoMlQ0PC4Y0oj 77cv3ifn7WEigftJpvm6MovP91psx4/bJG6NaZ3/U48toTmWp3k3LqU3hK7ptlWR yD7hyVVtbLKySjvddKqwUB5JgEUS/2z6TFFiJFbL51KKrVm8jjNTCA5vSKnSDO4+ AFRUrg== Received: from mail-qk1-f199.google.com (mail-qk1-f199.google.com [209.85.222.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cqruka69j-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 06 Mar 2026 16:47:46 +0000 (GMT) Received: by mail-qk1-f199.google.com with SMTP id af79cd13be357-8c711251ac5so5155903785a.1 for ; Fri, 06 Mar 2026 08:47:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1772815665; x=1773420465; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=8B2fY2szI51s2UktTG+lS/Bhx/xmTLE0O8Z2hjeZB3M=; b=MXmojc+lDpJo1lofXZV9qxB4Y344SH7n3y/z8ztkOjyknHr/K5DBEhRJhAjf8goqnJ sSlI3n9FfC0+bkqj71/f6ymYmhW8CzubkYhwOdiD4asM+GvAG6Cw40YMMMvgE+WJuVsl rS0TAHJNoGqvNVma4+NAU3ukjnzSJVL8b4q5snDLhW5Pa6rpxfqcUqELJVoJRk5C8Gxz ie19o9MCXeZV7saSQE04yaySGfi35uyXQnKoENetG+5m4OabESuGcMQ+8woQixfIUSgu AZSAsPc4DhxM0hcw2hB9ifaB3o/E5lS8VDejKalXEykO5qD6pnhhNT/dHUbIzKQg5dNx NOTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772815665; x=1773420465; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=8B2fY2szI51s2UktTG+lS/Bhx/xmTLE0O8Z2hjeZB3M=; b=QntP2HqJiCD3/UX5sJXojlg/pJD+q1vr0B+IzALWc7Ct+yMiDq3Py3MK5CXBXYJsA1 nyc/klaIhBxEVlxHOzRCWUt7tqM0bQJgOv2Zz2SE3ZXfisdAfkB6d1dISVpxmWb1EpIN ++oZqCsz6pHzdMnJuVapUb2VZbQ01Wf99aCHZiMOhGjkuGulKkY2FkCexdWk8KIg3WOg JB7uh+M0vlw6JlnUxEWt3xAEGQI+EfDVX+Pom+rseyqYBp1dlJmqEPucK0sJ+lWNMIDd KT7QMjFEVQFhZXwKuQliuMu8j4zPt15zhiOVZLHCtqHdxaRSAudZA7nRWwZi/kyiYGgf e0Xg== X-Forwarded-Encrypted: i=1; AJvYcCUQ5XSh1E5eXg5Y5mkTXPsv/pBothwW1Eel+lyGJ0jaVN+TFKU2Kbv4/6DANeUPUUCxi9Yk9+vC53bNuwQ=@vger.kernel.org X-Gm-Message-State: AOJu0YybZZ79y3UDcpCt253f3w4ESmEVSX7AYZOk3xQH+JmoOWN2L59l oJE7YuENsw5Si1sZ2CgoreLp+NVa/G1f7ntKM4zcn138B7n29xZSyiqTSxSY/2630fli93hMsLE L8FwftXAwG5IUOrjJei0iK8u7lLOddWEvuCzJmR6Tl5DYTl5dKjtV36gnvdtDuyw6c6nO2HjJoJ g= X-Gm-Gg: ATEYQzxwEJbunZsbFbd3i0ARiGQa1wMi3aYo8+rPE7Ydj2n0bsqpF0vsV/3ImPrDUWU mDesC8E7vgo7M3k6N9itSYcqdnaPxC2e/vj29Dhw+Zi1OsDfgAmiDqL62PRiatTSHGMKgj0INNQ WQYpDIHGI2ZUAdgZ14oj5P1qSKEWjWS5g3HT4sOuK3p00I/iq6W82mnEaxUSgcozRT4Zq5m58X8 NCj4f6bpeYLgBIpd5Fc8rDyrg7o3wR5YGWoIKnS2U9ZxxNuzubJaW4GfVxz9D0fM2iuJZlg4owW w4+8zX3dj6ChzcbEQuaBepopwjUgaeO4sKa9XN56oR3P4viMTBG3XqGwiH6qCm6LzDLpWw/YSzI +Uyendlz2RKD0Kna+GsRsYOF1GLG2XmdL/NL5Hj/P2/IM4MOcYHWitRhJ5h/+DCYRags8uMfIg8 92PbBKIXtUcTIkHXZTB+XfwqvC+Q2hUnSG5Ko= X-Received: by 2002:a05:620a:4588:b0:8c7:7a3:501c with SMTP id af79cd13be357-8cd6d4285famr320359885a.52.1772815665308; Fri, 06 Mar 2026 08:47:45 -0800 (PST) X-Received: by 2002:a05:620a:4588:b0:8c7:7a3:501c with SMTP id af79cd13be357-8cd6d4285famr320355185a.52.1772815664713; Fri, 06 Mar 2026 08:47:44 -0800 (PST) Received: from umbar.lan (2001-14ba-a073-af00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a073:af00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a13eaebd0asm213804e87.51.2026.03.06.08.47.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 08:47:43 -0800 (PST) From: Dmitry Baryshkov Date: Fri, 06 Mar 2026 18:47:25 +0200 Subject: [PATCH 19/24] soc: qcom: ubwc: drop ubwc_dec_version Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260306-ubwc-rework-v1-19-9cfdff12f2bb@oss.qualcomm.com> References: <20260306-ubwc-rework-v1-0-9cfdff12f2bb@oss.qualcomm.com> In-Reply-To: <20260306-ubwc-rework-v1-0-9cfdff12f2bb@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=7985; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=I5lnRHVGhO47eC0F1oaZyDm7ZkFRRSTBKLhGEMk45GY=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBpqwUP2OplnHHja4BRO4yhK/fj0N6AFxrAN6uGe IpWOa6IgaeJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaasFDwAKCRCLPIo+Aiko 1e8+B/9VHHMj3Z1WJ6gHWxG4HrplPXaGNkLWk9J7IRA0MoH+jP5w3tXUEHYfYE/UJuj10kDg9k+ WOXq50TAQT7uM9FFbba9r+ufgQEtnfEgC5rlskKCNglsQSKewLV1LQT1bOdck2lHLSNn8wCz9FK yCRcNHJe/2PqXdT5Md09RiHWOvhWLLzbIy0UdrOy/l5R56Dmc0G2Cog+L9/eL95sDiWDj+ZR6Js HBvI18TIlErDhTDE9Kgal48p9fTf0KTEJy2rbg66vTtl/ry9m7b/JLP3CJ9BKPRpW3KgbfFFq7/ CAKtTaO1vaTWJi8sNyBMM4SlTOQ3HkCU61Y8QYwjsg9Yrwtg X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA2MDE1OSBTYWx0ZWRfX2Ce24aCWAs7s GfAQUH7ohuUYS6yu91mrPBqMuaDNbQqEViwADfw0mkztIZ1c8semE5/CHHZBHFgPEwrBsdc5ZBI VFtjHnto+EU6o2//Ch9X6p+siLEvsDgcrEpLL6b3PC0mZ4aYCZY+lcDS8epwA/WTAm5HPtlAMQk wXnpnTcJCBcEaHYzrlw1cRWhNUZdCH9Df44O2wHWZFvqt+eve6Bm0utS6RT0l9Hzohedsuh7Ton bVHzmaBMc3lKnKrbxj5S/vvQ33QCLlKoR3ZoJPtkSzkQf3aOtT+8geP26puypZz9Qf2jfEPGrPF v/KKX1QvTG2/v1K/nem94uTgeJXtZD1Cry7jmyVcESbgpHoOXsZ8qE0XM/J8PBppWMfm37hbPVY HfzbL6qaTGI7RZ0ey3zeEHnRUCjW/eEMc9T+K8rmFScJNy9hct/EGd3rRifKuRtvLl9mUbUllgd HJUvWfSIh8qT0ofAOTw== X-Proofpoint-ORIG-GUID: UUnudMasCdYB_kn4v8S0jZTkDRBau5HK X-Authority-Analysis: v=2.4 cv=DvZbOW/+ c=1 sm=1 tr=0 ts=69ab0532 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=LGEa-qlQBoucZRe8vqkA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-GUID: UUnudMasCdYB_kn4v8S0jZTkDRBau5HK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-06_05,2026-03-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 bulkscore=0 adultscore=0 suspectscore=0 clxscore=1015 phishscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603060159 The ubwc_dec_version field has been inherited from the MDSS driver and it is equal to the version of the UBWC decoder in the display block only. Other IP Cores can have different UBWC decoders and so the version would vary between blocks. As the value is no longer used as is not relevant to other UBWC database consumers, drop it from the UBWC database. Signed-off-by: Dmitry Baryshkov --- drivers/soc/qcom/ubwc_config.c | 22 ---------------------- include/linux/soc/qcom/ubwc.h | 2 -- 2 files changed, 24 deletions(-) diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index e63daf748e30..c5c7fcb4d013 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -18,7 +18,6 @@ static const struct qcom_ubwc_cfg_data no_ubwc_data =3D { =20 static const struct qcom_ubwc_cfg_data kaanapali_data =3D { .ubwc_enc_version =3D UBWC_6_0, - .ubwc_dec_version =3D UBWC_6_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, @@ -28,7 +27,6 @@ static const struct qcom_ubwc_cfg_data kaanapali_data =3D= { =20 static const struct qcom_ubwc_cfg_data msm8937_data =3D { .ubwc_enc_version =3D UBWC_1_0, - .ubwc_dec_version =3D UBWC_1_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, @@ -37,7 +35,6 @@ static const struct qcom_ubwc_cfg_data msm8937_data =3D { =20 static const struct qcom_ubwc_cfg_data msm8998_data =3D { .ubwc_enc_version =3D UBWC_1_0, - .ubwc_dec_version =3D UBWC_1_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, @@ -51,7 +48,6 @@ static const struct qcom_ubwc_cfg_data qcm2290_data =3D { =20 static const struct qcom_ubwc_cfg_data sa8775p_data =3D { .ubwc_enc_version =3D UBWC_4_0, - .ubwc_dec_version =3D UBWC_4_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, .highest_bank_bit =3D 13, @@ -60,7 +56,6 @@ static const struct qcom_ubwc_cfg_data sa8775p_data =3D { =20 static const struct qcom_ubwc_cfg_data sar2130p_data =3D { .ubwc_enc_version =3D UBWC_3_0, /* 4.0.2 in hw */ - .ubwc_dec_version =3D UBWC_4_3, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, @@ -70,7 +65,6 @@ static const struct qcom_ubwc_cfg_data sar2130p_data =3D { =20 static const struct qcom_ubwc_cfg_data sc7180_data =3D { .ubwc_enc_version =3D UBWC_2_0, - .ubwc_dec_version =3D UBWC_2_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, @@ -79,7 +73,6 @@ static const struct qcom_ubwc_cfg_data sc7180_data =3D { =20 static const struct qcom_ubwc_cfg_data sc7280_data =3D { .ubwc_enc_version =3D UBWC_3_0, - .ubwc_dec_version =3D UBWC_4_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, @@ -89,7 +82,6 @@ static const struct qcom_ubwc_cfg_data sc7280_data =3D { =20 static const struct qcom_ubwc_cfg_data sc8180x_data =3D { .ubwc_enc_version =3D UBWC_3_0, - .ubwc_dec_version =3D UBWC_3_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 16, @@ -98,7 +90,6 @@ static const struct qcom_ubwc_cfg_data sc8180x_data =3D { =20 static const struct qcom_ubwc_cfg_data sc8280xp_data =3D { .ubwc_enc_version =3D UBWC_4_0, - .ubwc_dec_version =3D UBWC_4_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, @@ -108,7 +99,6 @@ static const struct qcom_ubwc_cfg_data sc8280xp_data =3D= { =20 static const struct qcom_ubwc_cfg_data sdm670_data =3D { .ubwc_enc_version =3D UBWC_2_0, - .ubwc_dec_version =3D UBWC_2_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, @@ -116,7 +106,6 @@ static const struct qcom_ubwc_cfg_data sdm670_data =3D { =20 static const struct qcom_ubwc_cfg_data sdm845_data =3D { .ubwc_enc_version =3D UBWC_2_0, - .ubwc_dec_version =3D UBWC_2_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 15, @@ -124,7 +113,6 @@ static const struct qcom_ubwc_cfg_data sdm845_data =3D { =20 static const struct qcom_ubwc_cfg_data sm6115_data =3D { .ubwc_enc_version =3D UBWC_1_0, - .ubwc_dec_version =3D UBWC_2_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, @@ -134,7 +122,6 @@ static const struct qcom_ubwc_cfg_data sm6115_data =3D { =20 static const struct qcom_ubwc_cfg_data sm6125_data =3D { .ubwc_enc_version =3D UBWC_1_0, - .ubwc_dec_version =3D UBWC_3_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL1 | UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, @@ -143,7 +130,6 @@ static const struct qcom_ubwc_cfg_data sm6125_data =3D { =20 static const struct qcom_ubwc_cfg_data sm6150_data =3D { .ubwc_enc_version =3D UBWC_2_0, - .ubwc_dec_version =3D UBWC_2_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, @@ -151,7 +137,6 @@ static const struct qcom_ubwc_cfg_data sm6150_data =3D { =20 static const struct qcom_ubwc_cfg_data sm6350_data =3D { .ubwc_enc_version =3D UBWC_2_0, - .ubwc_dec_version =3D UBWC_2_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, @@ -160,7 +145,6 @@ static const struct qcom_ubwc_cfg_data sm6350_data =3D { =20 static const struct qcom_ubwc_cfg_data sm7150_data =3D { .ubwc_enc_version =3D UBWC_2_0, - .ubwc_dec_version =3D UBWC_2_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 14, @@ -168,7 +152,6 @@ static const struct qcom_ubwc_cfg_data sm7150_data =3D { =20 static const struct qcom_ubwc_cfg_data sm8150_data =3D { .ubwc_enc_version =3D UBWC_3_0, - .ubwc_dec_version =3D UBWC_3_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit =3D 15, @@ -176,7 +159,6 @@ static const struct qcom_ubwc_cfg_data sm8150_data =3D { =20 static const struct qcom_ubwc_cfg_data sm8250_data =3D { .ubwc_enc_version =3D UBWC_4_0, - .ubwc_dec_version =3D UBWC_4_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, @@ -187,7 +169,6 @@ static const struct qcom_ubwc_cfg_data sm8250_data =3D { =20 static const struct qcom_ubwc_cfg_data sm8350_data =3D { .ubwc_enc_version =3D UBWC_4_0, - .ubwc_dec_version =3D UBWC_4_0, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, @@ -198,7 +179,6 @@ static const struct qcom_ubwc_cfg_data sm8350_data =3D { =20 static const struct qcom_ubwc_cfg_data sm8550_data =3D { .ubwc_enc_version =3D UBWC_4_0, - .ubwc_dec_version =3D UBWC_4_3, .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread =3D true, @@ -209,7 +189,6 @@ static const struct qcom_ubwc_cfg_data sm8550_data =3D { =20 static const struct qcom_ubwc_cfg_data sm8750_data =3D { .ubwc_enc_version =3D UBWC_5_0, - .ubwc_dec_version =3D UBWC_5_0, .ubwc_swizzle =3D 6, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ @@ -219,7 +198,6 @@ static const struct qcom_ubwc_cfg_data sm8750_data =3D { =20 static const struct qcom_ubwc_cfg_data glymur_data =3D { .ubwc_enc_version =3D UBWC_5_0, - .ubwc_dec_version =3D UBWC_5_0, .ubwc_swizzle =3D 0, .ubwc_bank_spread =3D true, /* TODO: highest_bank_bit =3D 15 for LP_DDR4 */ diff --git a/include/linux/soc/qcom/ubwc.h b/include/linux/soc/qcom/ubwc.h index ddd7b15d9ff1..c5f049eab07d 100644 --- a/include/linux/soc/qcom/ubwc.h +++ b/include/linux/soc/qcom/ubwc.h @@ -13,8 +13,6 @@ =20 struct qcom_ubwc_cfg_data { u32 ubwc_enc_version; - /* Can be read from MDSS_BASE + 0x58 */ - u32 ubwc_dec_version; =20 /** * @ubwc_swizzle: Whether to enable level 1, 2 & 3 bank swizzling. --=20 2.47.3