From nobody Thu Apr 9 17:59:34 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 490CF3F0753 for ; Fri, 6 Mar 2026 15:47:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772812057; cv=none; b=C5rfH3IJieKL5Jq3NBfaZoK0Oa/GFY0WA/dTIOlf2rzXmVxyffQJBrD9zC3pRru3R/MSRTNCQAG/2In0gaXc5IU0gdroHjSrZz0Sjjfg+33B82a/Om7aKWILbOM935bhnjiBd3U7IbhhYI8nkl6ONeVz7Q7sIC73o2+44YwZ/PI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772812057; c=relaxed/simple; bh=5mXZFESKLVZc5H2Ki6FhqRq9OaT7bl56nHZat6uRwdE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ppZjiiX2EOQrpczGeyZUoy95E/3a/lbk+Q+gpOX2BjSkN1myeFeJar33DyPl/4nGGkpAj+qnnupYVRXKFJKgy9rpBOrHwKd+u7vuBo9y9cYPMZlkzj1ozD6ZltlYbuUiDWeKvIDRZGoHVw19uEF60MnpgX6i9ZA2UAk8jnvEqP4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=LnELIkLo; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Eq/ekWim; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="LnELIkLo"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Eq/ekWim" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 626FTlwQ496296 for ; Fri, 6 Mar 2026 15:47:34 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= I9NS1s9pNWD9VPVBtroebVNHKvwsQDB1YstL1xWHubc=; b=LnELIkLop1fu6pIH jaLsH5zRt+87vuzmX4G6SqA7Am9wwXuzDVsYLKrl4f/xj9HjIJY3sJwZQ9DNBEmt zLR8wmkQVOkppxXceExeudSbDsUINXBWfu4vtQuOofFmsbi0gwg7WAcgzYt22v28 r89tl+DWEaMhvReV/21QEKhtzmtqTl1BSIKxhkXGuTYVB7Z7vq3WZM4C179kiB5i KRRgMs8urHBofKJLZ0l4yLMOm3kbAIKb5GEw5OkbyjfFery0ORK2Y+hd72btkGg+ 5DuGBlpXvP8S0REHbU8Pk81jmYmDRgKr+s3aasDHvPNDwPnz/nvyGSFQPjw2i3Lw lVyeNA== Received: from mail-qk1-f198.google.com (mail-qk1-f198.google.com [209.85.222.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cqruk9yfv-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 06 Mar 2026 15:47:34 +0000 (GMT) Received: by mail-qk1-f198.google.com with SMTP id af79cd13be357-8cb3b6b37d8so4927676385a.3 for ; Fri, 06 Mar 2026 07:47:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1772812054; x=1773416854; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=I9NS1s9pNWD9VPVBtroebVNHKvwsQDB1YstL1xWHubc=; b=Eq/ekWimw84XsZh1GV1eDIVU6LokduTgOLluRD9UBO7FMy0J9VKyeTEaw50Rd8Chzk x2WHHTxwdUIzkuCO2ggMa2dfh9Lo1rA9DDCy63+BK5FL3lqZXUUR2QB7feSZa3Bm6dUC JZekZYcMo5hirMx4TIo2frsGzUlfeVonTRRQxDlJ/gL0E/S7hjXNSvbDbjM3VIdTANm5 tqeL2v3gG1eJJlN+3NYhqB0RkupVKcB9/2irQ1uffo8ovg6DKI5o/+20XBpVlvtp60FJ ZE9FerT6t3DGXPDTPDlv3h3y/hsMQxRxO2ioEIwejDWtp7+egsGGzgea0GXUoX49dOcX bFxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772812054; x=1773416854; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=I9NS1s9pNWD9VPVBtroebVNHKvwsQDB1YstL1xWHubc=; b=fLWpNxh74ImBDm6jipBNUA/l6v6qfRbuALApoK3P3pShvaMt3h84ZPXzDqex+Ma6Di GLbEs+waYUg41T924yWbjoectR6IwpNt1PIWPC5xVNNeOkediuFlSKY84/8IlhJHxwwq JpjK1BJvWlPCk/7y5XjVh5MzJ4lolEAySRfEEGsAriRKzuaableQtn8fpEBcjY6vVdif O2Rek0ESETq4D6C5mxAoQ1HlTCD+xsGn/lKLQIgNJo1Yp/d66/n8OWcuamWbcxLxQ100 ujdSQ97B5N+K6Ta8I1Ffq06LOlpyWAa0SkM2vMfUEsHx6woZvA0B9Xq+S5Fi+Yr0X6K2 nGlA== X-Forwarded-Encrypted: i=1; AJvYcCWwUEbEvflbVbBIMuAPMIcbG0t5iho91BqNQa89MVCdYaChDSa9PEWm3pd9JouVCjVIaCMgTWi/s54RpFc=@vger.kernel.org X-Gm-Message-State: AOJu0YyhytEPu84ICcHYFOlsqJvyBLeWBq/wjlVnJ6IQCqyrTusn9a/d A258GTjwqtfrwWIAmcgsNEiFOKw44HRHCi2U73eU39gmPzIaakgAgWB2FcKuzCeedNmX6S0IjTs EEWlET/gUYbC2YVAQ+rCqepcIriXMFNdr9aQqVqGptgw9qrHU9Fh1zEADOXhTIufvHU0= X-Gm-Gg: ATEYQzwvNsECcxhn5UXgxl3MG0T5Fq/hbhebps57/eJIBEDkkMLbST1Sb9PQxt7fO24 6c6WCx6mNSw+h1eUvhNpW3dAur0pgYZ+YFY3wCQt+TYoqTVJ+sDTgtN0MjZEwVq8ohxgnhSvmjb BWibPCf1mI3guuv6kYxsZHh5BpRkYQin3U58bl/tEZN6I4PFLzJy2t956ulMNvszLVeSFltAmSD Ldlhf1KTSW5a+7LBjPgj2ykVdfOA1Eo/q5IjtJXwGXutk+SLMNeTC1p50FYjNi9mMi/qzhHmI43 HFVuPgN41voT9Qu5rX4KeOEDJ0RPOIQtEAEOl2Loa0EmbzWrXFfiRLlNGZ5njkzpQDIhJfmJ2gc lllkqPMFgMmbAao7CgjOJp0LLFPjz2mQoeLi7SOGHOAZMEfcFMQ8G X-Received: by 2002:a05:620a:4588:b0:8c9:ea1c:f21e with SMTP id af79cd13be357-8cd6d40b0a0mr304592985a.10.1772812053637; Fri, 06 Mar 2026 07:47:33 -0800 (PST) X-Received: by 2002:a05:620a:4588:b0:8c9:ea1c:f21e with SMTP id af79cd13be357-8cd6d40b0a0mr304584585a.10.1772812053002; Fri, 06 Mar 2026 07:47:33 -0800 (PST) Received: from brgl-qcom.local ([2a01:cb1d:dc:7e00:6d2b:ebde:c946:11eb]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439dae35cf7sm5122767f8f.26.2026.03.06.07.47.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 07:47:32 -0800 (PST) From: Bartosz Golaszewski Date: Fri, 06 Mar 2026 16:46:45 +0100 Subject: [PATCH net-next v7 7/7] net: stmmac: qcom-ethqos: add support for sa8255p Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260306-qcom-sa8255p-emac-v7-7-d6a3013094b7@oss.qualcomm.com> References: <20260306-qcom-sa8255p-emac-v7-0-d6a3013094b7@oss.qualcomm.com> In-Reply-To: <20260306-qcom-sa8255p-emac-v7-0-d6a3013094b7@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Vinod Koul , Giuseppe Cavallaro , Jose Abreu , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Matthew Gerlach , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Keguang Zhang , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Jan Petrous , s32@nxp.com, Romain Gantois , Lad Prabhakar , Heiko Stuebner , Chen Wang , Inochi Amaoto , Emil Renner Berthing , Minda Chen , Drew Fustini , Guo Ren , Fu Wei , Nobuhiro Iwamatsu , Geert Uytterhoeven , Magnus Damm , Maxime Ripard , Shuang Liang , Zhi Li , Shangjuan Wei , "G. Jaya Kumaran" , Clark Wang , Linux Team , Frank Li , David Wu , Samin Guo , Christophe Roullier , Swathi K S , Bartosz Golaszewski , Mohd Ayaan Anwar Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Drew Fustini , linux-sunxi@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-mips@vger.kernel.org, imx@lists.linux.dev, linux-renesas-soc@vger.kernel.org, linux-rockchip@lists.infradead.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, brgl@kernel.org, Bartosz Golaszewski , Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11062; i=bartosz.golaszewski@oss.qualcomm.com; h=from:subject:message-id; bh=BKhKJbICc8tI75o/engfT3L3gUjtRZVnMoUMnjfOnYM=; b=owEBbQKS/ZANAwAKAQWdLsv/NoTDAcsmYgBpqvbxEYxj6MZAAMZo860nypNVfQKsnyjcfWK0/ aDMuIsnoxuJAjMEAAEKAB0WIQSR5RMt5bVGHXuiZfwFnS7L/zaEwwUCaar28QAKCRAFnS7L/zaE wychD/wP2KGziFxXaHa0/fP7oDwaE6O0o7aCs3po4B6+ZVEGXUKPJmOAJ22pZPgKNyBVPSQ67Vt wJ3xZhWR0vqqWhQX1H/2EBiHBD+KWnPJq10dqzxYJFwc24bTpTvF5tGpUxzzyciU6DZlf7ssNmI 90JgRVXBmpKJ85lETVVCc+0eAmddOj6wjR2ubl4udouuD/J3o90DS0AP3HNdgdoyAOw/x2bKW1K 3pF7CD7/efEWW42cY0h7GYUwjTRcJ1/aqB0d00Dyns+Ex7I871T1v2osXRWtl448wXk/J8TmCHN buQpatkND14BFbc8ZQqidsCoE5jnNLsM0BoNpCQLi2eGrYEZNDyZUMLGqmz/eK9qP4QYoxrYbF/ COvKuxW2bLw37Bntpd5UWf1ih+BPu5Y6R4i4W4r2XIOEc40k/cy0uMNsaRLuZ1ToBCt1SWqGYVj 4OL3IUS5Fg1Dvg0Jkmydf3pM+fTxXFsqm8TwgxR/EAAvgpl+KTFIUhQEmKzmOnaP7MqajSC327d vFF2nSjwy7vhyEz/wDRoFRLA3FmmWRAwigxxi0Dk52BhSMqrv7PtdCiJQ065Cl9aDw10IGSyyj6 V9Kk9UChOFFo1cHvhQym6wqG3Ju5Few6KPD6WQb88Yq2pl7pwSpqXCJ+6jHbL1FhRMgdoCg9OZ/ 1IfCmLd3qqtmHpQ== X-Developer-Key: i=bartosz.golaszewski@oss.qualcomm.com; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA2MDE0NiBTYWx0ZWRfX9iJ6050rU+ZO n3i8p5FqkCRzQomz9IB83qlS8OHcanB9raN2wPqy5zPaO24WTgcQNok2dX3Swy96FodWFevcSEy CizN90R60xseg7LCMzaV4o0fEcgT2P0whSe2XbqWSXa8drXqg8BFYGR3aq/VvS/zpLAm1ealzH/ LX1HIhwREkER7DTY6F6rylh2dKeHIykiAz5pxRaKO2fFfF66yO1d2jNUnpDH4nZAqd3qS6frtNR SXLG67SVwErsDlGgz0mCJ1cTqnfKNzNq0+sZOsl9b+GWHZjF5j9AdhmGOVOub2ifHS7dV/HqBcL KLHckMP3YfSS9JhGu6u/oBFhYhyzD/bdJNK9rAr15tIo2asZJNqkUlb/bI7d/Il/kU/NBiqlG2i +9XmGpIdcQlJ3eJo0WKMkZTMWU5NgNXm76qi4J/Cb5teTnAUrupKsGhYn8HAP6t/8F7QDCJub7F hXlTPnjFXNG4Thx+w4g== X-Proofpoint-ORIG-GUID: RFUu50WUKl72RBAVuKigZg-yRexSPUd5 X-Authority-Analysis: v=2.4 cv=DvZbOW/+ c=1 sm=1 tr=0 ts=69aaf716 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=gYhETRYomtM5McKHAMIA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: RFUu50WUKl72RBAVuKigZg-yRexSPUd5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-06_04,2026-03-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 bulkscore=0 adultscore=0 suspectscore=0 clxscore=1015 phishscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603060146 From: Bartosz Golaszewski Extend the driver to support a new model - sa8255p. Unlike the previously supported variants, this one's power management is done in the firmware using SCMI. This is modeled in linux using power domains so add support for them. Signed-off-by: Bartosz Golaszewski Signed-off-by: Bartosz Golaszewski --- .../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 230 +++++++++++++++++= +--- 1 file changed, 205 insertions(+), 25 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/driv= ers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c index 038ca4da3cff4eaac1d1255573f32e0c87701e78..64f2b5dd4110765fa0931e3e5ca= 1c98d9d906bb9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 #include "stmmac.h" #include "stmmac_platform.h" @@ -81,6 +83,13 @@ =20 #define SGMII_10M_RX_CLK_DVDR 0x31 =20 +enum ethqos_pd_selector { + ETHQOS_PD_CORE =3D 0, + ETHQOS_PD_MDIO, + ETHQOS_PD_SERDES, + ETHQOS_NUM_PDS, +}; + struct ethqos_emac_por { unsigned int offset; unsigned int value; @@ -98,6 +107,9 @@ struct ethqos_emac_driver_data { =20 struct ethqos_emac_pm_data { const char *link_clk_name; + bool use_domains; + struct dev_pm_domain_attach_data pd; + unsigned int clk_ptp_rate; }; =20 struct ethqos_emac_match_data { @@ -111,12 +123,19 @@ struct ethqos_emac_pm_ctx { struct phy *serdes_phy; }; =20 +struct ethqos_emac_pd_ctx { + struct dev_pm_domain_list *pd_list; +}; + struct qcom_ethqos { struct platform_device *pdev; void __iomem *rgmii_base; int (*configure_func)(struct qcom_ethqos *ethqos, int speed); =20 - struct ethqos_emac_pm_ctx pm; + union { + struct ethqos_emac_pm_ctx pm; + struct ethqos_emac_pd_ctx pd; + }; phy_interface_t phy_mode; int serdes_speed; int (*set_serdes_speed)(struct qcom_ethqos *ethqos); @@ -340,6 +359,25 @@ static const struct ethqos_emac_match_data emac_sa8775= p_data =3D { .pm_data =3D &emac_sa8775p_pm_data, }; =20 +static const char * const emac_sa8255p_pd_names[] =3D { + "core", "mdio", "serdes" +}; + +static const struct ethqos_emac_pm_data emac_sa8255p_pm_data =3D { + .pd =3D { + .pd_flags =3D PD_FLAG_NO_DEV_LINK, + .pd_names =3D emac_sa8255p_pd_names, + .num_pd_names =3D ETHQOS_NUM_PDS, + }, + .use_domains =3D true, + .clk_ptp_rate =3D 230400000, +}; + +static const struct ethqos_emac_match_data emac_sa8255p_data =3D { + .drv_data =3D &emac_v4_0_0_data, + .pm_data =3D &emac_sa8255p_pm_data, +}; + static int ethqos_dll_configure(struct qcom_ethqos *ethqos) { struct device *dev =3D ðqos->pdev->dev; @@ -406,6 +444,28 @@ static int ethqos_dll_configure(struct qcom_ethqos *et= hqos) return 0; } =20 +static int qcom_ethqos_domain_on(struct qcom_ethqos *ethqos, + enum ethqos_pd_selector sel) +{ + struct device *dev =3D ethqos->pd.pd_list->pd_devs[sel]; + int ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + dev_err(ðqos->pdev->dev, + "Failed to enable the power domain for %s\n", + dev_name(dev)); + return ret; +} + +static void qcom_ethqos_domain_off(struct qcom_ethqos *ethqos, + enum ethqos_pd_selector sel) +{ + struct device *dev =3D ethqos->pd.pd_list->pd_devs[sel]; + + pm_runtime_put_sync(dev); +} + static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed) { struct device *dev =3D ðqos->pdev->dev; @@ -622,6 +682,13 @@ static int ethqos_set_serdes_speed_phy(struct qcom_eth= qos *ethqos) return phy_set_speed(ethqos->pm.serdes_phy, ethqos->serdes_speed); } =20 +static int ethqos_set_serdes_speed_pd(struct qcom_ethqos *ethqos) +{ + struct device *dev =3D ethqos->pd.pd_list->pd_devs[ETHQOS_PD_SERDES]; + + return dev_pm_opp_set_level(dev, ethqos->serdes_speed); +} + static void ethqos_set_serdes_speed(struct qcom_ethqos *ethqos, int speed) { if (ethqos->serdes_speed !=3D speed) { @@ -719,6 +786,28 @@ static void qcom_ethqos_serdes_powerdown(struct net_de= vice *ndev, void *priv) phy_exit(ethqos->pm.serdes_phy); } =20 +static int qcom_ethqos_pd_serdes_powerup(struct net_device *ndev, void *pr= iv) +{ + struct qcom_ethqos *ethqos =3D priv; + struct device *dev =3D ethqos->pd.pd_list->pd_devs[ETHQOS_PD_SERDES]; + int ret; + + ret =3D qcom_ethqos_domain_on(ethqos, ETHQOS_PD_SERDES); + if (ret < 0) + return ret; + + return dev_pm_opp_set_level(dev, ethqos->serdes_speed); +} + +static void qcom_ethqos_pd_serdes_powerdown(struct net_device *ndev, void = *priv) +{ + struct qcom_ethqos *ethqos =3D priv; + struct device *dev =3D ethqos->pd.pd_list->pd_devs[ETHQOS_PD_SERDES]; + + dev_pm_opp_set_level(dev, 0); + qcom_ethqos_domain_off(ethqos, ETHQOS_PD_SERDES); +} + static int ethqos_clks_config(void *priv, bool enabled) { struct qcom_ethqos *ethqos =3D priv; @@ -749,6 +838,68 @@ static void ethqos_clks_disable(void *data) ethqos_clks_config(data, false); } =20 +static void ethqos_disable_serdes(void *data) +{ + struct qcom_ethqos *ethqos =3D data; + + qcom_ethqos_domain_off(ethqos, ETHQOS_PD_SERDES); +} + +static int ethqos_pd_clks_config(void *priv, bool enabled) +{ + struct qcom_ethqos *ethqos =3D priv; + int ret =3D 0; + + if (enabled) { + ret =3D qcom_ethqos_domain_on(ethqos, ETHQOS_PD_MDIO); + if (ret < 0) { + dev_err(ðqos->pdev->dev, + "Failed to enable the MDIO power domain\n"); + return ret; + } + + ethqos_set_func_clk_en(ethqos); + } else { + qcom_ethqos_domain_off(ethqos, ETHQOS_PD_MDIO); + } + + return ret; +} + +static int qcom_ethqos_pd_init(struct device *dev, void *priv) +{ + struct qcom_ethqos *ethqos =3D priv; + int ret; + + /* + * Enable functional clock to prevent DMA reset after timeout due + * to no PHY clock being enabled after the hardware block has been + * power cycled. The actual configuration will be adjusted once + * ethqos_fix_mac_speed() is called. + */ + ethqos_set_func_clk_en(ethqos); + + ret =3D qcom_ethqos_domain_on(ethqos, ETHQOS_PD_CORE); + if (ret) + return ret; + + ret =3D qcom_ethqos_domain_on(ethqos, ETHQOS_PD_MDIO); + if (ret) { + qcom_ethqos_domain_off(ethqos, ETHQOS_PD_CORE); + return ret; + } + + return 0; +} + +static void qcom_ethqos_pd_exit(struct device *dev, void *data) +{ + struct qcom_ethqos *ethqos =3D data; + + qcom_ethqos_domain_off(ethqos, ETHQOS_PD_MDIO); + qcom_ethqos_domain_off(ethqos, ETHQOS_PD_CORE); +} + static void ethqos_ptp_clk_freq_config(struct stmmac_priv *priv) { struct plat_stmmacenet_data *plat_dat =3D priv->plat; @@ -789,8 +940,6 @@ static int qcom_ethqos_probe(struct platform_device *pd= ev) "dt configuration failed\n"); } =20 - plat_dat->clks_config =3D ethqos_clks_config; - ethqos =3D devm_kzalloc(dev, sizeof(*ethqos), GFP_KERNEL); if (!ethqos) return -ENOMEM; @@ -830,28 +979,63 @@ static int qcom_ethqos_probe(struct platform_device *= pdev) ethqos->rgmii_config_loopback_en =3D drv_data->rgmii_config_loopback_en; ethqos->has_emac_ge_3 =3D drv_data->has_emac_ge_3; ethqos->needs_sgmii_loopback =3D drv_data->needs_sgmii_loopback; + ethqos->serdes_speed =3D SPEED_1000; =20 - ethqos->pm.link_clk =3D devm_clk_get(dev, clk_name); - if (IS_ERR(ethqos->pm.link_clk)) - return dev_err_probe(dev, PTR_ERR(ethqos->pm.link_clk), - "Failed to get link_clk\n"); + if (pm_data && pm_data->use_domains) { + ethqos->set_serdes_speed =3D ethqos_set_serdes_speed_pd; =20 - ret =3D ethqos_clks_config(ethqos, true); - if (ret) - return ret; + ret =3D devm_pm_domain_attach_list(dev, &pm_data->pd, + ðqos->pd.pd_list); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to attach power domains\n"); =20 - ret =3D devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos); - if (ret) - return ret; + plat_dat->clks_config =3D ethqos_pd_clks_config; + plat_dat->serdes_powerup =3D qcom_ethqos_pd_serdes_powerup; + plat_dat->serdes_powerdown =3D qcom_ethqos_pd_serdes_powerdown; + plat_dat->exit =3D qcom_ethqos_pd_exit; + plat_dat->init =3D qcom_ethqos_pd_init; + plat_dat->clk_ptp_rate =3D pm_data->clk_ptp_rate; =20 - ethqos->pm.serdes_phy =3D devm_phy_optional_get(dev, "serdes"); - if (IS_ERR(ethqos->pm.serdes_phy)) - return dev_err_probe(dev, PTR_ERR(ethqos->pm.serdes_phy), - "Failed to get serdes phy\n"); + ret =3D qcom_ethqos_domain_on(ethqos, ETHQOS_PD_SERDES); + if (ret) + return dev_err_probe(dev, ret, + "Failed to enable the serdes power domain\n"); + + ret =3D devm_add_action_or_reset(dev, ethqos_disable_serdes, ethqos); + if (ret) + return ret; + } else { + ethqos->set_serdes_speed =3D ethqos_set_serdes_speed_phy; + + ethqos->pm.link_clk =3D devm_clk_get(dev, clk_name); + if (IS_ERR(ethqos->pm.link_clk)) + return dev_err_probe(dev, PTR_ERR(ethqos->pm.link_clk), + "Failed to get link_clk\n"); + + ret =3D ethqos_clks_config(ethqos, true); + if (ret) + return ret; + + ret =3D devm_add_action_or_reset(dev, ethqos_clks_disable, ethqos); + if (ret) + return ret; + + ethqos->pm.serdes_phy =3D devm_phy_optional_get(dev, "serdes"); + if (IS_ERR(ethqos->pm.serdes_phy)) + return dev_err_probe(dev, PTR_ERR(ethqos->pm.serdes_phy), + "Failed to get serdes phy\n"); + + ethqos_update_link_clk(ethqos, SPEED_1000); + + plat_dat->clks_config =3D ethqos_clks_config; + plat_dat->ptp_clk_freq_config =3D ethqos_ptp_clk_freq_config; + + if (ethqos->pm.serdes_phy) { + plat_dat->serdes_powerup =3D qcom_ethqos_serdes_powerup; + plat_dat->serdes_powerdown =3D qcom_ethqos_serdes_powerdown; + } + } =20 - ethqos->set_serdes_speed =3D ethqos_set_serdes_speed_phy; - ethqos->serdes_speed =3D SPEED_1000; - ethqos_update_link_clk(ethqos, SPEED_1000); ethqos_set_func_clk_en(ethqos); =20 plat_dat->bsp_priv =3D ethqos; @@ -869,11 +1053,6 @@ static int qcom_ethqos_probe(struct platform_device *= pdev) if (drv_data->dma_addr_width) plat_dat->host_dma_width =3D drv_data->dma_addr_width; =20 - if (ethqos->pm.serdes_phy) { - plat_dat->serdes_powerup =3D qcom_ethqos_serdes_powerup; - plat_dat->serdes_powerdown =3D qcom_ethqos_serdes_powerdown; - } - /* Enable TSO on queue0 and enable TBS on rest of the queues */ for (i =3D 1; i < plat_dat->tx_queues_to_use; i++) plat_dat->tx_queues_cfg[i].tbs_en =3D 1; @@ -883,6 +1062,7 @@ static int qcom_ethqos_probe(struct platform_device *p= dev) =20 static const struct of_device_id qcom_ethqos_match[] =3D { { .compatible =3D "qcom,qcs404-ethqos", .data =3D &emac_qcs404_data}, + { .compatible =3D "qcom,sa8255p-ethqos", .data =3D &emac_sa8255p_data}, { .compatible =3D "qcom,sa8775p-ethqos", .data =3D &emac_sa8775p_data}, { .compatible =3D "qcom,sc8280xp-ethqos", .data =3D &emac_sc8280xp_data}, { .compatible =3D "qcom,sm8150-ethqos", .data =3D &emac_sm8150_data}, --=20 2.47.3