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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-661a3c66d3fsm517251a12.2.2026.03.06.06.22.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 06:22:23 -0800 (PST) From: Luca Weiss Date: Fri, 06 Mar 2026 15:22:18 +0100 Subject: [PATCH 4/4] arm64: dts: qcom: milos: Add LPASS LPI pinctrl node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260306-milos-pinctrl-lpi-v1-4-086946dbb855@fairphone.com> References: <20260306-milos-pinctrl-lpi-v1-0-086946dbb855@fairphone.com> In-Reply-To: <20260306-milos-pinctrl-lpi-v1-0-086946dbb855@fairphone.com> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772806937; l=3258; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=ceaAYHgyAOISMMGiY+fNNjyu+n4n2FiUVw5y5npeShc=; b=GKmNcNAkRbQfG9aIk8UKVimfr43zZminilltWJfAq60uRDyaLQCYTurQFUFAZ/rd1Zn5kpKRx ZKw1JGCcpTQCprIzBCXF+ID3isfIfFpuM+JN4GEenepgDNXXo3kK3Gx X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add a node for the LPASS LPI pinctrl found on the Milos SoC and define a few pinctrl states that will be used in the future. Signed-off-by: Luca Weiss Acked-by: Linus Walleij Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/milos.dtsi | 103 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 103 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom= /milos.dtsi index 5691eb2dcfd0..ccacf8d14ae8 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -20,6 +20,7 @@ #include #include #include +#include =20 / { interrupt-parent =3D <&intc>; @@ -1307,6 +1308,108 @@ q6prmcc: clock-controller { }; }; =20 + lpass_tlmm: pinctrl@3440000 { + compatible =3D "qcom,milos-lpass-lpi-pinctrl"; + reg =3D <0x0 0x03440000 0x0 0x20000>, + <0x0 0x034d0000 0x0 0x10000>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpass_tlmm 0 0 23>; + + clocks =3D <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "core", + "audio"; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins =3D "gpio0"; + function =3D "swr_tx_clk"; + drive-strength =3D <4>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio1", "gpio2", "gpio14"; + function =3D "swr_tx_data"; + drive-strength =3D <4>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins =3D "gpio3"; + function =3D "swr_rx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio4", "gpio5"; + function =3D "swr_rx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + lpi_i2s2_active: lpi-i2s2-active-state { + clk-pins { + pins =3D "gpio10"; + function =3D "i2s2_clk"; + drive-strength =3D <8>; + bias-disable; + output-high; + }; + + ws-pins { + pins =3D "gpio11"; + function =3D "i2s2_ws"; + drive-strength =3D <8>; + bias-disable; + output-high; + }; + + data-pins { + pins =3D "gpio12", "gpio13"; + function =3D "i2s2_data"; + drive-strength =3D <8>; + bias-disable; + output-high; + }; + }; + + lpi_i2s2_sleep: lpi-i2s2-sleep-state { + clk-pins { + pins =3D "gpio10"; + function =3D "i2s2_clk"; + drive-strength =3D <2>; + bias-pull-down; + input-enable; + }; + + ws-pins { + pins =3D "gpio11"; + function =3D "i2s2_ws"; + drive-strength =3D <2>; + bias-pull-down; + input-enable; + }; + + data-pins { + pins =3D "gpio12", "gpio13"; + function =3D "i2s2_data"; + drive-strength =3D <2>; + bias-pull-down; + input-enable; + }; + }; + }; + lpass_ag_noc: interconnect@3c40000 { compatible =3D "qcom,milos-lpass-ag-noc"; reg =3D <0x0 0x03c40000 0x0 0x17200>; --=20 2.53.0