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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-661a3c66d3fsm517251a12.2.2026.03.06.06.22.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 06:22:19 -0800 (PST) From: Luca Weiss Date: Fri, 06 Mar 2026 15:22:15 +0100 Subject: [PATCH 1/4] dt-bindings: pinctrl: qcom: Add Milos LPI pinctrl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260306-milos-pinctrl-lpi-v1-1-086946dbb855@fairphone.com> References: <20260306-milos-pinctrl-lpi-v1-0-086946dbb855@fairphone.com> In-Reply-To: <20260306-milos-pinctrl-lpi-v1-0-086946dbb855@fairphone.com> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772806937; l=3950; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=ZG4vqB20u3oeYRitCqSlm46mL+bG1BN+RLcEZiDnQkU=; b=OAJkK1lyilgTaVbUADvWkxNsB0geeBBFLPZb9wjke7dZCGjzcAgc5fzWmWQBfKECKiMnjaKMS bSFHpto6X04DKRly3wX4Z4F/zi+JWIE7pZ2R+/kbML4z4GzqH9M38jG X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add bindings for pin controller in Milos Low Power Audio SubSystem (LPASS). Signed-off-by: Luca Weiss Reviewed-by: Krzysztof Kozlowski --- .../pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml | 109 +++++++++++++++++= ++++ 1 file changed, 109 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi= -pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-= lpi-pinctrl.yaml new file mode 100644 index 000000000000..73e84f188591 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctr= l.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,milos-lpass-lpi-pinctrl.ya= ml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Milos SoC LPASS LPI TLMM + +maintainers: + - Luca Weiss + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSyst= em + (LPASS) Low Power Island (LPI) of Qualcomm Milos SoC. + +properties: + compatible: + const: qcom,milos-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + - description: LPASS LPI MCC registers + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-milos-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-milos-lpass-state" + additionalProperties: false + +$defs: + qcom-milos-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-9]|2[0-2])$" + + function: + enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk, + dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_= b, + ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk, + i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk, + i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, qca_swr_= clk, + qca_swr_data, slimbus_clk, slimbus_data, swr_rx_clk, + swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk, + wsa_swr_data ] + description: + Specify the alternative function to be configured for the specif= ied + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + + pinctrl@3440000 { + compatible =3D "qcom,milos-lpass-lpi-pinctrl"; + reg =3D <0x03440000 0x20000>, + <0x034d0000 0x10000>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpass_tlmm 0 0 23>; + + clocks =3D <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPL= E_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE= _NO>; + clock-names =3D "core", + "audio"; + + tx-swr-active-clk-state { + pins =3D "gpio0"; + function =3D "swr_tx_clk"; + drive-strength =3D <4>; + slew-rate =3D <1>; + bias-disable; + }; + }; --=20 2.53.0 From nobody Thu Apr 9 17:21:10 2026 Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12F8D3AE197 for ; Fri, 6 Mar 2026 14:22:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772806950; cv=none; b=GkNYOGPa073BqH0H+ptGgGHLtsc0BBNoPecZSs0Z63qcTxjSWj7epsTfVnXh0K/IRndBKt1B/ZRcwfuOv9Mi3wXRyuMXYvW5RJQdSPRY+9HyB+RrmQhsVqpSMJyifRlk0hOTwUVU7vxUMWDub6jqVkd+cwW4xL9yySJpk5xLreM= ARC-Message-Signature: i=1; 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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-661a3c66d3fsm517251a12.2.2026.03.06.06.22.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 06:22:21 -0800 (PST) From: Luca Weiss Date: Fri, 06 Mar 2026 15:22:16 +0100 Subject: [PATCH 2/4] pinctrl: qcom: Add Milos LPASS LPI TLMM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260306-milos-pinctrl-lpi-v1-2-086946dbb855@fairphone.com> References: <20260306-milos-pinctrl-lpi-v1-0-086946dbb855@fairphone.com> In-Reply-To: <20260306-milos-pinctrl-lpi-v1-0-086946dbb855@fairphone.com> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772806937; l=10462; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=h5gWHA0irmgEDKdcC2MAqtMGfH7nJlQdsrUo0byY85o=; b=1OAEp7Rt/+L3HcoUCG87WyO+/aDLSp+A9OR7Ph7tDnDh5TK9ybU61b3/NRCx1UV2nW2Xgn/Pj TCrFb1ypWvZBSViZtxNIYTSAK1PwvEv/NjNg4zcvD+JjwYNVL1zs7GS X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add a driver for the pin controller in the Low Power Audio SubSystem (LPASS) on the Milos SoC. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio --- Not quite sure what to do with gpio15-gpio18, while downstream just treats them as the others, based on the datasheets there's no GPIO_* where they could be routed to. Shall we just remove them from the driver and treat them as missing? Do holes in pinctrl drivers not cause any extra issues? --- drivers/pinctrl/qcom/Kconfig | 10 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c | 217 +++++++++++++++++++++= ++++ 3 files changed, 228 insertions(+) diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index f56592411cf6..ee34ffca3917 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -60,6 +60,16 @@ config PINCTRL_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SoCs. =20 +config PINCTRL_MILOS_LPASS_LPI + tristate "Qualcomm Technologies Inc Milos LPASS LPI pin controller driver" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc Milos + platform. + config PINCTRL_SC7280_LPASS_LPI tristate "Qualcomm Technologies Inc SC7280 and SM8350 LPASS LPI pin contr= oller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 831103b3827b..a8fd12f90d6e 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_PINCTRL_QDF2XXX) +=3D pinctrl-qdf2xxx.o obj-$(CONFIG_PINCTRL_MDM9607) +=3D pinctrl-mdm9607.o obj-$(CONFIG_PINCTRL_MDM9615) +=3D pinctrl-mdm9615.o obj-$(CONFIG_PINCTRL_MILOS) +=3D pinctrl-milos.o +obj-$(CONFIG_PINCTRL_MILOS_LPASS_LPI) +=3D pinctrl-milos-lpass-lpi.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) +=3D pinctrl-spmi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) +=3D pinctrl-spmi-mpp.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) +=3D pinctrl-ssbi-gpio.o diff --git a/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c b/drivers/pinct= rl/qcom/pinctrl-milos-lpass-lpi.c new file mode 100644 index 000000000000..3bf6fe0cf1bb --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022-2023 Linaro Ltd. + * Copyright (c) 2026 Luca Weiss + */ + +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_dmic3_clk, + LPI_MUX_dmic3_data, + LPI_MUX_dmic4_clk, + LPI_MUX_dmic4_data, + LPI_MUX_i2s0_clk, + LPI_MUX_i2s0_data, + LPI_MUX_i2s0_ws, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_i2s3_clk, + LPI_MUX_i2s3_data, + LPI_MUX_i2s3_ws, + LPI_MUX_qca_swr_clk, + LPI_MUX_qca_swr_data, + LPI_MUX_slimbus_clk, + LPI_MUX_slimbus_data, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_data, + LPI_MUX_wsa_swr_clk, + LPI_MUX_wsa_swr_data, + LPI_MUX_ext_mclk1_a, + LPI_MUX_ext_mclk1_b, + LPI_MUX_ext_mclk1_c, + LPI_MUX_ext_mclk1_d, + LPI_MUX_ext_mclk1_e, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static const struct pinctrl_pin_desc milos_lpi_pins[] =3D { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), +}; + +static const char * const gpio_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", +}; + +static const char * const dmic1_clk_groups[] =3D { "gpio6" }; +static const char * const dmic1_data_groups[] =3D { "gpio7" }; +static const char * const dmic2_clk_groups[] =3D { "gpio8" }; +static const char * const dmic2_data_groups[] =3D { "gpio9" }; +static const char * const dmic3_clk_groups[] =3D { "gpio12" }; +static const char * const dmic3_data_groups[] =3D { "gpio13" }; +static const char * const dmic4_clk_groups[] =3D { "gpio21" }; +static const char * const dmic4_data_groups[] =3D { "gpio22" }; +static const char * const i2s0_clk_groups[] =3D { "gpio0" }; +static const char * const i2s0_ws_groups[] =3D { "gpio1" }; +static const char * const i2s0_data_groups[] =3D { "gpio2", "gpio3", "gpio= 4", "gpio5" }; +static const char * const i2s1_clk_groups[] =3D { "gpio6" }; +static const char * const i2s1_ws_groups[] =3D { "gpio7" }; +static const char * const i2s1_data_groups[] =3D { "gpio8", "gpio9" }; +static const char * const i2s2_clk_groups[] =3D { "gpio10" }; +static const char * const i2s2_ws_groups[] =3D { "gpio11" }; +static const char * const i2s2_data_groups[] =3D { "gpio12", "gpio13" }; +static const char * const i2s3_clk_groups[] =3D { "gpio19" }; +static const char * const i2s3_ws_groups[] =3D { "gpio20" }; +static const char * const i2s3_data_groups[] =3D { "gpio21", "gpio22" }; +static const char * const qca_swr_clk_groups[] =3D { "gpio19" }; +static const char * const qca_swr_data_groups[] =3D { "gpio20" }; +static const char * const slimbus_clk_groups[] =3D { "gpio19" }; +static const char * const slimbus_data_groups[] =3D { "gpio20" }; +static const char * const swr_rx_clk_groups[] =3D { "gpio3" }; +static const char * const swr_rx_data_groups[] =3D { "gpio4", "gpio5" }; +static const char * const swr_tx_clk_groups[] =3D { "gpio0" }; +static const char * const swr_tx_data_groups[] =3D { "gpio1", "gpio2", "gp= io14" }; +static const char * const wsa_swr_clk_groups[] =3D { "gpio10" }; +static const char * const wsa_swr_data_groups[] =3D { "gpio11" }; +static const char * const ext_mclk1_a_groups[] =3D { "gpio13" }; +static const char * const ext_mclk1_b_groups[] =3D { "gpio9" }; +static const char * const ext_mclk1_c_groups[] =3D { "gpio5" }; +static const char * const ext_mclk1_d_groups[] =3D { "gpio14" }; +static const char * const ext_mclk1_e_groups[] =3D { "gpio22" }; + +static const struct lpi_pingroup milos_groups[] =3D { + LPI_PINGROUP(0, 0, swr_tx_clk, i2s0_clk, _, _), + LPI_PINGROUP(1, 2, swr_tx_data, i2s0_ws, _, _), + LPI_PINGROUP(2, 4, swr_tx_data, i2s0_data, _, _), + LPI_PINGROUP(3, 8, swr_rx_clk, i2s0_data, _, _), + LPI_PINGROUP(4, 10, swr_rx_data, i2s0_data, _, _), + LPI_PINGROUP(5, 12, swr_rx_data, ext_mclk1_c, i2s0_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, i2s1_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, i2s1_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, i2s1_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, i2s1_data, ext_mclk1_b, _), + LPI_PINGROUP(10, 16, wsa_swr_clk, i2s2_clk, _, _), + LPI_PINGROUP(11, 18, wsa_swr_data, i2s2_ws, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s2_data, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, dmic3_data, i2s2_data, ext_mclk1_a, _), + LPI_PINGROUP(14, 6, swr_tx_data, ext_mclk1_d, _, _), + /* gpio15 - gpio18 do not really exist */ + LPI_PINGROUP(15, 20, _, _, _, _), + LPI_PINGROUP(16, 22, _, _, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(18, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(19, LPI_NO_SLEW, i2s3_clk, slimbus_clk, qca_swr_clk, _), + LPI_PINGROUP(20, LPI_NO_SLEW, i2s3_ws, slimbus_data, qca_swr_data, _), + LPI_PINGROUP(21, LPI_NO_SLEW, i2s3_data, dmic4_clk, _, _), + LPI_PINGROUP(22, LPI_NO_SLEW, i2s3_data, dmic4_data, ext_mclk1_e, _), +}; + +static const struct lpi_function milos_functions[] =3D { + LPI_FUNCTION(gpio), + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(dmic3_clk), + LPI_FUNCTION(dmic3_data), + LPI_FUNCTION(dmic4_clk), + LPI_FUNCTION(dmic4_data), + LPI_FUNCTION(i2s0_clk), + LPI_FUNCTION(i2s0_data), + LPI_FUNCTION(i2s0_ws), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(i2s3_clk), + LPI_FUNCTION(i2s3_data), + LPI_FUNCTION(i2s3_ws), + LPI_FUNCTION(qca_swr_clk), + LPI_FUNCTION(qca_swr_data), + LPI_FUNCTION(slimbus_clk), + LPI_FUNCTION(slimbus_data), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(wsa_swr_clk), + LPI_FUNCTION(wsa_swr_data), + LPI_FUNCTION(ext_mclk1_a), + LPI_FUNCTION(ext_mclk1_b), + LPI_FUNCTION(ext_mclk1_c), + LPI_FUNCTION(ext_mclk1_d), + LPI_FUNCTION(ext_mclk1_e), +}; + +static const struct lpi_pinctrl_variant_data milos_lpi_data =3D { + .pins =3D milos_lpi_pins, + .npins =3D ARRAY_SIZE(milos_lpi_pins), + .groups =3D milos_groups, + .ngroups =3D ARRAY_SIZE(milos_groups), + .functions =3D milos_functions, + .nfunctions =3D ARRAY_SIZE(milos_functions), +}; + +static const struct of_device_id lpi_pinctrl_of_match[] =3D { + { + .compatible =3D "qcom,milos-lpass-lpi-pinctrl", + .data =3D &milos_lpi_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static struct platform_driver lpi_pinctrl_driver =3D { + .driver =3D { + .name =3D "qcom-milos-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + }, + .probe =3D lpi_pinctrl_probe, + .remove =3D lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("Qualcomm Milos LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); --=20 2.53.0 From nobody Thu Apr 9 17:21:10 2026 Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8A7D3A784F for ; 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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-661a3c66d3fsm517251a12.2.2026.03.06.06.22.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 06:22:22 -0800 (PST) From: Luca Weiss Date: Fri, 06 Mar 2026 15:22:17 +0100 Subject: [PATCH 3/4] arm64: defconfig: Enable Milos LPASS LPI pinctrl driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260306-milos-pinctrl-lpi-v1-3-086946dbb855@fairphone.com> References: <20260306-milos-pinctrl-lpi-v1-0-086946dbb855@fairphone.com> In-Reply-To: <20260306-milos-pinctrl-lpi-v1-0-086946dbb855@fairphone.com> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772806937; l=715; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=OussAjG8fbFFqG3utkJvBKqk21rJMwTmbRmYRXniP1k=; b=OFivjjV4WyuTlJLQsk+h3UHX/H/piTEXQ86vP+pJ95fnEmqvIn1T4M7vpJDGZwBZDa3wHTkoY SJIFOZx3T5nDalppNNIRJmjHe6WL4qFhs6xu/xFRPrCb7jXsMlu9YsH X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Build the LPASS LPI pinctrl driver as module, as required by devices using the Qualcomm Milos SoC. Signed-off-by: Luca Weiss --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 4ed70ab7ee85..c8e294fa4b53 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -693,6 +693,7 @@ CONFIG_PINCTRL_SM8750=3Dy CONFIG_PINCTRL_X1E80100=3Dy CONFIG_PINCTRL_QCOM_SPMI_PMIC=3Dy CONFIG_PINCTRL_LPASS_LPI=3Dm +CONFIG_PINCTRL_MILOS_LPASS_LPI=3Dm CONFIG_PINCTRL_SC7280_LPASS_LPI=3Dm CONFIG_PINCTRL_SM6115_LPASS_LPI=3Dm CONFIG_PINCTRL_SM8250_LPASS_LPI=3Dm --=20 2.53.0 From nobody Thu Apr 9 17:21:10 2026 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5124C3AE702 for ; Fri, 6 Mar 2026 14:22:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772806951; cv=none; b=SG7AimhPmZo2iQKTqS5FLLiCZrPLr6vKIZGx5CJWlDvPQaPgXtxfuz89M1nKxY/wB3KCC8iK3jtNe4QCq+/1sHGbrLt+OME1g8Mqzna2oTexFXCZ3zRvocy5aXGbOBh0S3yg3gZjy+kNPebXW9tmceUOMjBKHhJO3l94rxfzuIA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772806951; c=relaxed/simple; bh=ceaAYHgyAOISMMGiY+fNNjyu+n4n2FiUVw5y5npeShc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jGLMnxX+Lf10cWYWFM6xhHf40biRnGdJ9SrIPwkqeqD/wajT/hu/0VBBCmLX+ZmkLlSB983lKMl/TwHPwLrrymiBjcCNEGaGODdkEyatOltbWbepIDL6rx2bNEz8VMIIus/slLAzKjIdN0/CIq+9gefaS3nDgy17r5auo/nBxiw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=WHNDsM3+; arc=none smtp.client-ip=209.85.208.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="WHNDsM3+" Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-660d77cacc2so944971a12.1 for ; Fri, 06 Mar 2026 06:22:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1772806944; x=1773411744; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+uGmjUwMwFnjrFzi7s2tWi4x0D5mNfrprS2P1mjJOIk=; b=WHNDsM3+QmKHSbTDx0Gyh7iSjnMW1ZDCaCQnV+FWwU3rqvxsWJxDpdBt2ryqaGMaKl RUuNY1Ee3L1snaoAA6Sy9LEXS68zDQMVa69JPkTNg4CUxSMIwNMgLAiShmUbg1sXKVxJ 06iyUqGvtPvYLL5u8WZ2knvvfEYcnFXAB4+Toj91mvuAMSiITRZNKj//koILnYvhT8LV Yp7xNZ+4cS3LJ+E21kjDZtHjUQ318Z5xPgPithD4hW0MNHF4jXs8V7+WJCSc8uiLQttl vs0TpqaC8O3gNv6E/RoJN/gQZKpXGf0O64Nl0Ud24LNjy8rc0irW/nglYgXVl8FHZrh5 uDdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772806944; x=1773411744; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=+uGmjUwMwFnjrFzi7s2tWi4x0D5mNfrprS2P1mjJOIk=; b=hoJVki7rxcm4k3C5yFxdksMdoqN+N0ff3nND2P7onW+VNhmhU5uUVCnfojTq6X7cfd 9qishiWBSEDGE23RPxrOAuW9JBs3pMDFdCOorpQO2E8LOmFmcS2V8hFD1d9wr1f/V0pI RyVSlQ75rq0KUH23eWTXHJZPfrsoilw7NNlEdT8wIBlSItVSTPXT88kDVQHe6v4MtRai hVjPnLH2dKkPTGwujud/+KXFD3isw87Mf3XuBr6OaZWMHO4fWFxIRD2CDpn8yTBlPmqm /CvDDJAgAYVtM+21JCQO9XO2883txpsAk0LEX4Mvd9jVtD/Hqp5E04itL19qU5CGmQrC AkkQ== X-Forwarded-Encrypted: i=1; AJvYcCXNowX9L6VQh9/2uXo5/a+81eArg6NTXlOuTIigK8ZUWqkA2rjqxVnGmozGE8vItVk+aHNp7dz0/DCpHpg=@vger.kernel.org X-Gm-Message-State: AOJu0YwF3FmHKjlBJtmQE+cD2M+we2FqOtpe3c7DhJbV7CYbdcAKVQi8 0Z1VZRm1pooBAP/QNmO5ArG8yU4q6qYPD7P6gY7OSOC/ay4OVOfkSyZ0Ki+pRjYKB9Y= X-Gm-Gg: ATEYQzxeOeqb2WJdEVM1RR5H2xXV70ue4WZSGc2gqCza6d095DP8SImc/gL6LwR5FPF f1IMQX9Hl6sh7WCE6L6FrnkHZL+Me6dFGwC0aS9zTDTzWZKe8FxuS5R0wDcz37D/vggmVDBg2q+ K4mCfJo6B+SYbQAh7Hh9zQmdR8zjOIhPEfOFDVqP02IVdwXK1DjC29bcWQFrk5a+39RNTc3UweI CVd211T4RzmPatuJYdjBumYSQ4QwDIJjFu0hY6nBfQJeCxEvga1DZAc8OxvZ7WqOFbChSFS0RME jDTqbovn6PlbdAL0IUJAouRMc+1LZSgFtvN8nv0IWBCQxDK4g44cd46/oEv7cKPyxy1k00bEfFJ xmIPTUgYN9zdE1pzCdCNhpHW8fRZUgevU2KnQf87huuxOk9iPJD3HniX/qx8OECBSz8F0Z5TtiW 7YAWSD/cqfDp0/ZJiPom4f0xf359gUs17cULfpQqJnZaH4yTuO17tVUzPNqD8Dsj4OJ3ecmH2O+ BFz X-Received: by 2002:aa7:d350:0:b0:659:9068:9786 with SMTP id 4fb4d7f45d1cf-66143049299mr2529371a12.10.1772806944337; Fri, 06 Mar 2026 06:22:24 -0800 (PST) Received: from [172.16.240.99] (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-661a3c66d3fsm517251a12.2.2026.03.06.06.22.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 06:22:23 -0800 (PST) From: Luca Weiss Date: Fri, 06 Mar 2026 15:22:18 +0100 Subject: [PATCH 4/4] arm64: dts: qcom: milos: Add LPASS LPI pinctrl node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260306-milos-pinctrl-lpi-v1-4-086946dbb855@fairphone.com> References: <20260306-milos-pinctrl-lpi-v1-0-086946dbb855@fairphone.com> In-Reply-To: <20260306-milos-pinctrl-lpi-v1-0-086946dbb855@fairphone.com> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772806937; l=3258; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=ceaAYHgyAOISMMGiY+fNNjyu+n4n2FiUVw5y5npeShc=; b=GKmNcNAkRbQfG9aIk8UKVimfr43zZminilltWJfAq60uRDyaLQCYTurQFUFAZ/rd1Zn5kpKRx ZKw1JGCcpTQCprIzBCXF+ID3isfIfFpuM+JN4GEenepgDNXXo3kK3Gx X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add a node for the LPASS LPI pinctrl found on the Milos SoC and define a few pinctrl states that will be used in the future. Signed-off-by: Luca Weiss Acked-by: Linus Walleij Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/milos.dtsi | 103 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 103 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom= /milos.dtsi index 5691eb2dcfd0..ccacf8d14ae8 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -20,6 +20,7 @@ #include #include #include +#include =20 / { interrupt-parent =3D <&intc>; @@ -1307,6 +1308,108 @@ q6prmcc: clock-controller { }; }; =20 + lpass_tlmm: pinctrl@3440000 { + compatible =3D "qcom,milos-lpass-lpi-pinctrl"; + reg =3D <0x0 0x03440000 0x0 0x20000>, + <0x0 0x034d0000 0x0 0x10000>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpass_tlmm 0 0 23>; + + clocks =3D <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "core", + "audio"; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins =3D "gpio0"; + function =3D "swr_tx_clk"; + drive-strength =3D <4>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio1", "gpio2", "gpio14"; + function =3D "swr_tx_data"; + drive-strength =3D <4>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins =3D "gpio3"; + function =3D "swr_rx_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data-pins { + pins =3D "gpio4", "gpio5"; + function =3D "swr_rx_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + lpi_i2s2_active: lpi-i2s2-active-state { + clk-pins { + pins =3D "gpio10"; + function =3D "i2s2_clk"; + drive-strength =3D <8>; + bias-disable; + output-high; + }; + + ws-pins { + pins =3D "gpio11"; + function =3D "i2s2_ws"; + drive-strength =3D <8>; + bias-disable; + output-high; + }; + + data-pins { + pins =3D "gpio12", "gpio13"; + function =3D "i2s2_data"; + drive-strength =3D <8>; + bias-disable; + output-high; + }; + }; + + lpi_i2s2_sleep: lpi-i2s2-sleep-state { + clk-pins { + pins =3D "gpio10"; + function =3D "i2s2_clk"; + drive-strength =3D <2>; + bias-pull-down; + input-enable; + }; + + ws-pins { + pins =3D "gpio11"; + function =3D "i2s2_ws"; + drive-strength =3D <2>; + bias-pull-down; + input-enable; + }; + + data-pins { + pins =3D "gpio12", "gpio13"; + function =3D "i2s2_data"; + drive-strength =3D <2>; + bias-pull-down; + input-enable; + }; + }; + }; + lpass_ag_noc: interconnect@3c40000 { compatible =3D "qcom,milos-lpass-ag-noc"; reg =3D <0x0 0x03c40000 0x0 0x17200>; --=20 2.53.0