From nobody Sun Apr 5 18:20:21 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7888C41324E; Fri, 6 Mar 2026 17:10:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772817005; cv=none; b=NdMm+ESz2T6fQ3jtDKM+fFyfPRPW+uzZ02I57FTXlRXwXjCDf3ducchh2UTvDOD+LVYeSa0BjYudduwLSGB8F9g7juQp8qkIUED6OK6ehgpG3m007Rv7CCHKUkYRcMlwsWjj7+1dH1nb/Hm0q72hC7gsXQuir38fEGfoY2jYXFc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772817005; c=relaxed/simple; bh=BKO7iJk2IhyUeOcAxAzJmMDV35mroMAKYnKUOQP13Fg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=d49C//mIqtc1NJ6DggQ4Pa7I9Wo1Zz1f2OI2u7ul1NDJ465DYt61PQBly/F5e6C845xv42TRyw9L5dCoxf8FvaEAA9UWWp12SRZFHrG6WHHvv08iJW9R+oTU7q0vjLne+pP0ueCh2bon+WTYtLuLPcLzzuda/NGRC9lmUCe2qTc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MG50ustp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MG50ustp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EB07EC4CEF7; Fri, 6 Mar 2026 17:10:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772817005; bh=BKO7iJk2IhyUeOcAxAzJmMDV35mroMAKYnKUOQP13Fg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=MG50ustpwFvAzXQGd6PIyWdUQ1JjYf+8iyfc39XPB/5PeuukLDErjQPbx9CXUc++f QwmpTbfk3jTfCW9UouegSufW5mbxbfdvM/VO/QpTN29279upIjNrQdBGdTA3K/tmoF FwTSLZllP04HGT0DEU2dVpA21bbbcwrsBV7RwR5IwUNhWG1zHgA/Ce4saQJiGUC/mv bWDoJ8sTrf51Ij/w351vm/2E9kKDr7OMJzL6K6MYbRPenKQTR5mQFCjpc5JkhZhKlW p9JUII/LPB+9t3cA0GmrgPkPuPLabb059Ccdg6BG00WMLCFVavDkDO37iSVHuUilxT tQ/Hv/LH//7wg== From: Mark Brown Date: Fri, 06 Mar 2026 17:01:01 +0000 Subject: [PATCH v10 09/30] KVM: arm64: Define internal features for SME Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260306-kvm-arm64-sme-v10-9-43f7683a0fb7@kernel.org> References: <20260306-kvm-arm64-sme-v10-0-43f7683a0fb7@kernel.org> In-Reply-To: <20260306-kvm-arm64-sme-v10-0-43f7683a0fb7@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.15-dev-6ac23 X-Developer-Signature: v=1; a=openpgp-sha256; l=3307; i=broonie@kernel.org; h=from:subject:message-id; bh=BKO7iJk2IhyUeOcAxAzJmMDV35mroMAKYnKUOQP13Fg=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBpqwovGjatnkSdoMG1R7IqeeLHYVyk4vOq/u0bv 10T1mcq7eaJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaasKLwAKCRAk1otyXVSH 0PrrB/9Hg8AGVXjAruDGgoXORBmhD7QMKXYrUDcD4+9YqTX1wkK6LYvmJgAZfl/sZ0mHV8RsAkw 3ebwtOUYs0sbSxewQPIqq2jCubvEfdnPKeqNRavQFEjKDqit4frkvcEeFCoZYuVCBUcK9Ybk6wb QzHyZ9vwfORoX7sIKQsjk1B9rLnyZakOQC+Z8RmldljooFyMh2r2i4OdRAhBEIK11JR24Chj4ie 9uipE0mCRmBVr6uglVJjXmT3uCxOilPoTNR7Z+sAfFwsBVUXa5uTjp12vQPc/c76BB6P3D7TUuv Kb8wyVDEooOzlOV4F2Tc3NYQB03qfbmtbiLYqIa5Hgn/IxQy X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB In order to simplify interdependencies in the rest of the series define the feature detection for SME and its subfeatures. Due to the need for vector length configuration we define a flag for SME like for SVE. We also have two subfeatures which add architectural state, FA64 and SME2, which are configured via the normal ID register scheme. Also provide helpers which check if the vCPU is in streaming mode or has ZA enabled. Reviewed-by: Fuad Tabba Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_host.h | 35 ++++++++++++++++++++++++++++++++++- arch/arm64/kvm/sys_regs.c | 2 +- 2 files changed, 35 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 656464179ba8..906dbefc5b33 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -353,6 +353,8 @@ struct kvm_arch { #define KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS 10 /* Unhandled SEAs are taken to userspace */ #define KVM_ARCH_FLAG_EXIT_SEA 11 + /* SME exposed to guest */ +#define KVM_ARCH_FLAG_GUEST_HAS_SME 12 unsigned long flags; =20 /* VM-wide vCPU feature set */ @@ -1086,7 +1088,16 @@ struct kvm_vcpu_arch { #define vcpu_has_sve(vcpu) kvm_has_sve((vcpu)->kvm) #endif =20 -#define vcpu_has_vec(vcpu) vcpu_has_sve(vcpu) +#define kvm_has_sme(kvm) (system_supports_sme() && \ + test_bit(KVM_ARCH_FLAG_GUEST_HAS_SME, &(kvm)->arch.flags)) + +#ifdef __KVM_NVHE_HYPERVISOR__ +#define vcpu_has_sme(vcpu) kvm_has_sme(kern_hyp_va((vcpu)->kvm)) +#else +#define vcpu_has_sme(vcpu) kvm_has_sme((vcpu)->kvm) +#endif + +#define vcpu_has_vec(vcpu) (vcpu_has_sve(vcpu) || vcpu_has_sme(vcpu)) =20 #ifdef CONFIG_ARM64_PTR_AUTH #define vcpu_has_ptrauth(vcpu) \ @@ -1627,6 +1638,28 @@ void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64= val); #define kvm_has_sctlr2(k) \ (kvm_has_feat((k), ID_AA64MMFR3_EL1, SCTLRX, IMP)) =20 +#define kvm_has_fa64(k) \ + (system_supports_fa64() && \ + kvm_has_feat((k), ID_AA64SMFR0_EL1, FA64, IMP)) + +#define kvm_has_sme2(k) \ + (system_supports_sme2() && \ + kvm_has_feat((k), ID_AA64PFR1_EL1, SME, SME2)) + +#ifdef __KVM_NVHE_HYPERVISOR__ +#define vcpu_has_sme2(vcpu) kvm_has_sme2(kern_hyp_va((vcpu)->kvm)) +#define vcpu_has_fa64(vcpu) kvm_has_fa64(kern_hyp_va((vcpu)->kvm)) +#else +#define vcpu_has_sme2(vcpu) kvm_has_sme2((vcpu)->kvm) +#define vcpu_has_fa64(vcpu) kvm_has_fa64((vcpu)->kvm) +#endif + +#define vcpu_in_streaming_mode(vcpu) \ + (__vcpu_sys_reg(vcpu, SVCR) & SVCR_SM_MASK) + +#define vcpu_za_enabled(vcpu) \ + (__vcpu_sys_reg(vcpu, SVCR) & SVCR_ZA_MASK) + static inline bool kvm_arch_has_irq_bypass(void) { return true; diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 1b4cacb6e918..f94fe57adcad 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1948,7 +1948,7 @@ static unsigned int sve_visibility(const struct kvm_v= cpu *vcpu, static unsigned int sme_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) { - if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, SME, IMP)) + if (vcpu_has_sme(vcpu)) return 0; =20 return REG_HIDDEN; --=20 2.47.3