From nobody Sun Apr 5 18:20:20 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D525401491; Fri, 6 Mar 2026 17:09:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772816996; cv=none; b=AFcCMF0OiLYU81ia5IepJiMxxbxBgnVaRzTjUtpRNITWLUZbqK8r3DlHHQQTMTe1ae0Sulotb56bHXma46ccxN4OrWBfYnr+dkbKepeU46QDmi/ClIb2BQRXMZbVP6A1ulLZ+NbKmi8ujmBbV4wjSjulUn7Ha65nUYdItx6M6NU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772816996; c=relaxed/simple; bh=WVinD+PZg5gNJJmXAaqYdYZjNnA9vJnAHHaWmmyoiA0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ufvVnjQqchVMyyNy0RPoQZjB33sDqhe4Oc3rCRYKUHijlzYnnU6dMv6WtKChsg2Nx+6MvgXrP9IwRnxg+/nhTMlu/5J6SnRGO5zOx06Amfdsjf3z2W+ENJdYpbXtLT898MhOuvRyTkMBKBeOuHfMufzTADTFUwj1bUjmUrkR4bs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=l+SNf2LJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="l+SNf2LJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 245DCC2BC86; Fri, 6 Mar 2026 17:09:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772816996; bh=WVinD+PZg5gNJJmXAaqYdYZjNnA9vJnAHHaWmmyoiA0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=l+SNf2LJKvzXJvTAXxdWC2sMdkaz+ozbrbV8vW5MZT3te7IMAzl5YxKu/5MeWgrZh P+aMITHI6G37NIkM4Pwgf5eH2MWibKf25naqVNY0m7fI4VQ78C87GBWdrwM7UY5buR ItLKDJ6skZIhcI8lJ2Y+hvPOPAKoPmy0IhHarctHEQp+7XfVS7IpryXVq2GUnRw4nq EFvaL8YczoFxOYmi/bn204pfh5Lx/4/r4t/ZsAxgQS64dRaAb5KXcpIx9Vy8zMsH21 ffrAfYm7yfqdlAOegtqJB7pYFJaRKc3zLAq+yUNjNEsz/H9BAN6vjd2fsTE432v96w PyAfbrTDiE4fw== From: Mark Brown Date: Fri, 06 Mar 2026 17:00:59 +0000 Subject: [PATCH v10 07/30] KVM: arm64: Move SVE state access macros after feature test macros Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260306-kvm-arm64-sme-v10-7-43f7683a0fb7@kernel.org> References: <20260306-kvm-arm64-sme-v10-0-43f7683a0fb7@kernel.org> In-Reply-To: <20260306-kvm-arm64-sme-v10-0-43f7683a0fb7@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.15-dev-6ac23 X-Developer-Signature: v=1; a=openpgp-sha256; l=2766; i=broonie@kernel.org; h=from:subject:message-id; bh=WVinD+PZg5gNJJmXAaqYdYZjNnA9vJnAHHaWmmyoiA0=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBpqwouL/LMzLhb7e8WoxtZwIEbzOl4rfVnCNAcj 9NpObJy/I6JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaasKLgAKCRAk1otyXVSH 0J7KB/9cDJ3yEZzWS61XCor71OYqImPMtHbcwcGrAwSt9+PIEB0J4xMggs8anSvNbOjxmJ6vcm6 uDYL08igkJwXWVPCWsdyxDSaVPLAN5E1NogM95HuOCD4ZXncP817BevI6naP6Vmu6/hqM7z4PUe cNlqLYM2JTpPgRch0cQbp/pZNmutdQDMEMoLqSbZfdM2qGRLdrMZ4MI3MloXaaUB0vGTUzgFjAp kcz/QCklxqYhptf4b0um1WVDdCdRL91EypKUhor+zsxqtdccd9JOydp2mxN50M/aOCe03cYM6Ws gdm17lBZmTgbHJKpLgKxHdK+yasjHF/3XVmSYLZ2HSvL6+Ys X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB In preparation for SME support move the macros used to access SVE state after the feature test macros, we will need to test for SME subfeatures to determine the size of the SME state. Reviewed-by: Fuad Tabba Signed-off-by: Mark Brown Reviewed-by: Jean-Philippe Brucker --- arch/arm64/include/asm/kvm_host.h | 50 +++++++++++++++++++----------------= ---- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 2ca264b3db5f..3e7247b3890c 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -1072,31 +1072,6 @@ struct kvm_vcpu_arch { #define NESTED_SERROR_PENDING __vcpu_single_flag(sflags, BIT(8)) =20 =20 -/* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ -#define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \ - sve_ffr_offset((vcpu)->arch.sve_max_vl)) - -#define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl) - -#define vcpu_sve_zcr_elx(vcpu) \ - (unlikely(is_hyp_ctxt(vcpu)) ? ZCR_EL2 : ZCR_EL1) - -#define sve_state_size_from_vl(sve_max_vl) ({ \ - size_t __size_ret; \ - unsigned int __vq; \ - \ - if (WARN_ON(!sve_vl_valid(sve_max_vl))) { \ - __size_ret =3D 0; \ - } else { \ - __vq =3D sve_vq_from_vl(sve_max_vl); \ - __size_ret =3D SVE_SIG_REGS_SIZE(__vq); \ - } \ - \ - __size_ret; \ -}) - -#define vcpu_sve_state_size(vcpu) sve_state_size_from_vl((vcpu)->arch.sve_= max_vl) - #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \ KVM_GUESTDBG_USE_SW_BP | \ KVM_GUESTDBG_USE_HW | \ @@ -1132,6 +1107,31 @@ struct kvm_vcpu_arch { =20 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs) =20 +/* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ +#define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) + \ + sve_ffr_offset((vcpu)->arch.sve_max_vl)) + +#define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl) + +#define vcpu_sve_zcr_elx(vcpu) \ + (unlikely(is_hyp_ctxt(vcpu)) ? ZCR_EL2 : ZCR_EL1) + +#define sve_state_size_from_vl(sve_max_vl) ({ \ + size_t __size_ret; \ + unsigned int __vq; \ + \ + if (WARN_ON(!sve_vl_valid(sve_max_vl))) { \ + __size_ret =3D 0; \ + } else { \ + __vq =3D sve_vq_from_vl(sve_max_vl); \ + __size_ret =3D SVE_SIG_REGS_SIZE(__vq); \ + } \ + \ + __size_ret; \ +}) + +#define vcpu_sve_state_size(vcpu) sve_state_size_from_vl((vcpu)->arch.sve_= max_vl) + /* * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the * memory backed version of a register, and not the one most recently --=20 2.47.3