From nobody Sun Apr 5 18:20:20 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 912643ED5A7; Fri, 6 Mar 2026 17:09:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772816978; cv=none; b=F7WUIbMlJpG+LfNJMeu8U4vyxKzXXN+qrXiXsFx4N2RsBdbhRvyKbKsaowSmWehCDL5HPHGTW622zrbLT6FDOCAMMZprctXxn58rw2qwYJruid6/YuWuFKbHD2vvb0gtRBzI6LCaES50VTzzfCZsjGZ95ZILqkFmfelV7DEO5Dc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772816978; c=relaxed/simple; bh=sM9E+HyTSNR7eo/xMvIQXOjg3Prwq/RvlNfqR4HFAKw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mIM/kmV7yblyt94Rfk4jPrAQAnQb4fc5lwNktWpo6FhO/zl4kP6iieicsg1o9HDQlry9QLOAKYVU3wP6U21hVrBy6G43yXABA+U5bbGC1UCGbIKPfUpFmQShPLQ08Kq3zbGKYVzTUtWmjuJWOskDDTynPBVZNd4cTUzzhYNk3Bg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pa8RwM4h; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pa8RwM4h" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 75FCAC19425; Fri, 6 Mar 2026 17:09:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772816978; bh=sM9E+HyTSNR7eo/xMvIQXOjg3Prwq/RvlNfqR4HFAKw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=pa8RwM4heujOlb8MDd1b6sXTwRaFj5C21AjuX5JQgc3XvXVc3KoNh4ciBe5o9W6KQ Y18LpZLHpa32FY7l/zQkOAnTzZbYiNmmCdAREWxN18rY2Z71qZr++0Qt5VvKqO25Xw YhfIZn4fJa3tRToMqwgIOpg88U20o1JhIGEIamM83dOx1xc0RQ5TVCicVB3CNTTfXx t3Q05+VwkA/mt+4aXHVgnuFQmw1FwYZdNP0aEwU/pE7xe7TAZTFof4CmMzhjiWAOrU YOnBiHQFkI3oFsK/HKJ3VPAD39X+SagQqrnvNUf3aGRgJtar6W4prfeqzrYFchbi0T 8A7o2JmZQx4Ag== From: Mark Brown Date: Fri, 06 Mar 2026 17:00:55 +0000 Subject: [PATCH v10 03/30] arm64/fpsimd: Decide to save ZT0 and streaming mode FFR at bind time Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260306-kvm-arm64-sme-v10-3-43f7683a0fb7@kernel.org> References: <20260306-kvm-arm64-sme-v10-0-43f7683a0fb7@kernel.org> In-Reply-To: <20260306-kvm-arm64-sme-v10-0-43f7683a0fb7@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.15-dev-6ac23 X-Developer-Signature: v=1; a=openpgp-sha256; l=3297; i=broonie@kernel.org; h=from:subject:message-id; bh=sM9E+HyTSNR7eo/xMvIQXOjg3Prwq/RvlNfqR4HFAKw=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBpqwoq5zUTgfzO46tRiQ5ZzpXJgba6fXPBrZsxe +CIkm++mEmJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaasKKgAKCRAk1otyXVSH 0CwJB/9C13km6pWUoAvqHsbOVm3SS4n6CBgFM2r7aTMrW+PlTIWM83xo0vOJA4Nt7RlP2JD2NSF srDCWFqiDsg+m1VKmZGMb9uIrAOwFogIxAd3QPCXL7nfFnecDbFCcpYFM94kJnrG/va6nd2/VT7 qBRg2PIdfcYLHCKQMxm+U9gLFnO755Vnz31WxvbJGnSqNRilZ/533E+pKyWoePCeF1vwFPa+Zz9 EmuK34/nfAeu7PrcNdr0ZgGzbiSe3nGSrmvPa+INrTIxWQ1/iyOv8HWM19gHXQ4VhQnxo1RjNJz /st2NpVPHhU0H1Lo9zuGjEODTgtAXWmEIysw8IrW+OBz7HtQ X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Some parts of the SME state are optional, enabled by additional features on top of the base FEAT_SME and controlled with enable bits in SMCR_ELx. We unconditionally enable these for the host but for KVM we will allow the feature set exposed to guests to be restricted by the VMM. These are the FFR register (FEAT_SME_FA64) and ZT0 (FEAT_SME2). We defer saving of guest floating point state for non-protected guests to the host kernel. We also want to avoid having to reconfigure the guest floating point state if nothing used the floating point state while running the host. If the guest was running with the optional features disabled then traps will be enabled for them so the host kernel will need to skip accessing that state when saving state for the guest. Support this by moving the decision about saving this state to the point where we bind floating point state to the CPU, adding a new variable to the cpu_fp_state which uses the enable bits in SMCR_ELx to flag which features are enabled. Reviewed-by: Fuad Tabba Signed-off-by: Mark Brown Reviewed-by: Catalin Marinas --- arch/arm64/include/asm/fpsimd.h | 1 + arch/arm64/kernel/fpsimd.c | 10 ++++++++-- arch/arm64/kvm/fpsimd.c | 1 + 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsim= d.h index 7361b3b4a5f5..e97729aa3b2f 100644 --- a/arch/arm64/include/asm/fpsimd.h +++ b/arch/arm64/include/asm/fpsimd.h @@ -87,6 +87,7 @@ struct cpu_fp_state { void *sme_state; u64 *svcr; u64 *fpmr; + u64 sme_features; unsigned int sve_vl; unsigned int sme_vl; enum fp_type *fp_type; diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index cf419319f077..2af0e0c5b9f4 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -483,12 +483,12 @@ static void fpsimd_save_user_state(void) =20 if (*svcr & SVCR_ZA_MASK) sme_save_state(last->sme_state, - system_supports_sme2()); + last->sme_features & SMCR_ELx_EZT0); =20 /* If we are in streaming mode override regular SVE. */ if (*svcr & SVCR_SM_MASK) { save_sve_regs =3D true; - save_ffr =3D system_supports_fa64(); + save_ffr =3D last->sme_features & SMCR_ELx_FA64; vl =3D last->sme_vl; } } @@ -1632,6 +1632,12 @@ static void fpsimd_bind_task_to_cpu(void) last->to_save =3D FP_STATE_CURRENT; current->thread.fpsimd_cpu =3D smp_processor_id(); =20 + last->sme_features =3D 0; + if (system_supports_fa64()) + last->sme_features |=3D SMCR_ELx_FA64; + if (system_supports_sme2()) + last->sme_features |=3D SMCR_ELx_EZT0; + /* * Toggle SVE and SME trapping for userspace if needed, these * are serialsied by ret_to_user(). diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c index 15e17aca1dec..9158353d8be3 100644 --- a/arch/arm64/kvm/fpsimd.c +++ b/arch/arm64/kvm/fpsimd.c @@ -80,6 +80,7 @@ void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu) fp_state.svcr =3D __ctxt_sys_reg(&vcpu->arch.ctxt, SVCR); fp_state.fpmr =3D __ctxt_sys_reg(&vcpu->arch.ctxt, FPMR); fp_state.fp_type =3D &vcpu->arch.fp_type; + fp_state.sme_features =3D 0; =20 if (vcpu_has_sve(vcpu)) fp_state.to_save =3D FP_STATE_SVE; --=20 2.47.3