From nobody Sun Apr 5 18:20:40 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15EE841B34E; Fri, 6 Mar 2026 17:10:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772817054; cv=none; b=WSASsXoVY4EDFqDkNC6ROpLyzdcJFrwA4N9zvBp1XKFKgoqMolgk0wAJDYjLssoevfD6UXV0VzjfI/ABX+3yYTDLPcy1uVHz+D5/1BhnYZZprDLDXyPInKkHJaWoWPkpoPVQDhH4mXo0hjV6IfDve+3sCG7bCLBcy+qVjHOXsrc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772817054; c=relaxed/simple; bh=adTxBFGRwQgcoDahtmqxTjtuGOAKvsxDnqc+RXBB7TE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Z0vAE0USfSLee6PKPIedeFho2Ze3vHxEUDEtwjbsphsWPjdf3u7IQLeDRSx6WJV9Y8svi6XKTVZH7OgiWb9gnJwbKgFtiEhSg2EtswQqn6uB+S3b16dzxoIjsUrAft9eftkk9FCyBE3jBFpoqgGVYAsLJMeyFbelyb88G59aUJA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=P+t6cMfr; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="P+t6cMfr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B08D8C4CEF7; Fri, 6 Mar 2026 17:10:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772817053; bh=adTxBFGRwQgcoDahtmqxTjtuGOAKvsxDnqc+RXBB7TE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=P+t6cMfruA3noVoGA+fw/wB+mk2enpMDLfvQ8j8XARair3vL0IwqYBhen0Fv3+H9E NlWNDNYjnzwsxnaE3ZwbR+Ce1tQ2Rjh/cok5oE9yH9dbcjM/y7hDWE+5o+7eyd02oi l2tqCb6/f3llO7K8x2mzTO9Mm8w5r5UKX66QFmxd1EnKDpXe968/HnGDNm/4Mk325h p6Z+dx5NdqfzQFzhi3Io1cbkTLLv5cCjFig0O2waxMswjetXxMKtim8p3Esz0bV+6D s4sC3uinbkWgPLpX4SNyVn1G0ml/SQxEqtwQmortAaTN63MZLRMK0laVRjvy7ln6Dd nkDTE3DbaAAQA== From: Mark Brown Date: Fri, 06 Mar 2026 17:01:12 +0000 Subject: [PATCH v10 20/30] KVM: arm64: Support userspace access to streaming mode Z and P registers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260306-kvm-arm64-sme-v10-20-43f7683a0fb7@kernel.org> References: <20260306-kvm-arm64-sme-v10-0-43f7683a0fb7@kernel.org> In-Reply-To: <20260306-kvm-arm64-sme-v10-0-43f7683a0fb7@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.15-dev-6ac23 X-Developer-Signature: v=1; a=openpgp-sha256; l=5535; i=broonie@kernel.org; h=from:subject:message-id; bh=adTxBFGRwQgcoDahtmqxTjtuGOAKvsxDnqc+RXBB7TE=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBpqwo4vuM/qvToJ/erMef+mTT8+E2MOiB02B8xK rUCsyw4o/6JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaasKOAAKCRAk1otyXVSH 0H/EB/9WbvOJbemHDY5M9t8n5SLcw2NQ6dV+b4W/ALqCyPneVNWB7Qj1lVutSczk7wkC2W10E2h hm4u0UURF0Zh5RnHC3/9u9WGgQAm+p5nQH9KjETJOTVvb8yWZStMCFxEPwE7AgWXmLL1yJ/z42I R1bOvV4+1fIAUzCzWJhvh/OLVd7zuUKuDJKme+IdtEwOXtmzxbwrUt+nfUbaqUIOPmErVOKCXuy 7PB7sdZgZ9npHPaQDddBJdKJfz75vU3Wpq1Gvl0rE+kg/gZBqnibf6vj9lJD+2BUWRNCrxEaCwq 5dNy3LhUHtlmaInaBRQmubYJPPDv/Vgpbc5oTydIBWeg7ItY X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB SME introduces a mode called streaming mode where the Z, P and optionally FFR registers can be accessed using the SVE instructions but with the SME vector length. Reflect this in the ABI for accessing the guest registers by making the vector length for the vcpu reflect the vector length that would be seen by the guest were it running, using the SME vector length when the guest is configured for streaming mode. Since SME may be present without SVE we also update the existing checks for access to the Z, P and V registers to check for either SVE or streaming mode. When not in streaming mode the guest floating point state may be accessed via the V registers. Any VMM that supports SME must be aware of the need to configure streaming mode prior to writing the floating point registers that this creates. Signed-off-by: Mark Brown --- arch/arm64/kvm/guest.c | 67 +++++++++++++++++++++++++++++++++++++++++++---= ---- 1 file changed, 58 insertions(+), 9 deletions(-) diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 9276054b5bdd..20e06047d4bf 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -73,6 +73,19 @@ static u64 core_reg_offset_from_id(u64 id) return id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE); } =20 +static bool vcpu_has_sve_regs(const struct kvm_vcpu *vcpu) +{ + return vcpu_has_sve(vcpu) || vcpu_in_streaming_mode(vcpu); +} + +static bool vcpu_has_ffr(const struct kvm_vcpu *vcpu) +{ + if (vcpu_in_streaming_mode(vcpu)) + return vcpu_has_fa64(vcpu); + else + return vcpu_has_sve(vcpu); +} + static int core_reg_size_from_offset(const struct kvm_vcpu *vcpu, u64 off) { int size; @@ -110,9 +123,10 @@ static int core_reg_size_from_offset(const struct kvm_= vcpu *vcpu, u64 off) /* * The KVM_REG_ARM64_SVE regs must be used instead of * KVM_REG_ARM_CORE for accessing the FPSIMD V-registers on - * SVE-enabled vcpus: + * SVE-enabled vcpus or when a SME enabled vcpu is in + * streaming mode: */ - if (vcpu_has_sve(vcpu) && core_reg_offset_is_vreg(off)) + if (vcpu_has_sve_regs(vcpu) && core_reg_offset_is_vreg(off)) return -EINVAL; =20 return size; @@ -423,6 +437,24 @@ struct vec_state_reg_region { unsigned int upad; /* extra trailing padding in user memory */ }; =20 +/* + * We represent the Z and P registers to userspace using either the + * SVE or SME vector length, depending on which features the guest has + * and if the guest is in streaming mode. + */ +static unsigned int vcpu_sve_cur_vq(struct kvm_vcpu *vcpu) +{ + unsigned int vq =3D 0; + + if (vcpu_has_sve(vcpu)) + vq =3D vcpu_sve_max_vq(vcpu); + + if (vcpu_in_streaming_mode(vcpu)) + vq =3D vcpu_sme_max_vq(vcpu); + + return vq; +} + /* * Validate SVE register ID and get sanitised bounds for user/kernel SVE * register copy @@ -460,20 +492,25 @@ static int sve_reg_to_region(struct vec_state_reg_reg= ion *region, reg_num =3D (reg->id & SVE_REG_ID_MASK) >> SVE_REG_ID_SHIFT; =20 if (reg->id >=3D zreg_id_min && reg->id <=3D zreg_id_max) { - if (!vcpu_has_sve(vcpu) || (reg->id & SVE_REG_SLICE_MASK) > 0) + if (!vcpu_has_sve_regs(vcpu) || (reg->id & SVE_REG_SLICE_MASK) > 0) return -ENOENT; =20 - vq =3D vcpu_sve_max_vq(vcpu); + vq =3D vcpu_sve_cur_vq(vcpu); =20 reqoffset =3D SVE_SIG_ZREG_OFFSET(vq, reg_num) - SVE_SIG_REGS_OFFSET; reqlen =3D KVM_SVE_ZREG_SIZE; maxlen =3D SVE_SIG_ZREG_SIZE(vq); } else if (reg->id >=3D preg_id_min && reg->id <=3D preg_id_max) { - if (!vcpu_has_sve(vcpu) || (reg->id & SVE_REG_SLICE_MASK) > 0) + if (!vcpu_has_sve_regs(vcpu) || (reg->id & SVE_REG_SLICE_MASK) > 0) return -ENOENT; =20 - vq =3D vcpu_sve_max_vq(vcpu); + if (!vcpu_has_ffr(vcpu) && + (reg->id >=3D KVM_REG_ARM64_SVE_FFR(0)) && + (reg->id <=3D KVM_REG_ARM64_SVE_FFR(SVE_NUM_SLICES - 1))) + return -ENOENT; + + vq =3D vcpu_sve_cur_vq(vcpu); =20 reqoffset =3D SVE_SIG_PREG_OFFSET(vq, reg_num) - SVE_SIG_REGS_OFFSET; @@ -512,6 +549,9 @@ static int get_sve_reg(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) if (!kvm_arm_vcpu_vec_finalized(vcpu)) return -EPERM; =20 + if (!vcpu_has_sve_regs(vcpu)) + return -EBUSY; + if (copy_to_user(uptr, vcpu->arch.sve_state + region.koffset, region.klen) || clear_user(uptr + region.klen, region.upad)) @@ -538,6 +578,9 @@ static int set_sve_reg(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) if (!kvm_arm_vcpu_vec_finalized(vcpu)) return -EPERM; =20 + if (!vcpu_has_sve_regs(vcpu)) + return -EBUSY; + if (copy_from_user(vcpu->arch.sve_state + region.koffset, uptr, region.klen)) return -EFAULT; @@ -639,15 +682,21 @@ static unsigned long num_core_regs(const struct kvm_v= cpu *vcpu) static unsigned long num_sve_regs(const struct kvm_vcpu *vcpu) { const unsigned int slices =3D vcpu_sve_slices(vcpu); + int regs, ret; =20 - if (!vcpu_has_sve(vcpu)) + if (!vcpu_has_sve(vcpu) && !vcpu_in_streaming_mode(vcpu)) return 0; =20 /* Policed by KVM_GET_REG_LIST: */ WARN_ON(!kvm_arm_vcpu_vec_finalized(vcpu)); =20 - return slices * (SVE_NUM_PREGS + SVE_NUM_ZREGS + 1 /* FFR */) - + 1; /* KVM_REG_ARM64_SVE_VLS */ + regs =3D SVE_NUM_PREGS + SVE_NUM_ZREGS; + if (vcpu_has_sve(vcpu) || vcpu_has_fa64(vcpu)) + regs++; /* FFR */ + ret =3D regs * slices; + if (vcpu_has_sve(vcpu)) + ret++; /* KVM_REG_ARM64_SVE_VLS */ + return ret; } =20 static int copy_sve_reg_indices(const struct kvm_vcpu *vcpu, --=20 2.47.3