From nobody Sun Apr 5 18:20:40 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62D7C41325C; Fri, 6 Mar 2026 17:10:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772817036; cv=none; b=u5zcaWdXuxZU3CMth4dJaJq7FYsn0UyN2pAfH0ozhc/L+T0PG6uamHsSRviBU6XqBhAJGK1fS7t5VBDLwHAZMLwkXx54CNjR5wO67pk5aDMNZvsU7OHoAcmg+JNrvtRXNhuIybnOIP8eiQLHjv+R3rlhuLKOGQy1Tv0aYa3RacM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772817036; c=relaxed/simple; bh=WfGxhqhjq10VSZV2h4qBa1D5MAiiOjvTsGIutBZvgzc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WEagRIMFtsvqCaePIMFWbQF1BAg9NhfXO0HB95FlT5M76vtZRBxvzBKfPZburQKlJJYrD9fspR3cFQiRqn/Bck5ky6xvoP/hb21dQBQv39MJlozMF41Bt4AM2aRkkWTVXaXbmBnU2LsBA2E+Um2UB7g2/TW29PcFu5qlqxdrhRc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YGQF1lpW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YGQF1lpW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id ED45FC19425; Fri, 6 Mar 2026 17:10:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772817035; bh=WfGxhqhjq10VSZV2h4qBa1D5MAiiOjvTsGIutBZvgzc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=YGQF1lpWRSNCgIY7ZSXaI+wlaPYuTpKe7GWuHTZlkTV4EmygG5gPWR4TpekpDfek7 9SKQuzptPALC/VjW1Rb7bnWEEAq+QMxfkERwsp7pDfrNfOoKelAItMonhu4zmZvM6x E2ubrJ74qHgeuOF+XCJKxAe9lmZC59ZrEGGz2J1a4114Z3Coxte7YW4Y1mWeS/amlS YmXBKezMUx43vs01pf3wnQbqzLDcr3+qfNVWKnrSFuI7OS43Wx1iNsq2EYcvGSrHFi EKj2vMB/u2L7g6UNtCmx1YRAwMbzbnIX3mXVK1tRwmqwed1ezShH/SRObdkHYOMj6m ulFxdD2xug7pg== From: Mark Brown Date: Fri, 06 Mar 2026 17:01:08 +0000 Subject: [PATCH v10 16/30] KVM: arm64: Support TPIDR2_EL0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260306-kvm-arm64-sme-v10-16-43f7683a0fb7@kernel.org> References: <20260306-kvm-arm64-sme-v10-0-43f7683a0fb7@kernel.org> In-Reply-To: <20260306-kvm-arm64-sme-v10-0-43f7683a0fb7@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.15-dev-6ac23 X-Developer-Signature: v=1; a=openpgp-sha256; l=3509; i=broonie@kernel.org; h=from:subject:message-id; bh=WfGxhqhjq10VSZV2h4qBa1D5MAiiOjvTsGIutBZvgzc=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBpqwo1v7dD/KcG9s1sYihJjHjqzTXtoGqAjolYy d2DqFiDNKWJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaasKNQAKCRAk1otyXVSH 0OTvB/97FvvhkZuzELh6GOdRs9rjuutO8EvVc+/Z/UoedyQy3bhhUUa81iUPK4TUX6dRAlSWyRj yngohaEvhpTlOOS2oNqJZoYk1AU4/kcjQQ3oKm/f6LU566xg2v7SCzM+qZB0or89nDT4J29AliJ zF3EGfPafDtb6ah3hxN9dAfSbLdLea0nLhxha1mzdSmoYL61Hnwj9tIHDpaJu6a/6jkiJrVu5P5 xYRnFkoewo2fmAgJOM7JunfhXZTBroKTKiCtC2GOL6nZnSg32qd0+OT0p29barLlUOYOwtyVLP6 wx3H0YqJwLDTakRDeK1To9odEizdPUz2lnUKrmcaoMK08ONB X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB SME adds a new thread ID register, TPIDR2_EL0. This is used in userspace for delayed saving of the ZA state but in terms of the architecture is not really connected to SME other than being part of FEAT_SME. It has an independent fine grained trap and the runtime connection with the rest of SME is purely software defined. Expose the register as a system register if the guest supports SME, context switching it along with the other EL0 TPIDRs. Reviewed-by: Fuad Tabba Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 15 +++++++++++++++ arch/arm64/kvm/sys_regs.c | 3 ++- 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index e5194ffc40a7..ec1ede0c3c12 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -445,6 +445,7 @@ enum vcpu_sysreg { CSSELR_EL1, /* Cache Size Selection Register */ TPIDR_EL0, /* Thread ID, User R/W */ TPIDRRO_EL0, /* Thread ID, User R/O */ + TPIDR2_EL0, /* Thread ID, Register 2 */ TPIDR_EL1, /* Thread ID, Privileged */ CNTKCTL_EL1, /* Timer Control Register (EL1) */ PAR_EL1, /* Physical Address Register */ diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hy= p/include/hyp/sysreg-sr.h index 5624fd705ae3..8c3b3d6df99f 100644 --- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h +++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h @@ -88,6 +88,17 @@ static inline bool ctxt_has_sctlr2(struct kvm_cpu_contex= t *ctxt) return kvm_has_sctlr2(kern_hyp_va(vcpu->kvm)); } =20 +static inline bool ctxt_has_sme(struct kvm_cpu_context *ctxt) +{ + struct kvm_vcpu *vcpu; + + if (!system_supports_sme()) + return false; + + vcpu =3D ctxt_to_vcpu(ctxt); + return kvm_has_sme(kern_hyp_va(vcpu->kvm)); +} + static inline bool ctxt_is_guest(struct kvm_cpu_context *ctxt) { return host_data_ptr(host_ctxt) !=3D ctxt; @@ -127,6 +138,8 @@ static inline void __sysreg_save_user_state(struct kvm_= cpu_context *ctxt) { ctxt_sys_reg(ctxt, TPIDR_EL0) =3D read_sysreg(tpidr_el0); ctxt_sys_reg(ctxt, TPIDRRO_EL0) =3D read_sysreg(tpidrro_el0); + if (ctxt_has_sme(ctxt)) + ctxt_sys_reg(ctxt, TPIDR2_EL0) =3D read_sysreg_s(SYS_TPIDR2_EL0); } =20 static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt) @@ -204,6 +217,8 @@ static inline void __sysreg_restore_user_state(struct k= vm_cpu_context *ctxt) { write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL0), tpidr_el0); write_sysreg(ctxt_sys_reg(ctxt, TPIDRRO_EL0), tpidrro_el0); + if (ctxt_has_sme(ctxt)) + write_sysreg_s(ctxt_sys_reg(ctxt, TPIDR2_EL0), SYS_TPIDR2_EL0); } =20 static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt, diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index f13ff8e630f2..66248fd48a7d 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -3511,7 +3511,8 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { .visibility =3D s1poe_visibility }, { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, - { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, + { SYS_DESC(SYS_TPIDR2_EL0), NULL, reset_unknown, TPIDR2_EL0, + .visibility =3D sme_visibility}, =20 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, =20 --=20 2.47.3