From nobody Thu Apr 9 19:19:02 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 197773783B2; Fri, 6 Mar 2026 08:07:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772784464; cv=none; b=bu6jpfeUgY1tXyb8N3RmJZJoxFGmYhHk+mUkov8caxvqS3SuSM+4fPsBSRWmYkaGuYRWezWiXc6lZrptp+wjAbTbX4XUlJAUvCrlWgM3T0qQZroiMHnqCSwHH5xOn3nuaXIPEMIDMddelDH8k6mR2zu+Lgzkzrd1KsHcKIggXxQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772784464; c=relaxed/simple; bh=3E1xw0HsueF+u/KGpP5CYluFLpq97aaG2OP77KelhBs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=mXNHp6Q9glhacclzNzdcWh/o20c87YWaZpjujx2SYQj4u/6HkvO5QR22HMJcNErn9Lrq1zDCx2EtXi32TkaIS6wJDSMkHcs4W6R19c+k5WNqrp1ZGKecNE7ZZmqHUx7ZlJsR6sa1Pdnbvu5X479GiDqlEyJieuXSteojWf+U+nE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 6 Mar 2026 16:07:24 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 6 Mar 2026 16:07:24 +0800 From: Ryan Chen Date: Fri, 6 Mar 2026 16:07:27 +0800 Subject: [PATCH v2 5/5] dt-bindings: interrupt-controller: aspeed: Remove AST2700-A0 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260306-irqchip-v2-5-f8512c09be63@aspeedtech.com> References: <20260306-irqchip-v2-0-f8512c09be63@aspeedtech.com> In-Reply-To: <20260306-irqchip-v2-0-f8512c09be63@aspeedtech.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , "Andrew Jeffery" , Paul Walmsley , "Palmer Dabbelt" , Albert Ou , "Alexandre Ghiti" , Thomas Gleixner , Thomas Gleixner CC: , , , , , Ryan Chen X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772784444; l=4783; i=ryan_chen@aspeedtech.com; s=20251126; h=from:subject:message-id; bh=3E1xw0HsueF+u/KGpP5CYluFLpq97aaG2OP77KelhBs=; b=kn3OWDXDQmtIRzIJ+vraA5kn3sCgavptGJTCroJCF5tKMdeBxGWqFh6O/g3qUTIV5PITffJCm x6t6XR7doW0DCAxoEbGTDatBhB49uxvPlTHJYMShILaxIWY7BloaU+0 X-Developer-Key: i=ryan_chen@aspeedtech.com; a=ed25519; pk=Xe73xY6tcnkuRjjbVAB/oU30KdB3FvG4nuJuILj7ZVc= The existing AST2700 interrupt controller binding ("aspeed,ast2700-intc-ic") was written against the A0 pre-production design. In A0, the interrupt hierarchy effectively converged at the Primary Service Processor (PSP): INTC1 instances fed into INTC0, and INTC0 was wired to the PSP GIC. The binding therefore described a fixed, PSP aggregation model. From A1 onwards (retained in the A2 production silicon), the interrupt fabric was re-architected: interrupt routing is programmable and interrupt outputs can be directed to multiple upstream controllers (PSP GIC, Secondary Service Processor (SSP) NVIC, Tertiary Service Processor (TSP) NVIC, and Boot MCU interrupt controller). This design requires route resolution and a controller hierarchy model which the A0 binding cannot represent. Remove the binding for the pre-production A0 design in favour of the binding for the A2 production design. There is no significant user impact from the removal as there are no existing devicetrees in any of Linux, u-boot or Zephyr that make use of the A0 binding. Signed-off-by: Ryan Chen --- .../interrupt-controller/aspeed,ast2700-intc.yaml | 90 ------------------= ---- 1 file changed, 90 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,= ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/= aspeed,ast2700-intc.yaml deleted file mode 100644 index 258d21fe6e35..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -intc.yaml +++ /dev/null @@ -1,90 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-int= c.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Aspeed AST2700 Interrupt Controller - -description: - This interrupt controller hardware is second level interrupt controller = that - is hooked to a parent interrupt controller. It's useful to combine multi= ple - interrupt sources into 1 interrupt to parent interrupt controller. - -maintainers: - - Kevin Chen - -properties: - compatible: - enum: - - aspeed,ast2700-intc-ic - - reg: - maxItems: 1 - - interrupt-controller: true - - '#interrupt-cells': - const: 1 - description: - The first cell is the IRQ number, the second cell is the trigger - type as defined in interrupt.txt in this directory. - - interrupts: - minItems: 1 - maxItems: 10 - description: | - Depend to which INTC0 or INTC1 used. - INTC0 and INTC1 are two kinds of interrupt controller with enable an= d raw - status registers for use. - INTC0 is used to assert GIC if interrupt in INTC1 asserted. - INTC1 is used to assert INTC0 if interrupt of modules asserted. - +-----+ +-------+ +---------+---module0 - | GIC |---| INTC0 |--+--| INTC1_0 |---module2 - | | | | | | |---... - +-----+ +-------+ | +---------+---module31 - | - | +---------+---module0 - +---| INTC1_1 |---module2 - | | |---... - | +---------+---module31 - ... - | +---------+---module0 - +---| INTC1_5 |---module2 - | |---... - +---------+---module31 - -required: - - compatible - - reg - - interrupt-controller - - '#interrupt-cells' - - interrupts - -additionalProperties: false - -examples: - - | - #include - - bus { - #address-cells =3D <2>; - #size-cells =3D <2>; - - interrupt-controller@12101b00 { - compatible =3D "aspeed,ast2700-intc-ic"; - reg =3D <0 0x12101b00 0 0x10>; - #interrupt-cells =3D <1>; - interrupt-controller; - interrupts =3D , - , - , - , - , - , - , - , - , - ; - }; - }; --=20 2.34.1