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[34.91.210.221]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b942ef8c95csm42907266b.21.2026.03.06.02.29.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 02:29:59 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Fri, 06 Mar 2026 10:30:00 +0000 Subject: [PATCH v7 09/10] pmdomain: samsung: implement SMC to save / restore TZ config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260306-gs101-pd-v7-9-03f7c7965ba5@linaro.org> References: <20260306-gs101-pd-v7-0-03f7c7965ba5@linaro.org> In-Reply-To: <20260306-gs101-pd-v7-0-03f7c7965ba5@linaro.org> To: Krzysztof Kozlowski , Alim Akhtar , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Ulf Hansson , Liam Girdwood , Mark Brown Cc: Peter Griffin , Tudor Ambarus , Juan Yescas , Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.3 Newer Exynos platforms have a Distributed Trust Zone Protection Control (DTZPC) linked to each power domain. It controls the access permissions to various registers from secure and non-secure world. An SMC call is required to instruct the firmware that the power domain is about to be turned off and again once it was turned on. This allows the firmware to save and restore the DTZPC configuration. Without, register access to various registers becomes impossible from Linux (causing SError), as the PoR configuration doesn't allow access. Neither the requirement for the SMC call, nor its arguments appear to be specific to gs101, as at least Exynos E850 also uses the same as can be seen in [1], hence prefix the new macros simply with EXYNOS_. At least on gs101, this SMC call isn't implemented for all power domains (e.g. it's missing for HSI2 (UFS)), therefore we issue a test SMC to store the configuration during probe, and if it fails we mark a domain as always-on to avoid the SErrors and to avoid unnecessarily retrying for each domain on/off. Link: https://lore.kernel.org/all/20230308233822.31180-4-semen.protsenko@li= naro.org/ [1] Signed-off-by: Andr=C3=A9 Draszik Reviewed-by: Peter Griffin --- drivers/pmdomain/samsung/exynos-pm-domains.c | 96 ++++++++++++++++++++++++= ++-- 1 file changed, 90 insertions(+), 6 deletions(-) diff --git a/drivers/pmdomain/samsung/exynos-pm-domains.c b/drivers/pmdomai= n/samsung/exynos-pm-domains.c index 41a232b3cdaf..f59986b56213 100644 --- a/drivers/pmdomain/samsung/exynos-pm-domains.c +++ b/drivers/pmdomain/samsung/exynos-pm-domains.c @@ -9,6 +9,7 @@ // conjunction with runtime-pm. Support for both device-tree and non-devic= e-tree // based power domain support is included. =20 +#include #include #include #include @@ -16,12 +17,19 @@ #include #include #include +#include #include #include =20 +#define EXYNOS_SMC_CMD_PREPARE_PD_ONOFF 0x82000410 +#define EXYNOS_GET_IN_PD_DOWN 0 +#define EXYNOS_WAKEUP_PD_DOWN 1 +#define EXYNOS_RUNTIME_PM_TZPC_GROUP 2 + struct exynos_pm_domain_config { /* Value for LOCAL_PWR_CFG and STATUS fields for each domain */ u32 local_pwr_cfg; + u32 smc_offset; bool use_parent_regmap; }; =20 @@ -32,11 +40,28 @@ struct exynos_pm_domain { struct regmap *regmap; struct device *dev; struct generic_pm_domain pd; - u32 local_pwr_cfg; + const struct exynos_pm_domain_config *cfg; u32 configuration_reg; u32 status_reg; + phys_addr_t ac_pa; }; =20 +static int exynos_pd_access_controller_power(struct exynos_pm_domain *pd, + bool power_on) +{ + struct arm_smccc_res res; + + if (!pd->ac_pa || !pd->cfg->smc_offset) + return 0; + + arm_smccc_smc(EXYNOS_SMC_CMD_PREPARE_PD_ONOFF, + power_on ? EXYNOS_WAKEUP_PD_DOWN : EXYNOS_GET_IN_PD_DOWN, + pd->ac_pa + pd->cfg->smc_offset, + EXYNOS_RUNTIME_PM_TZPC_GROUP, 0, 0, 0, 0, &res); + + return res.a0; +} + static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) { struct exynos_pm_domain *pd; @@ -45,7 +70,17 @@ static int exynos_pd_power(struct generic_pm_domain *dom= ain, bool power_on) =20 pd =3D container_of(domain, struct exynos_pm_domain, pd); =20 - pwr =3D power_on ? pd->local_pwr_cfg : 0; + if (!power_on) { + err =3D exynos_pd_access_controller_power(pd, power_on); + if (err) { + dev_err(pd->dev, + "SMC for power domain %s %sable failed: %d\n", + domain->name, power_on ? "en" : "dis", err); + return err; + } + } + + pwr =3D power_on ? pd->cfg->local_pwr_cfg : 0; err =3D regmap_write(pd->regmap, pd->configuration_reg, pwr); if (err) { dev_err(pd->dev, @@ -60,7 +95,7 @@ static int exynos_pd_power(struct generic_pm_domain *doma= in, bool power_on) unsigned int val; =20 err =3D regmap_read(pd->regmap, pd->status_reg, &val); - if (err || ((val & pd->local_pwr_cfg) !=3D pwr)) { + if (err || ((val & pd->cfg->local_pwr_cfg) !=3D pwr)) { cpu_relax(); usleep_range(80, 100); continue; @@ -72,9 +107,21 @@ static int exynos_pd_power(struct generic_pm_domain *do= main, bool power_on) if (!timeout && !err) /* Only return timeout if no other error also occurred. */ err =3D -ETIMEDOUT; - if (err) + if (err) { dev_err(pd->dev, "Power domain %s %sable failed: %d\n", domain->name, power_on ? "en" : "dis", err); + return err; + } + + if (power_on) { + err =3D exynos_pd_access_controller_power(pd, power_on); + if (err) { + dev_err(pd->dev, + "SMC for power domain %s %sable failed: %d\n", + domain->name, power_on ? "en" : "dis", err); + return err; + } + } =20 return err; } @@ -99,6 +146,7 @@ static const struct exynos_pm_domain_config exynos5433_c= fg =3D { =20 static const struct exynos_pm_domain_config gs101_cfg =3D { .local_pwr_cfg =3D BIT(0), + .smc_offset =3D 0x0204, .use_parent_regmap =3D true, }; =20 @@ -126,6 +174,38 @@ static const char *exynos_get_domain_name(struct devic= e *dev, return devm_kstrdup_const(dev, name, GFP_KERNEL); } =20 +static int exynos_pd_get_access_controller(struct exynos_pm_domain *pd) +{ + struct device_node *ac_np; + struct resource ac_res; + int ret; + + ac_np =3D of_parse_phandle(pd->dev->of_node, "samsung,dtzpc", 0); + if (!ac_np) + return 0; + + ret =3D of_address_to_resource(ac_np, 0, &ac_res); + of_node_put(ac_np); + if (ret) + return dev_err_probe(pd->dev, ret, + "failed to get access controller\n"); + + pd->ac_pa =3D ac_res.start; + + /* + * For some domains, TZ save/restore might not be implemented. If that + * is the case, simply mark it as always on, as otherwise a power cycle + * will lead to lost TZ configuration, making it impossible to access + * registers from Linux afterwards. + */ + if (exynos_pd_access_controller_power(pd, false) =3D=3D -ENOENT) { + pd->ac_pa =3D 0; + pd->pd.flags |=3D GENPD_FLAG_ALWAYS_ON; + } + + return 0; +} + static int exynos_pd_probe(struct platform_device *pdev) { const struct exynos_pm_domain_config *pm_domain_cfg; @@ -195,10 +275,14 @@ static int exynos_pd_probe(struct platform_device *pd= ev) =20 pd->pd.power_off =3D exynos_pd_power_off; pd->pd.power_on =3D exynos_pd_power_on; - pd->local_pwr_cfg =3D pm_domain_cfg->local_pwr_cfg; + pd->cfg =3D pm_domain_cfg; pd->configuration_reg +=3D 0; pd->status_reg +=3D 4; =20 + ret =3D exynos_pd_get_access_controller(pd); + if (ret) + return ret; + /* * Some Samsung platforms with bootloaders turning on the splash-screen * and handing it over to the kernel, requires the power-domains to be @@ -212,7 +296,7 @@ static int exynos_pd_probe(struct platform_device *pdev) if (ret) return dev_err_probe(dev, ret, "failed to read status"); =20 - on =3D val & pd->local_pwr_cfg; + on =3D val & pd->cfg->local_pwr_cfg; =20 pm_genpd_init(&pd->pd, NULL, !on); ret =3D of_genpd_add_provider_simple(np, &pd->pd); --=20 2.53.0.473.g4a7958ca14-goog