From nobody Thu Apr 9 17:15:55 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 041062264AB for ; Fri, 6 Mar 2026 10:24:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772792657; cv=none; b=WVKHLk3OoqV66x8TlT8eubyPtA79vi/wZ5ovhEH8yFazE648WYwsllc+OGDG+BxZ571zavP73QyPUqiHYwnx+HK9fwXkHz/eKZE7I5gv2hpUlq9WWXSjMTzl//1ttz7P3HcsvK+rIQE5uqL0edVDraPs4MOzzgAVrCcy0ATMLk0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772792657; c=relaxed/simple; bh=BloDWQWMfJ0ERbjWfUnRoTVFCa3vllTd7BOk4Grbihk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To:Cc; b=d+5EVwP/wa09b4wyaKS3/5Dd2phXEi+W9RIM9mENbEeBqRp8wNoSXcGQb5ezZKOsM42k7GMXLEk92CBPqTkE9YNbA/4kb5Fd7oh999y1jKVHMfkySDXgXvTXeKB8NePfUu4T8fQzulv4PJevndX921Bjlk64tom7Rhi6eQW/9qc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=sVXHyXLC; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="sVXHyXLC" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id 3B2C6C4042C; Fri, 6 Mar 2026 10:24:26 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 392385FF92; Fri, 6 Mar 2026 10:24:07 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 9988D1036991C; Fri, 6 Mar 2026 11:24:02 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1772792646; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding; bh=vvms8os0Db8p9kw4wcOWZOZmv0C6Az1ptb21jcBPIYw=; b=sVXHyXLCY5Erp2gsraYrnuT3PAf2FtOWyALYFzrsMWHSduI/Qbm4jiv2pS2AP51cC6CoCD wUZPjze3EKR8422EHxrcBaTQIUZ1y2ujAoPjZtz1wmc06riMjiO3Dguyeh7ogMBdXyZ4pi KqIIB8gjM3ybpnKQkDFdR6BYonC66OCRT2Fx4yZWeaVS/Nn7W5UZ0q1MTWhPdvaXhHO0wN 5IbJu2VjquyHhs6cm/ORpC3yMVF1BUCZ3DOVGOxOrOofL2m9SKR0dvbfwPh2hTqU6t7YeP vR3cA8k7+VpEsKVr63LcSK0TQDjqcaHu0pixvZnAf5sUUPisa6NQWJ2gIxkbng== From: Gregory CLEMENT Date: Fri, 06 Mar 2026 11:23:58 +0100 Subject: [PATCH v2] phy: cadence: Sierra: Do not modify register when getting parent clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260306-fix_sierra_get_parent-v2-1-cafe89ee5382@bootlin.com> X-B4-Tracking: v=1; b=H4sIAD2rqmkC/4WNXQrCMBCEr1L22UiTmv745D2klLiu7YImZROKU np3Yy/g4zfMfLNCJGGKcC5WEFo4cvAZzKEAnJwfSfE9M5jS1GVVWvXg9xCZRNwwUhpmJ+ST6rA 9VRaxttRA3s5Cubh7r33miWMK8tlvFv1L/xkXrbRyDeqWOqrRtpdbCOnJ/ojhBf22bV/M/bUfv AAAAA== X-Change-ID: 20260305-fix_sierra_get_parent-9c8435cc65e7 To: Vinod Koul , Neil Armstrong , Aswath Govindraju , Swapnil Jakhade Cc: =?utf-8?q?Th=C3=A9o_Lebrun?= , Thomas Petazzoni , Vladimir Kondratiev , linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Gregory CLEMENT X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 The get_parent() callback for the PLL_CMNLC1 clock was incorrectly writing to the register while determining the parent clock index. This unintended register access forces the PHY back into training mode. If the PHY is already configured, this unexpected change prevents it from exiting training mode. Remove the register write operation to ensure the PHY remains stable during the get_parent() callback. Fixes: da08aab940092 ("phy: cadence: Sierra: Fix to get correct parent for = mux clocks") Signed-off-by: Gregory CLEMENT Reviewed-by: Neil Armstrong --- Changes in v2: - Removed unused variable spotted by the 0-DAY CI Kernel Test Service: https://lore.kernel.org/oe-kbuild-all/202603061235.hrl27Jvj-lkp@intel.com/ - Link to v1: https://lore.kernel.org/r/20260305-fix_sierra_get_parent-v1-1= -a7c18e9e6c58@bootlin.com --- drivers/phy/cadence/phy-cadence-sierra.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence= /phy-cadence-sierra.c index 92ab1a31646ae..dbeda7f01cbb2 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -698,23 +698,16 @@ static const struct phy_ops noop_ops =3D { static u8 cdns_sierra_pll_mux_get_parent(struct clk_hw *hw) { struct cdns_sierra_pll_mux *mux =3D to_cdns_sierra_pll_mux(hw); - struct regmap_field *plllc1en_field =3D mux->plllc1en_field; - struct regmap_field *termen_field =3D mux->termen_field; struct regmap_field *field =3D mux->pfdclk_sel_preg; unsigned int val; int index; =20 regmap_field_read(field, &val); =20 - if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1])) { + if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1])) index =3D clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC1]= , 0, val); - if (index =3D=3D 1) { - regmap_field_write(plllc1en_field, 1); - regmap_field_write(termen_field, 1); - } - } else { + else index =3D clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC],= 0, val); - } =20 return index; } --- base-commit: 11439c4635edd669ae435eec308f4ab8a0804808 change-id: 20260305-fix_sierra_get_parent-9c8435cc65e7 Best regards, --=20 Gr=C3=A9gory CLEMENT, Bootlin Embedded Linux and Kernel engineering https://bootlin.com