From nobody Thu Apr 9 19:23:17 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF41F379ED7 for ; Fri, 6 Mar 2026 08:44:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772786695; cv=none; b=Ew9+5V46Dgxh43BFVXUA6yWGZL58SAzYpbqsYw4fA7Ewqt7+uDimKufSq4C2DG+P3AtTtTFZTnFrrahe8tF65Y2yilvHUpwupO0P0oQvjd0dXyk/kDmkGI5aDqPejC3QiL6sph7je8WYeYG8ARvI/9gqgYLuW9Wc3+XdaohpeGk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772786695; c=relaxed/simple; bh=KA18KGyDt3RXzJgye73pZlEUQ6kGq8j/JfGqg316kMc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AEkxemFOAvn9R/pmawgUwAH1Hg18mfEfxzn073dI+HKOEVTVCQ3GvBCuJolHWX3fH9C4oasLUBVkRRfKPTxd30cFo8ps9ZZmumZ8liKvfvloqy0qU0fJlRSOVpefv5SF1L1p7kkz0yrpvisfDeTlGcmDqE7W2FXwQI6BP8/NDTo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=E9NQLOyN; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=IrP0T7VK; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="E9NQLOyN"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="IrP0T7VK" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6264aErQ3219011 for ; Fri, 6 Mar 2026 08:44:53 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 1DBByKuzvkaKJ29qKLEZiH31R+C0wZhUtK6HatDKMR0=; b=E9NQLOyNZkWhiy5n DfIq5YauA1Uh7DCF7AvZJU88adXqZc32UHxfxX3mu9hwfvWc2MsqtQkQSjOncqiA BUUvNGnCkKFBGgj96qKB7yPpXD2oHB6gT3YOHcA10xN64hYcd7N+amKyFYGIAU0V ZEMDjbMrwrt2uPRP+5YRady2NXobmtyn36zCAx4fbDlYxVQ47NWSVyex2wrSwXIL De7gpALjqw8Jh4L806KKdbzyL/ZoXu0k43ZIw4iRy00DU3OkKPrpG6rNipi6xY76 N6a175JAUGsx/sUTbqb807sJdbL0te+73S/7M3PrKcKg+5shCdqvmvfkC59ZoU0J eLYv2g== Received: from mail-pg1-f197.google.com (mail-pg1-f197.google.com [209.85.215.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cqf25tdq2-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 06 Mar 2026 08:44:52 +0000 (GMT) Received: by mail-pg1-f197.google.com with SMTP id 41be03b00d2f7-c70ea91bfe1so5584908a12.1 for ; Fri, 06 Mar 2026 00:44:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1772786692; x=1773391492; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=1DBByKuzvkaKJ29qKLEZiH31R+C0wZhUtK6HatDKMR0=; b=IrP0T7VKFmBxM1MJEAz9ws1Ejo36Wb2Lyz5glKy8K+YjTQUpMVcXiJiq4pyK1LJXbO 9XKFP7FXuN9Gv1MBdLV/odE9hwOcim8xg2dzhCXdcHDxLT7moatgKjwiJWU8rRkG5Gfs 2txAxXX5d3Bqp2U3/OJn15HkbIH/t2rqcp3JUOSUBEP5/7Sma9nBq/+oipUSnyGG+Ev5 HqgFayt6QEWwn6n2xEpQ5saBry/ZtNZRyWd7zHE3lOA8anBZfKNHVSKfvj2qk64+cEDU /yQI5xHicgQqfPX+YxiGUo4aHIbPeQyJdm+p1NPcw9LTWp3tgVjQuM/c/EITW1wluiKw 0zpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772786692; x=1773391492; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=1DBByKuzvkaKJ29qKLEZiH31R+C0wZhUtK6HatDKMR0=; b=jhPMo9HtMJN/sGPAh1x92W1whkglzlPLpIXa29hPdGiRRtvSk9+DgFpt4y6nRrJe7Y 8kLjJ+u506U0ZBhId/DUHuWcFy1hBiJNR1zo0SHhXYyYG8GrYn1cro2e2/vYgqHwyyKd FTgoL1/tf/2uqG5rf3N8OhTpcH+dqSOFz7eKn3OYkyfzOMCOi8UI9Xnt1kpQPgthPkNn cb+7v2jwIXCk2AT9T4GNuDmamsIS8hBK2iTsdDYhwvWiVphUHiTt0apKR2lUo1yJGJdE vTSuaCqHO8tbVJ8SFEHqCLGxnv868RtCV2s6091xEa7zMjFRbDhMfUpgmFTbkGUFaKb6 V5Pg== X-Forwarded-Encrypted: i=1; AJvYcCXZCVgXcAJ3VL2c4RYLiyjM2IlVAayanHuUuxpURM86Ig/wwyeZH6Q661ELRijwpKOqg5m5R51cOX4/uXQ=@vger.kernel.org X-Gm-Message-State: AOJu0YwXS3C0w68Aogz6c79L1JEQurmxwdETnxs3UwQk1i9+TJcord5m hrWm8suoqWItBeG0PEGSNFTP3Mvb3E0lvk7xg39ZRvIoFSsYktFQdefx/Pw8/DslW6iJdOINNvl z0kFc7AsxBWQy/EhoX2KZQ4aMF5JznTxZ1gYrr7KiPBpcCwBH8r4vRJlipb/sEd9lkAw= X-Gm-Gg: ATEYQzz4iXKo9widpF/02idICKiHWygAJgLJa5EhoLErB0V0kB4rb4P/L80jWO7Xzf1 9P9/mv72/PAUsGhDRJTwFYKUDjytRpbUG6totm/bAwmJH+/DwjglBBRGa4BApxXTEBRUstoNLgw y0xDwBNf3ZV12PxU6DSl/2TMDOpbYiFI0LBAShqfhTWpKIZACaWrM58S2AXRllsxI9moZEyHb7U 2PLadWOOZ1wt8vYSzy2EkOjELsPnsENWwXjCFE+dxlFKc2OEV4YrbYuwQ/dK+r47uz/RQmn2SAH yY4VDAzSXjG8HgCNGXQURZwBxSZCK5MBBQIcw1TBcSHD+W/XgtDWKsC8gAUjPn6uiTd6lfIg14y 5T0hF63Js0+339i11rHZF7WxUzm+GTgz68nKyMmHzQ1VhiOac8VyJJR8RhwTeND+dMhtU1lNX+a Ipw3O25I2AwGezFKydzmdd X-Received: by 2002:a05:6a00:3c8a:b0:822:1dbc:e75d with SMTP id d2e1a72fcca58-829a2d65577mr1402048b3a.1.1772786692005; Fri, 06 Mar 2026 00:44:52 -0800 (PST) X-Received: by 2002:a05:6a00:3c8a:b0:822:1dbc:e75d with SMTP id d2e1a72fcca58-829a2d65577mr1402017b3a.1.1772786691497; Fri, 06 Mar 2026 00:44:51 -0800 (PST) Received: from WANGAOW-LAB01.ap.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-829a4636c74sm1393573b3a.12.2026.03.06.00.44.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 00:44:51 -0800 (PST) From: Wangao Wang Date: Fri, 06 Mar 2026 16:44:31 +0800 Subject: [PATCH v2 3/5] media: iris: Add IRIS_BSE_HW_CLK handling in vpu3 power on/off sequence Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260306-enable_iris_on_purwa-v2-3-75fa80a0a9e3@oss.qualcomm.com> References: <20260306-enable_iris_on_purwa-v2-0-75fa80a0a9e3@oss.qualcomm.com> In-Reply-To: <20260306-enable_iris_on_purwa-v2-0-75fa80a0a9e3@oss.qualcomm.com> To: Bryan O'Donoghue , Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Wangao Wang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772786674; l=4048; i=wangao.wang@oss.qualcomm.com; s=20251021; h=from:subject:message-id; bh=KA18KGyDt3RXzJgye73pZlEUQ6kGq8j/JfGqg316kMc=; b=Bnvf2rulCR4TGvaytwZz4dESvtFbUyOgS8wcQ6BaCMuc36BwTd/pcJL8jYXNW1sTxn2YhlI2k s5EKxIKPxr7CP/a5OWyzrsJMdAaUPF0P7LFmnofsuew7ghIvpuYIoOW X-Developer-Key: i=wangao.wang@oss.qualcomm.com; a=ed25519; pk=bUPgYblBUAsoPyGfssbNR7ZXUSGF8v1VF4FJzSO6/aA= X-Proofpoint-ORIG-GUID: -KAAgbSzFilpwR1ndN5YlZ_AcRDTVDp7 X-Authority-Analysis: v=2.4 cv=Uvdu9uwB c=1 sm=1 tr=0 ts=69aa9404 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=RNMrTprwP3u3wXAvS-YA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA2MDA4MiBTYWx0ZWRfX+4xHho1AlpWo HA8SGT3m2KrH/laqdhVJ3MaYgKjZstIffM+qQG06QbmciskYsdW65APEhBii2XDpVMwifFd7ANy ikX9EVk2AGa6MSy84FjFYDulwUmbfWSPuUolMR4LDOBXwAo4OjDaCKxCf8qOoN3/cQ72tNXbAkX 9veKf7AnKCE9nP5jQoFeN8WqeyfTrhS1UYEsR6yBlrNhXZ7bB3mHrs8SKV5vcRXrQjx5aY+oW5U DNQI+ap/Nh1LLwvwPVh/HDQvL74pyNBJ7GLzKqwydo1d20f/weh4mwFgLiNmP2csP6+P4rRaTUw PxOt1a8o90efrXuQ2cFlTLClxx8WPU0d533Gypijg9u7IgpM6cyUwk6zbRmKNzLuBqosbcLlaiR MtHodawhqOuGF5s1gW4lZ6Ys2F/r9oUwheUzpcVIx2xQ6scdksg9+ZdLSPMo/lOBjGiovxI3wf9 NTZDn41hXsSgQQY4UvA== X-Proofpoint-GUID: -KAAgbSzFilpwR1ndN5YlZ_AcRDTVDp7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-06_03,2026-03-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 malwarescore=0 spamscore=0 priorityscore=1501 suspectscore=0 impostorscore=0 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603060082 On X1P42100 the Iris block has an extra BSE clock. Wire this clock into the power on/off sequence. The BSE clock is used to drive the Bin Stream Engine, which is a sub-block of the video codec hardware responsible for bitstream-level processing. It is required to be enabled separately from the core clock to ensure proper codec operation. Signed-off-by: Wangao Wang --- drivers/media/platform/qcom/iris/iris_vpu3x.c | 55 +++++++++++++++++++++++= ++-- 1 file changed, 51 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c index fe4423b951b1e9e31d06dffc69d18071cc985731..3f9e67604ef6aad773837df5843= 62446052e34c2 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -27,6 +27,53 @@ static bool iris_vpu3x_hw_power_collapsed(struct iris_co= re *core) return pwr_status ? false : true; } =20 +static int iris_vpu3_power_on_hw(struct iris_core *core) +{ + int ret; + + ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_= HW_POWER_DOMAIN]); + if (ret) + return ret; + + ret =3D iris_prepare_enable_clock(core, IRIS_HW_CLK); + if (ret) + goto err_disable_power; + + ret =3D iris_prepare_enable_clock(core, IRIS_HW_AHB_CLK); + if (ret && ret !=3D -ENOENT) + goto err_disable_hw_clock; + + ret =3D iris_prepare_enable_clock(core, IRIS_BSE_HW_CLK); + if (ret && ret !=3D -ENOENT) + goto err_disable_hw_ahb_clock; + + ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER= _DOMAIN], true); + if (ret) + goto err_disable_bse_hw_clock; + + return 0; + +err_disable_bse_hw_clock: + iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); +err_disable_hw_ahb_clock: + iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); +err_disable_hw_clock: + iris_disable_unprepare_clock(core, IRIS_HW_CLK); +err_disable_power: + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); + + return ret; +} + +static void iris_vpu3_power_off_hw(struct iris_core *core) +{ + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]= , false); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); + iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); + iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); + iris_disable_unprepare_clock(core, IRIS_HW_CLK); +} + static void iris_vpu3_power_off_hardware(struct iris_core *core) { u32 reg_val =3D 0, value, i; @@ -68,7 +115,7 @@ static void iris_vpu3_power_off_hardware(struct iris_cor= e *core) writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); =20 disable_power: - iris_vpu_power_off_hw(core); + iris_vpu3_power_off_hw(core); } =20 static void iris_vpu33_power_off_hardware(struct iris_core *core) @@ -131,7 +178,7 @@ static void iris_vpu33_power_off_hardware(struct iris_c= ore *core) writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); =20 disable_power: - iris_vpu_power_off_hw(core); + iris_vpu3_power_off_hw(core); } =20 static int iris_vpu33_power_off_controller(struct iris_core *core) @@ -262,7 +309,7 @@ static void iris_vpu35_power_off_hw(struct iris_core *c= ore) =20 const struct vpu_ops iris_vpu3_ops =3D { .power_off_hw =3D iris_vpu3_power_off_hardware, - .power_on_hw =3D iris_vpu_power_on_hw, + .power_on_hw =3D iris_vpu3_power_on_hw, .power_off_controller =3D iris_vpu_power_off_controller, .power_on_controller =3D iris_vpu_power_on_controller, .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, @@ -270,7 +317,7 @@ const struct vpu_ops iris_vpu3_ops =3D { =20 const struct vpu_ops iris_vpu33_ops =3D { .power_off_hw =3D iris_vpu33_power_off_hardware, - .power_on_hw =3D iris_vpu_power_on_hw, + .power_on_hw =3D iris_vpu3_power_on_hw, .power_off_controller =3D iris_vpu33_power_off_controller, .power_on_controller =3D iris_vpu_power_on_controller, .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, --=20 2.43.0