From nobody Sat Apr 11 12:22:04 2026 Received: from mxout70.expurgate.net (mxout70.expurgate.net [194.37.255.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48A4533AD82 for ; Fri, 6 Mar 2026 08:27:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=194.37.255.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772785673; cv=none; b=GnqmA1Rq1muOa+QT4gTGkTCqRthPaB5zzpusTN8Q0IfvFxl1VeQ/GLeMUpAv3vuD1FDwwYQH60MHTqU2hvYjb2dKSWiJWCQn8dno3lnW7DY+IFMGMK/a1I3lN9TOWaMkcyXBVQjY3tLg2GgkTTaZSnicCfz6XCHLRy2KP7tX/oY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772785673; c=relaxed/simple; bh=NQZf/OEsxVfNZzzCfUgbDqJjVaITgzeMpP38x6OoxuU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:Cc; b=Xwan1P8g3NT6x0ExM/+aie0d3/nfJd8hFmelxuzO0JIb/bxVqpIKMh5BXpUoJ6oX1wqtA29FM7d/QlyDwXhVU9+KKqapfwUvL5DsuJtISLgWr8OYGlIOZUmzm9uXk3A7O31YB/2IPKdNxbQuZozUOxPNAkQ0+6gzC3xInUsMuOI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dev.tdt.de; spf=pass smtp.mailfrom=dev.tdt.de; dkim=temperror (0-bit key) header.d=dev.tdt.de header.i=@dev.tdt.de header.b=PxsJxpO5; arc=none smtp.client-ip=194.37.255.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dev.tdt.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=dev.tdt.de Authentication-Results: smtp.subspace.kernel.org; dkim=temperror (0-bit key) header.d=dev.tdt.de header.i=@dev.tdt.de header.b="PxsJxpO5" Received: from [194.37.255.9] (helo=mxout.expurgate.net) by relay.expurgate.net with smtp (Exim 4.92) (envelope-from ) id 1vyQX2-0024GR-TK; Fri, 06 Mar 2026 09:27:36 +0100 Received: from [195.243.126.94] (helo=securemail.tdt.de) by relay.expurgate.net with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1vyQX1-003amK-VZ; Fri, 06 Mar 2026 09:27:36 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dev.tdt.de; s=z1-selector1; t=1772785655; bh=OddomWiS/o2+wUkBO5Mh6nGaiQK78lX0jopPH2pp1iU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=PxsJxpO5pogivPYNhMnpTVKFVasIjXP6GGGyxfBy12umQLnneklhkw0i80O6xBE8k 3WA4OVJEDiPqFqXXyb/dlldRglV58+uyNNQVSTgMbcrWnHp1UCPFWldFkb0+8fE1QR hUu12c+Y7BKCgBwtUKbGARDjqCCILvI3zo6xVh4dkGvYkY4doSFDkwx7IX3qyyarXM xquxNxiCuYnkc9YheBiqmjChN2BKC8Gzp/zRjAuq3fglUTxwBrTcO+MTixzu/ECLq5 kEa2Z+26VWMmCcS7CGoalLhp11uoRQptDg7dSNLHZygMd9wXUxb62a6p0976vvlK3c VIcG9XSdsoCyg== Received: from securemail.tdt.de (localhost [127.0.0.1]) by securemail.tdt.de (Postfix) with ESMTP id 74E91240036; Fri, 6 Mar 2026 09:27:35 +0100 (CET) Received: from mail.dev.tdt.de (unknown [10.2.4.42]) by securemail.tdt.de (Postfix) with ESMTP id 5DF0A240046; Fri, 6 Mar 2026 09:27:35 +0100 (CET) Received: from [127.0.1.1] (unknown [10.2.3.19]) by mail.dev.tdt.de (Postfix) with ESMTPSA id 41FBA22F1D; Fri, 6 Mar 2026 09:27:35 +0100 (CET) From: Martin Schiller Date: Fri, 06 Mar 2026 09:27:25 +0100 Subject: [PATCH 2/2] x86/cpu/intel: Add EIST workaround for Lightning Mountain. Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260306-cpufreq_lgm-v1-2-47f104aed7c2@dev.tdt.de> References: <20260306-cpufreq_lgm-v1-0-47f104aed7c2@dev.tdt.de> In-Reply-To: <20260306-cpufreq_lgm-v1-0-47f104aed7c2@dev.tdt.de> To: Srinivas Pandruvada , Len Brown , "Rafael J. Wysocki" , Viresh Kumar , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Florian Eckert , Martin Schiller X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772785654; l=1815; i=ms@dev.tdt.de; s=20260220; h=from:subject:message-id; bh=NQZf/OEsxVfNZzzCfUgbDqJjVaITgzeMpP38x6OoxuU=; b=n7kBE45BDvRVzxlmR90+0ENMU4zLf5zMABoNth93V9dE0d0H27WezM9/72+wl+4VpK/mW1MG2 AyU3E4WxRATB/syl3Kl6uV6GHx60WZBuslcTg7OZla+hOgKDs901/Vw X-Developer-Key: i=ms@dev.tdt.de; a=ed25519; pk=MAojd7D5IafMnqCYSFC7hY/u/jppX58CLIEhsEsSOYE= X-purgate: clean X-purgate-ID: 151534::1772785656-09631836-E863CE59/0/0 X-purgate-type: clean Add a workaround for Intel / MaxLinear Lightning Mountain to enable Enhanced Intel SpeedStep Technology (EIST) for each cpu. Otherwise, the frequency on some cpus is locked to the minimum value of 624 MHz. This usually would be the job of the BIOS / bootloader, but U-Boot only enables it on the cpu on which it is running. Signed-off-by: Martin Schiller --- arch/x86/kernel/cpu/intel.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 98ae4c37c93eccf775d5632acf122603a19918a8..e49df04e8d491158cc48f8d8bef= 824c434256d09 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -466,6 +466,29 @@ static void intel_workarounds(struct cpuinfo_x86 *c) #else static void intel_workarounds(struct cpuinfo_x86 *c) { + u64 misc_enable; + + /* + * Intel / MaxLinear Lightning Mountain workaround to enable Enhanced + * Intel SpeedStep Technology (EIST) for each cpu. Otherwise, the + * frequency on some cpus is locked to the minimum value of 624 MHz. + * This usually would be the job of the BIOS / bootloader, but U-Boot + * only enables it on the cpu on which it is running. + */ + if (c->x86_vfm =3D=3D INTEL_ATOM_AIRMONT_NP) { + rdmsrq(MSR_IA32_MISC_ENABLE, misc_enable); + if (!(misc_enable & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) { + misc_enable |=3D MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP; + wrmsrq(MSR_IA32_MISC_ENABLE, misc_enable); + + /* check to see if it was enabled successfully */ + rdmsrq(MSR_IA32_MISC_ENABLE, misc_enable); + if (!(misc_enable & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) { + pr_info("CPU%d: Can't enable Enhanced SpeedStep\n", + c->cpu_index); + } + } + } } #endif =20 --=20 2.47.3