From nobody Sat Apr 11 10:48:08 2026 Received: from mxout70.expurgate.net (mxout70.expurgate.net [194.37.255.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 489DC338596 for ; Fri, 6 Mar 2026 08:27:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=194.37.255.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772785673; cv=none; b=m0uk58QKCGTDignkb2CksrNlyH3Gc++lUyc2P9aHyEXNvEApWbpT9j1pvBTe8cG2BmaTrNk/7hzK0i0SapcB2axIjnK8Xg0HcD0uA1m2IYxKvVLTk6JnAU/9JNgfkCFGN/QGy+jisNjvtV7E6fR47VlEnayrhy4DjfQWww1C2uc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772785673; c=relaxed/simple; bh=XBcUhX+9+tVjmqZS3FsSPqoEmsndYoetIvCSFJeCjBA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:Cc; b=Y7q9ojBlVeG/wgF8DoR7HQk1s8brF5DY8X+uNVtgjHXGzvxpUihIzwuJV4RcOK23hyBhX6WiGjKdvjY0vnLO2Fc1bAwRsrJ+aVIDje2L/eUsQ4cxUee0x83+TNL0OwC6t4IZY5MDE4F2DZ/hjI8hB644JIeOkMiY5SJl4U1102k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dev.tdt.de; spf=pass smtp.mailfrom=dev.tdt.de; dkim=temperror (0-bit key) header.d=dev.tdt.de header.i=@dev.tdt.de header.b=TuWyeYUG; arc=none smtp.client-ip=194.37.255.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dev.tdt.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=dev.tdt.de Authentication-Results: smtp.subspace.kernel.org; dkim=temperror (0-bit key) header.d=dev.tdt.de header.i=@dev.tdt.de header.b="TuWyeYUG" Received: from [194.37.255.9] (helo=mxout.expurgate.net) by relay.expurgate.net with smtp (Exim 4.92) (envelope-from ) id 1vyQX3-0024Gu-FG; Fri, 06 Mar 2026 09:27:37 +0100 Received: from [195.243.126.94] (helo=securemail.tdt.de) by relay.expurgate.net with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1vyQX1-007St2-Uf; Fri, 06 Mar 2026 09:27:35 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dev.tdt.de; s=z1-selector1; t=1772785655; bh=H5/TaKe7u4NR6EQ6rZ7iQQrNmQdWHE1NfDo1A435cCQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=TuWyeYUGiOgx7BHb8JBQyuZ6CnTKg3/DU49pw+GMrworor8D3W/TSAkMvqDTSxwwL lCTg07uudJuL5Kq5CvvZy3JloOoXChpUaVji7EqLm81gQEmW9v9bWOTQ6Ua/KbS9N/ etUyut8HcFV0FXaGGfiLbMDbOFClwQ8iRp+w8++TOuqIFcyVgkdNgFnhxNNyjpKphp PUN76cRZPEoZuaa1OFGz3zLxv4ySjIxxpPJ4PWSIy48rjl071dv/c0Gh6h8aLRawhb sd+jpHpyg1mDJkfWYJ8aD6J4Dzs+zaVh6B463tKwgXCaY5R4fC9Di8dzj/mxDKdBev /jeAN72PAuDVw== Received: from securemail.tdt.de (localhost [127.0.0.1]) by securemail.tdt.de (Postfix) with ESMTP id 59467240045; Fri, 6 Mar 2026 09:27:35 +0100 (CET) Received: from mail.dev.tdt.de (unknown [10.2.4.42]) by securemail.tdt.de (Postfix) with ESMTP id 4369B240040; Fri, 6 Mar 2026 09:27:35 +0100 (CET) Received: from [127.0.1.1] (unknown [10.2.3.19]) by mail.dev.tdt.de (Postfix) with ESMTPSA id 210E323267; Fri, 6 Mar 2026 09:27:35 +0100 (CET) From: Martin Schiller Date: Fri, 06 Mar 2026 09:27:24 +0100 Subject: [PATCH 1/2] cpufreq: intel_pstate: Add Lightning Mountain support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260306-cpufreq_lgm-v1-1-47f104aed7c2@dev.tdt.de> References: <20260306-cpufreq_lgm-v1-0-47f104aed7c2@dev.tdt.de> In-Reply-To: <20260306-cpufreq_lgm-v1-0-47f104aed7c2@dev.tdt.de> To: Srinivas Pandruvada , Len Brown , "Rafael J. Wysocki" , Viresh Kumar , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Florian Eckert , Martin Schiller X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772785654; l=3144; i=ms@dev.tdt.de; s=20260220; h=from:subject:message-id; bh=XBcUhX+9+tVjmqZS3FsSPqoEmsndYoetIvCSFJeCjBA=; b=LLEwtXt6rPzkO/7L3NXXb2//R80dftR7X7jOmT3VSbXoU2zbztF06r17D7Os8RJfvf3TDqpWv fhq6Fb4TGM+DaCrHUdYncAK1xzvfBb8wAbkYRBhuDdfD3vH5/ycBcsD X-Developer-Key: i=ms@dev.tdt.de; a=ed25519; pk=MAojd7D5IafMnqCYSFC7hY/u/jppX58CLIEhsEsSOYE= X-purgate: clean X-purgate-ID: 151534::1772785656-0AE34836-1187AFE2/0/0 X-purgate-type: clean This adds Intel / MaxLinear Lightning Mountain (LGM) support to the intel P-state driver. Although the LGM is related to the AIRMONT (Atom), it uses different register values and frequency table. This changes are based on patched kernel sources of the MaxLinear SDK, which can be found at https://github.com/maxlinear/linux Signed-off-by: Martin Schiller --- drivers/cpufreq/intel_pstate.c | 62 ++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 62 insertions(+) diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c index ec4abe3745736b0130fae117d037c5204e048f80..330a04d9af15309e231c5f8f3dc= 78e9eea0635e6 100644 --- a/drivers/cpufreq/intel_pstate.c +++ b/drivers/cpufreq/intel_pstate.c @@ -2150,6 +2150,58 @@ static void atom_get_vid(struct cpudata *cpudata) cpudata->vid.turbo =3D value & 0x7f; } =20 +static int lgm_get_max_pstate(int not_used) +{ + /* The Lightning Mountain hardware seems to be designed to run up to + * P-state 32 (2496 MHz), which is what atom_get_max_pstate() will + * return. But the Data Sheet shows a max. supported CPU freqency of + * 2028 MHz and also the code from the MaxLinear SDK tells, that "the + * max. P-state is currently not supported". So we have to manually + * limit the P-state here to 26 (2028 MHz). + */ + return 26; +} + +static u64 lgm_get_val(struct cpudata *cpudata, int pstate) +{ + u64 val; + int index; + + static const u32 vid[] =3D { + 2, 2, 2, 2, 3, 3, 3, 4, 5, 6, 7, 7, 7 + }; + + pstate &=3D ~0x1; + + val =3D (u64)pstate << 8; + + index =3D (pstate - cpudata->pstate.min_pstate) >> 1; + WARN_ON(index >=3D ARRAY_SIZE(vid)); + return val | vid[index]; +} + +static int lgm_get_scaling(void) +{ + u64 value; + int i, xtal, div, multi; + + static const u32 freq[8] =3D { + 26000, 25000, 19200, 38400, + 40000, 40000, 40000, 40000 + }; + + rdmsrq(MSR_FSB_FREQ, value); + i =3D value & 0x1f; + WARN_ON(i !=3D 0x1f); + + xtal =3D freq[(value >> 32) & 0x7]; + div =3D (value >> 40) & 0xff; + WARN_ON(div =3D=3D 0x0); + multi =3D (value >> 48) & 0xff; + + return (xtal * multi) / div; +} + static int core_get_min_pstate(int cpu) { u64 value; @@ -2669,6 +2721,15 @@ static const struct pstate_funcs airmont_funcs =3D { .get_vid =3D atom_get_vid, }; =20 +static const struct pstate_funcs lgm_funcs =3D { + .get_max =3D lgm_get_max_pstate, + .get_max_physical =3D lgm_get_max_pstate, + .get_min =3D atom_get_min_pstate, + .get_turbo =3D atom_get_turbo_pstate, + .get_val =3D lgm_get_val, + .get_scaling =3D lgm_get_scaling, +}; + static const struct pstate_funcs knl_funcs =3D { .get_max =3D core_get_max_pstate, .get_max_physical =3D core_get_max_pstate_physical, @@ -2695,6 +2756,7 @@ static const struct x86_cpu_id intel_pstate_cpu_ids[]= =3D { X86_MATCH(INTEL_HASWELL_G, core_funcs), X86_MATCH(INTEL_BROADWELL_G, core_funcs), X86_MATCH(INTEL_ATOM_AIRMONT, airmont_funcs), + X86_MATCH(INTEL_ATOM_AIRMONT_NP, lgm_funcs), X86_MATCH(INTEL_SKYLAKE_L, core_funcs), X86_MATCH(INTEL_BROADWELL_X, core_funcs), X86_MATCH(INTEL_SKYLAKE, core_funcs), --=20 2.47.3 From nobody Sat Apr 11 10:48:08 2026 Received: from mxout70.expurgate.net (mxout70.expurgate.net [194.37.255.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48A4533AD82 for ; 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Fri, 6 Mar 2026 09:27:35 +0100 (CET) Received: from mail.dev.tdt.de (unknown [10.2.4.42]) by securemail.tdt.de (Postfix) with ESMTP id 5DF0A240046; Fri, 6 Mar 2026 09:27:35 +0100 (CET) Received: from [127.0.1.1] (unknown [10.2.3.19]) by mail.dev.tdt.de (Postfix) with ESMTPSA id 41FBA22F1D; Fri, 6 Mar 2026 09:27:35 +0100 (CET) From: Martin Schiller Date: Fri, 06 Mar 2026 09:27:25 +0100 Subject: [PATCH 2/2] x86/cpu/intel: Add EIST workaround for Lightning Mountain. Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260306-cpufreq_lgm-v1-2-47f104aed7c2@dev.tdt.de> References: <20260306-cpufreq_lgm-v1-0-47f104aed7c2@dev.tdt.de> In-Reply-To: <20260306-cpufreq_lgm-v1-0-47f104aed7c2@dev.tdt.de> To: Srinivas Pandruvada , Len Brown , "Rafael J. Wysocki" , Viresh Kumar , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Florian Eckert , Martin Schiller X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772785654; l=1815; i=ms@dev.tdt.de; s=20260220; h=from:subject:message-id; bh=NQZf/OEsxVfNZzzCfUgbDqJjVaITgzeMpP38x6OoxuU=; b=n7kBE45BDvRVzxlmR90+0ENMU4zLf5zMABoNth93V9dE0d0H27WezM9/72+wl+4VpK/mW1MG2 AyU3E4WxRATB/syl3Kl6uV6GHx60WZBuslcTg7OZla+hOgKDs901/Vw X-Developer-Key: i=ms@dev.tdt.de; a=ed25519; pk=MAojd7D5IafMnqCYSFC7hY/u/jppX58CLIEhsEsSOYE= X-purgate: clean X-purgate-ID: 151534::1772785656-09631836-E863CE59/0/0 X-purgate-type: clean Add a workaround for Intel / MaxLinear Lightning Mountain to enable Enhanced Intel SpeedStep Technology (EIST) for each cpu. Otherwise, the frequency on some cpus is locked to the minimum value of 624 MHz. This usually would be the job of the BIOS / bootloader, but U-Boot only enables it on the cpu on which it is running. Signed-off-by: Martin Schiller --- arch/x86/kernel/cpu/intel.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 98ae4c37c93eccf775d5632acf122603a19918a8..e49df04e8d491158cc48f8d8bef= 824c434256d09 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -466,6 +466,29 @@ static void intel_workarounds(struct cpuinfo_x86 *c) #else static void intel_workarounds(struct cpuinfo_x86 *c) { + u64 misc_enable; + + /* + * Intel / MaxLinear Lightning Mountain workaround to enable Enhanced + * Intel SpeedStep Technology (EIST) for each cpu. Otherwise, the + * frequency on some cpus is locked to the minimum value of 624 MHz. + * This usually would be the job of the BIOS / bootloader, but U-Boot + * only enables it on the cpu on which it is running. + */ + if (c->x86_vfm =3D=3D INTEL_ATOM_AIRMONT_NP) { + rdmsrq(MSR_IA32_MISC_ENABLE, misc_enable); + if (!(misc_enable & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) { + misc_enable |=3D MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP; + wrmsrq(MSR_IA32_MISC_ENABLE, misc_enable); + + /* check to see if it was enabled successfully */ + rdmsrq(MSR_IA32_MISC_ENABLE, misc_enable); + if (!(misc_enable & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) { + pr_info("CPU%d: Can't enable Enhanced SpeedStep\n", + c->cpu_index); + } + } + } } #endif =20 --=20 2.47.3